Upper computer system of battery management system

Abstract

The utility model provides an upper computer system of a battery management system. The upper computer system of the battery management system comprises a mainboard, a communication backboard, an acquisition board and a dynamic routing module. Distributed acquisition is realized by arranging a plurality of independent acquisition boards, so that the acquisition efficiency of the system is improved; at least one second communication interface and a signal repeater are arranged on the communication backboard, each acquisition board is connected with the communication backboard through one second communication interface, and the acquisition boards are sequentially connected in series to form a chain through the signal transmission interfaces, so that the average delay of the system is reduced, and the expansibility of the system is improved; according to the method, the paths of different priorities for transmitting data to the mainboard by each acquisition board are pre-configured in the hardware routing table, whether the current path of each acquisition board fails or not is judged, and switching is performed in sequence according to the priorities of the paths in the hardware routing table, so that the fault-tolerant capability of the system is improved.

Description

Technical Field

[0001] This utility model relates to the field of battery management systems, and more particularly to a host computer system for a battery management system. Background Technology

[0002] The existing lithium battery management system host computer mainly adopts the following architecture: (1) centralized acquisition architecture; (2) fixed topology architecture; (3) data synchronization mechanism that relies on the main control board to poll or report data at regular intervals: relying on the main control board to poll or report data at regular intervals.

[0003] In a centralized acquisition architecture, all battery module data is aggregated through a single concentrator (such as a main control board) and then processed by a host computer. This relies on RS485 / CAN bus transmission, but the single-point acquisition bandwidth is limited (such as 500kbps). When the number of modules is greater than 50, the data refresh delay is greater than 200ms.

[0004] In a fixed topology architecture, the battery modules and the host computer are connected in a star or tree pattern. Adding a new module requires rewiring, and the number of new modules is limited by the number of buses (e.g., the CAN bus supports a maximum of 110 nodes), resulting in limited scalability. Furthermore, the host computer is bound to the acquisition module, making it impossible to flexibly adapt to different battery pack specifications (such as voltage range and number of modules).

[0005] The data synchronization mechanism relies on polling or periodic reporting from the main control board. Under high load, data blockage or packet loss may occur, resulting in high-priority data (such as sudden temperature changes) not being uploaded in a timely manner.

[0006] In addition, under the existing architecture of the host computer of the lithium battery management system, failure of the main control board or bus will cause the entire system to crash. When a single acquisition module is damaged, the system needs to be shut down for replacement, which affects the continuity of the system and results in insufficient fault tolerance.

[0007] Therefore, providing a host computer system for a battery management system to address the efficiency, scalability, and fault tolerance issues of centralized architectures has significant application potential. Summary of the Invention

[0008] The technical problem to be solved by this utility model is to provide a host computer system for a battery management system, which improves the system's data acquisition efficiency, scalability, and fault tolerance.

[0009] To address the aforementioned problems, this utility model provides a host computer system for a battery management system, comprising: a main board, the main board including a first communication interface; a communication backplane, the communication backplane being connected to the main board via the first communication interface, the communication backplane including at least one second communication interface and a signal repeater, the signal repeater including a repeater interface; at least one acquisition board, the acquisition board being used to acquire data, each acquisition board being connected to the communication backplane via a second communication interface, the acquisition board including a signal transmission interface, the acquisition boards being sequentially connected in series to form a chain via the signal transmission interface so that the data acquired by the acquisition board is transmitted on the chain, each acquisition board serving as the chain. A node in the chain transmits data to the communication backplane via the relay interface. The path from which the data collected by the acquisition board is transmitted to the host board is the current path of the acquisition board. A dynamic routing module is connected to the communication backplane via the relay interface. The node at the tail of the chain is connected to the dynamic routing module. The dynamic routing module includes a hardware routing table, which is pre-configured with different priority paths for each acquisition board to transmit data to the host board. The dynamic routing module determines whether the current path of the acquisition board is faulty and switches the current path of the acquisition board sequentially according to the priority of the paths in the hardware routing table.

[0010] In some embodiments, the motherboard includes dual power supplies, wherein one power supply serves as the main power supply and the other power supply serves as a hot standby power supply.

[0011] In some embodiments, the first communication interface is a PCIe x16 slot, and the second communication interface is a PCIe x1 slot.

[0012] In some embodiments, the signal transmission interface is a low-voltage differential signal interface; the signal repeater is a low-voltage differential signal repeater; and the repeater interface is a low-voltage differential signal repeater interface.

[0013] In some embodiments, the acquisition board is used to acquire battery data, including battery voltage and battery temperature.

[0014] In some embodiments, the motherboard further includes a programmable integrated circuit coprocessor for processing the acquired parameters.

[0015] In some embodiments, the number of second communication interfaces on the communication backplane is 6, and each second communication interface can be connected to a maximum of 32 acquisition boards.

[0016] In some embodiments, the hardware routing table is configured with the primary path, backup path, and emergency path for the data collected by each acquisition board to be transmitted to the host board.

[0017] In some embodiments, the dynamic routing module further includes a fault detection unit, which determines whether the current path of the acquisition board is faulty through the data verification and timing monitoring. If the current path of the acquisition board is faulty, the current path of the acquisition board is switched sequentially to the next priority path in the hardware routing table.

[0018] The above technical solution provides a host computer system for a battery management system. The host computer system includes a motherboard, a communication backplane, acquisition boards, and a dynamic routing module. Distributed acquisition is achieved by setting up multiple independent acquisition boards, improving the system's acquisition efficiency. By setting at least one second communication interface and a signal repeater on the communication backplane, each acquisition board is connected to the communication backplane through a second communication interface. The acquisition boards are sequentially chained together through the signal transmission interface, reducing the system's average latency and improving its scalability. By pre-configuring different priority paths for each acquisition board to transmit data to the motherboard in the hardware routing table, determining whether the current path of each acquisition board is faulty, and switching paths sequentially according to their priorities in the hardware routing table, the system's fault tolerance is improved.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the present invention. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the overall structure of the host computer system of the battery management system provided in an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of the structure of a motherboard provided in one embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of the structure of a communication backplane provided in one embodiment of the present invention;

[0024] Figure 4This is a schematic diagram of the connection of the first chain provided in an embodiment of the present invention;

[0025] Figure 5 This utility model provides an embodiment of the configuration in the hardware routing table. Figure 4 The path to the acquisition board A3 in the middle. Detailed Implementation

[0026] The technical solutions in the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0027] Please refer to this as well. Figures 1-5 ,in, Figure 1 This is a schematic diagram of the overall structure of the host computer system of the battery management system provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a motherboard provided in one embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a communication backplane provided in one embodiment of the present invention; Figure 4 This is a schematic diagram of the connection of the first chain provided in an embodiment of the present invention; Figure 5 This utility model provides an embodiment of the configuration in the hardware routing table. Figure 4 The path to the acquisition board A3 in the middle.

[0028] like Figure 1 As shown, the host computer system of the battery management system includes: a main board 11, a communication backplane 12, a data acquisition board 13, and a dynamic routing module 14. Figure 1 The direction of the middle arrow indicates the direction of data transmission.

[0029] The mainboard 11 is the intelligent control center of the host computer system. The mainboard 11 is used to monitor various operating parameters in real time and to process and display the collected parameters. For example... Figure 2 As shown, the motherboard 11 includes a first communication interface 111. In this embodiment, the first communication interface 111 is a PCIe (PCI Express) x16 slot, which includes 16 pairs of differential signal lines. Each pair of differential signal lines includes a transmit line and a receive line, supporting full-duplex communication.

[0030] The motherboard 11 includes dual power supplies 112, where one power supply serves as the main power supply and the other as a hot standby power supply. When the main power supply fails, the hot standby power supply can seamlessly switch over, ensuring that the system interruption time is less than 1 millisecond.

[0031] In this embodiment, the motherboard 11 also includes a programmable gate array (FPGA) coprocessor (not shown) for processing the acquired parameters.

[0032] The communication backplane 12 is connected to the motherboard 11 via the first communication interface 111. Specifically, the communication backplane 12 is connected to the motherboard 11 via a PCIe x16 slot.

[0033] like Figure 3 As shown, the communication backplane 12 includes at least one second communication interface 121, which is a PCIe x1 slot supporting hot-swapping. In this embodiment, the number of second communication interfaces 121 on the communication backplane 12 is six.

[0034] The communication backplane 12 includes a signal repeater 122, which includes a repeater interface. The signal repeater 122 is a Low-Voltage Differential Signaling (LVDS) repeater, and the repeater interface is an LVDS repeater interface. The signal repeater 122 is used for signal amplification, shaping, and cross-node transmission, and can realize differential signal driving, signal attenuation compensation, and electrical isolation.

[0035] The acquisition board 13 is an embedded development board, and there is at least one. The acquisition board 13 is used to acquire data, and each acquisition board 13 is connected to the communication backplane 12 through a second communication interface 121. In this embodiment, the acquisition board 13 is used to acquire battery data, which includes battery voltage and battery temperature. Specifically, the battery data includes the voltage and charging / discharging current of individual cells.

[0036] The acquisition board 13 includes a signal transmission interface. The acquisition boards 13 are sequentially connected in series to form a chain through the signal transmission interface so that the data acquired by the acquisition boards 13 can be transmitted on the chain. Each acquisition board 13 serves as a node in the chain. The data transmitted on the chain is transmitted to the communication backplane 12 through the relay interface. The signal transmission interface is a low voltage differential signaling (LVDS) interface.

[0037] Furthermore, the data collected by the acquisition board 13 can be transmitted to the communication backplane 12 through the relay interface, and the communication backplane 12 transmits the data to the host board 11 through the first communication interface 111. In this embodiment, the data collected by the acquisition board 13 can be transmitted to the communication backplane 12 through the LVDS interface, and the communication backplane 12 transmits the data to the host board 11 through the PCIe x16 slot.

[0038] like Figure 1 As shown, the four acquisition boards 13 are sequentially connected in series to form a first chain 15 via the signal transmission interface. The bandwidth of the first chain 15 can reach 1Gbps, while the bandwidth of the CAN bus used in the prior art is 1Mbps. The method of this application can increase the bandwidth by 1000 times. Furthermore, all three acquisition boards 13 are connected to the communication backplane 12 of the previous level. This forms a daisy-chain topology. When a new module and an additional acquisition board 13 are needed, the new acquisition board 13 can be added by connecting it to the end of the first chain 15. In this embodiment, each second communication interface 121 can be connected to a maximum of 32 acquisition boards 13, and correspondingly, the first chain 15 includes a maximum of 32 nodes.

[0039] Figure 1 Three additional acquisition boards 13 are connected in series to form a second chain 16. The first chain 15 and the second chain 16 are connected to the communication backplane 12 through different second communication interfaces 121.

[0040] In this embodiment, the number of second communication interfaces 121 on the communication backplane 12 is 6, and correspondingly, the communication backplane 12 can be connected to a maximum of 6 acquisition boards 13. That is to say, in this embodiment, the host board 11 can be connected to a maximum of 192 (6×32) nodes, enhancing the scalability of the host computer system of the battery management system.

[0041] The path by which the data collected by the acquisition board 13 is transmitted to the host board 11 is the current path of the acquisition board 11. In other words, the data collected by the acquisition board 13 is transmitted to the host board 11 through the current path.

[0042] The dynamic routing module 14 is connected to the communication backplane 12 through the relay interface. The node at the tail of the chain is connected to the dynamic routing module 14. The dynamic routing module 14 includes a hardware routing table. The hardware routing table is pre-configured with different priority paths for each acquisition board 13 to transmit data to the host board 11. The dynamic routing module 14 determines whether the current path of the acquisition board 13 has failed and switches the current path of the acquisition board 13 sequentially according to the priority of the path in the hardware routing table.

[0043] The dynamic routing module 14 further includes a fault detection unit. This unit determines whether the current path of the acquisition board 13 has failed through data verification and timing monitoring. If the current path of the acquisition board 13 fails, the current path of the acquisition board 13 is switched sequentially to the next priority path in the hardware routing table. In this embodiment, Cyclic Redundancy Check 32 (CRC32) is used for data verification.

[0044] The host computer system of the battery management system includes multiple acquisition boards 13 on the same chain or different chains. The hardware routing table is configured with the main path, backup path and emergency path for the data transmitted from each acquisition board 13 to the host board 11.

[0045] The following is a detailed explanation. (Reference) Figure 1 and Figure 4 The communication backplane 12 is connected to the host board 11 via the first communication interface 111. The first chain 15 includes four acquisition boards 13, which are connected in series via the signal transmission interface and all connected to the communication backplane 12 via the second communication interface 121. Figure 4 As shown, host board B represents host board 11, communication backplane C represents communication backplane 12, dynamic routing D represents dynamic routing module 14, and acquisition boards A1, A2, A3, and A4 represent each of the acquisition boards 13 in the first chain 15. The dynamic routing D also includes a fault detection unit, which determines whether a fault has occurred in the current path of acquisition board A3 through data verification and timing monitoring.

[0046] like Figure 5As shown, the paths configured in the hardware routing table for acquisition board A3 include: Primary path: Acquisition board A3 -> Communication backplane C -> Mainboard B; Backup path: Acquisition board A3 -> Acquisition board A4 -> Communication backplane C -> Mainboard B; Emergency path: Acquisition board A3 -> Dynamic route D -> Communication backplane C -> Mainboard B. The paths are prioritized according to their latency. For example, the latency of the three paths increases sequentially, and correspondingly, their priority decreases sequentially. In the primary path, data from acquisition board A3 can be directly transmitted to the communication backplane C, resulting in the lowest data transmission latency. Under normal system conditions, this primary path is used by default as the current path for acquisition board A3.

[0047] Continue with Figure 4 For the A3 acquisition board in the middle, if Figure 4 The system is running normally and adopts Figure 5 The primary path configured in the hardware routing table is used as the current path of the acquisition board A3. If the fault detection unit fails to perform CRC32 three times on the current path of the acquisition board A3, it is determined that the current path of the acquisition board A3 has failed, and the dynamic routing D triggers a switch to the current path of the acquisition board A3. Figure 5 The backup path configured in the hardware routing table; after the current path is switched, if the fault detection unit finds that the latency of the current path of the acquisition board A3 has timed out during timing monitoring, then the current path of the acquisition board A3 will be switched sequentially to a lower priority path. Figure 5 The emergency path is configured in the hardware routing table.

[0048] In some embodiments, the hardware routing table is further configured with cross-chain paths for the data collected by each acquisition board 13 to be transmitted to the host board 11. These cross-chain paths utilize cross-chain detours to transmit the data collected by the acquisition board 13 to the host board. The transmission latency of these cross-chain paths is typically higher; correspondingly, their priority is lower than that of the emergency path. The cross-chain path is only used as the current path for the acquisition board 13 when the emergency path also fails.

[0049] The above technical solution provides a host computer system for a battery management system. The host computer system includes a motherboard, a communication backplane, acquisition boards, and a dynamic routing module. Distributed acquisition is achieved by setting up multiple independent acquisition boards, improving the system's acquisition efficiency. By setting at least one second communication interface and a signal repeater on the communication backplane, each acquisition board is connected to the communication backplane through a second communication interface. The acquisition boards are sequentially chained together through the signal transmission interface, reducing the system's average latency and improving its scalability. By pre-configuring different priority paths for each acquisition board to transmit data to the motherboard in the hardware routing table, determining whether the current path of each acquisition board is faulty, and switching paths sequentially according to their priorities in the hardware routing table, the system's fault tolerance is improved.

[0050] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion. The various embodiments in this specification are described in a related manner, and similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments.

[0051] The above description is merely a preferred embodiment of this utility model and is not intended to limit the scope of protection of this utility model. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of this utility model, and these improvements and modifications should also be considered within the scope of protection of this utility model.

Claims

1. A host computer system for a battery management system, characterized in that, include: A motherboard, the motherboard including a first communication interface; A communication backplane is provided, connected to the host board via the first communication interface. The communication backplane includes at least one second communication interface and a signal repeater, the signal repeater including a repeater interface. At least one acquisition board is provided, used for data acquisition. Each acquisition board is connected to the communication backplane via a second communication interface, and each acquisition board includes a signal transmission interface. The acquisition boards are sequentially connected in series via the signal transmission interfaces to transmit the data acquired by the acquisition boards on the chain. Each acquisition board serves as a node in the chain, and the data transmitted on the chain is transmitted to the host board via the repeater interface. The communication backplane, the path of the data collected by the acquisition board to the host board is the current path of the acquisition board; the dynamic routing module, the dynamic routing module is connected to the communication backplane through the relay interface, the end node of the chain is connected to the dynamic routing module, the dynamic routing module includes a hardware routing table, the hardware routing table is pre-configured with different priority paths for each acquisition board to transmit data to the host board, the dynamic routing module determines whether the current path of the acquisition board is faulty and switches the current path of the acquisition board in sequence according to the priority of the path in the hardware routing table.

2. The host computer system according to claim 1, characterized in that, The motherboard includes dual power supplies, one of which serves as the main power supply and the other as a hot standby power supply.

3. The host computer system according to claim 1, characterized in that, The first communication interface is a PCIe x16 slot, and the second communication interface is a PCIe x1 slot.

4. The host computer system according to claim 1, characterized in that, The signal transmission interface is a low-voltage differential signal interface; the signal repeater is a low-voltage differential signal repeater; and the repeater interface is a low-voltage differential signal repeater interface.

5. The host computer system according to claim 1, characterized in that, The acquisition board is used to collect battery data, including battery voltage and battery temperature.

6. The host computer system according to claim 1, characterized in that, The motherboard also includes a programmable integrated circuit coprocessor for processing the acquired parameters.

7. The host computer system according to claim 1, characterized in that, The number of second communication interfaces on the communication backplane is 6, and each second communication interface can be connected to a maximum of 32 acquisition boards.

8. The host computer system according to claim 1, characterized in that, The hardware routing table is configured with the primary path, backup path, and emergency path for the data collected by each acquisition board to be transmitted to the host board.

9. The host computer system according to claim 1, characterized in that, The dynamic routing module also includes a fault detection unit. The fault detection unit determines whether the current path of the acquisition board is faulty through the data verification and timing monitoring. If the current path of the acquisition board is faulty, the current path of the acquisition board is switched to the next priority path in the hardware routing table.

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