Low driving voltage trench gate silicon carbide VDMOS

Abstract

The utility model provides a kind of low drive voltage trench gate silicon carbide VDMOS, comprising: drift layer is connected to silicon carbide substrate;Drift layer is equipped with protruding part, and recess is equipped in protruding part;P-type trap area is connected to drift layer, and P-type trap area is connected to protruding part;P-type base area is connected to P-type trap area, and P-type base area is connected to protruding part;P-type source area is connected to P-type base area;N-type source area is connected to P-type base area, and N-type source area is connected to P-type source area, and N-type source area is connected to protruding part;Mask layer is located in recess;Insulating medium layer is located in recess, and insulating medium layer is connected to mask layer;Insulating medium layer protrudes from recess, and groove is equipped in insulating medium layer;Gate metal layer is located in groove;Source metal layer is connected protruding part, P-type source area and N-type source area respectively;Drain metal layer is connected to silicon carbide substrate, reduce device drive voltage, reduce device drive loss. Improve device reliability.

Description

Technical Field

[0001] This utility model relates to a low-drive-voltage trench-gate silicon carbide VDMOS. Background Technology

[0002] Due to its wide bandgap characteristics, silicon carbide VDMOS devices naturally possess lower gate charge and higher switching speed compared to SiVDMOS devices. However, due to the bandgap relationship between its width and the insulating dielectric silicon dioxide, silicon carbide VDMOS devices generally require a gate drive voltage of 15V to achieve full conduction and the lowest on-resistance. However, due to the poor quality of the insulating dielectric silicon dioxide, the device has low gate withstand voltage, and high drive voltages can easily lead to gate reliability issues. Utility Model Content

[0003] The technical problem this invention aims to solve is to provide a low-drive-voltage trench-gate silicon carbide VDMOS that can achieve full conduction at a gate drive voltage of 12V, thereby reducing the device drive voltage, reducing device drive losses, and improving device reliability.

[0004] This invention provides a low-drive-voltage trench-gate silicon carbide VDMOS, comprising:

[0005] silicon carbide substrate,

[0006] A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate; the drift layer has a protrusion, and the protrusion has a groove;

[0007] The lower side of the P-type well region is connected to the upper side of the drift layer, and the inner side of the P-type well region is connected to the outer side of the protrusion.

[0008] The lower side of the P-type base region is connected to the upper side of the P-type well region, and the inner side of the P-type base region is connected to the outer side of the protrusion.

[0009] P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the P-type base region;

[0010] The N-type source region has its lower side connected to the upper side of the P-type base region, its outer side connected to the inner side of the P-type source region, and its inner side connected to the outer side of the protrusion.

[0011] A masking layer is disposed within the groove;

[0012] An insulating dielectric layer is disposed within the groove, and the lower side of the insulating dielectric layer is connected to the upper side of the masking layer; the insulating dielectric layer protrudes from the groove, and grooves are provided within the insulating dielectric layer;

[0013] A gate metal layer is disposed within the trench;

[0014] A source metal layer, wherein the source metal layer is respectively connected to the upper side of the protrusion, the upper side of the P-type source region and the upper side of the N-type source region;

[0015] And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

[0016] The advantages of this utility model are:

[0017] I. This invention constructs a P-type base region and a P-type well region with gradually decreasing concentration gradients. The highly doped P-type base region ensures that the space charge region formed by the N-type source region and the P-type well region does not affect the diffusion of the space charge region to the device gate in the lateral direction, thus ensuring the gate-controlled turn-off characteristics of the device. The P-type base region shields the space charge region of the N-type source region. The space charge region formed at the bottom of the low-doped P-type well region ensures the gate turn-off characteristics of the device. During reverse breakdown, the two-layer P-type doped structure can form a structure with a gradually increasing electric field near the N-type source region of the device, thereby improving the breakdown voltage capability of the source region of the device.

[0018] 2. The N-type source region, P-type base region, and P-type well region are not directly connected to the insulating dielectric layer. A drift layer is placed between them. The space charge region is formed between the P-type well region and the drift layer through the P-type base region and the drift layer, which realizes the turn-off during reverse breakdown. The gap structure can reduce the inversion driving voltage, thereby reducing the driving voltage of the device.

[0019] Third, in order to ensure the reliability of the device's gate, a masking layer of the same width as the insulating dielectric layer is constructed directly below the device's insulating dielectric layer to avoid the influence of the device's gate structure when the device is reverse withstand voltage. Attached Figure Description

[0020] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0021] Figure 1 This is a schematic diagram of a low-drive-voltage trench-gate silicon carbide VDMOS according to this utility model.

[0022] Figure 2 This is a cross-sectional view of the process of a low-drive-voltage trench-gate silicon carbide VDMOS according to this utility model. Figure 1 .

[0023] Figure 3 This is a cross-sectional view of the process of a low-drive-voltage trench-gate silicon carbide VDMOS according to this utility model. Figure 2 .

[0024] Figure 4This is a cross-sectional view of the process of a low-drive-voltage trench-gate silicon carbide VDMOS according to this utility model. Figure 3 .

[0025] Figure 5 This is a cross-sectional view of the process of a low-drive-voltage trench-gate silicon carbide VDMOS according to this utility model. Figure 4 .

[0026] Figure 6 This is a cross-sectional view of the process of a low-drive-voltage trench-gate silicon carbide VDMOS according to this utility model. Figure 5 .

[0027] Figure 7 This is a cross-sectional view of the process of a low-drive-voltage trench-gate silicon carbide VDMOS according to this utility model. Figure 6 .

[0028] Figure 8 This is a cross-sectional view of the process of a low-drive-voltage trench-gate silicon carbide VDMOS according to this utility model. Figure 7 .

[0029] Figure 9 This is a cross-sectional view of the process of a low-drive-voltage trench-gate silicon carbide VDMOS according to this utility model. Figure 8 .

[0030] Figure 10 This is a cross-sectional view of the process of a low-drive-voltage trench-gate silicon carbide VDMOS according to this utility model. Figure 9 .

[0031] Figure 11 This is a cross-sectional view of the process of a low-drive-voltage trench-gate silicon carbide VDMOS according to this utility model. Figure 10 .

[0032] Figure 12 This is a cross-sectional view of the process of a low-drive-voltage trench-gate silicon carbide VDMOS according to this utility model. Figure 10 one. Detailed Implementation

[0033] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0037] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0038] like Figure 1 As shown, this application embodiment provides a low-drive-voltage trench-gate silicon carbide VDMOS, comprising:

[0039] Silicon carbide substrate 101,

[0040] A drift layer 102 is provided, the lower side of which is connected to the upper side of the silicon carbide substrate 101; a protrusion 1021 is provided on the drift layer 102, and a groove (not shown in the figure) is provided in the protrusion 1021.

[0041] P-type well region 103, the lower side of the P-type well region 103 is connected to the upper side of the drift layer 102, and the inner side of the P-type well region 103 is connected to the outer side of the protrusion 1021.

[0042] P-type base region 104, the lower side of the P-type base region 104 is connected to the upper side of the P-type well region 103, and the inner side of the P-type base region 104 is connected to the outer side of the protrusion 1021.

[0043] P-type source region 105, the lower side of which is connected to the upper side of P-type base region 104;

[0044] N-type source region 106, the lower side of the N-type source region 106 is connected to the upper side of the P-type base region 104, the outer side of the N-type source region 106 is connected to the inner side of the P-type source region 105, and the inner side of the N-type source region 106 is connected to the outer side of the protrusion 1021.

[0045] A masking layer 107 is disposed within the groove;

[0046] An insulating dielectric layer 108 is disposed within the groove, and the lower side of the insulating dielectric layer 108 is connected to the upper side of the masking layer 107; the insulating dielectric layer 108 protrudes from the groove, and a groove 1081 is provided within the insulating dielectric layer 108;

[0047] A gate metal layer 109 is disposed within the trench 1081;

[0048] Source metal layer 110, which is connected to the upper side of the protrusion 1021, the upper side of the P-type source region 105 and the upper side of the N-type source region 106 respectively.

[0049] And a drain metal layer 111, which is connected to the lower side of the silicon carbide substrate 101.

[0050] In this embodiment, preferably, the distance between the inner side of the P-type well region 103 and the outer side of the insulating dielectric layer 108 is greater than the distance between the inner side of the P-type base region 104 and the outer side of the insulating dielectric layer 108.

[0051] In this embodiment, preferably, the lower side surface of the gate metal layer 109 and the lower side surface of the P-type well region 103 are located on the same plane.

[0052] In this embodiment, preferably, the doping concentration of the P-type base region 104 is greater than the doping concentration of the P-type well region 103.

[0053] In this embodiment, preferably, the doping concentration of the P-type well region 103 is greater than the doping concentration of the drift layer 102.

[0054] In this embodiment, preferably, the doping concentration of the P-type source region 105 is greater than the doping concentration of the N-type source region 106.

[0055] like Figures 1 to 12 As shown, the fabrication method of the above-mentioned trench-gate silicon carbide VDMOS includes the following steps:

[0056] Step 1: Deposit metal on the lower side of silicon carbide substrate 101 to form drain metal layer 111; epitaxially grow on the upper side of silicon carbide substrate 101 to form drift layer 102;

[0057] Step 2: Form a barrier layer 100 above the drift layer 102, etch the barrier layer 100 to form a via, and implant ions to form a masking layer 107.

[0058] Step 3: Remove the barrier layer 100 from Step 2, reform the barrier layer 100, etch the barrier layer 100 to form a via, and implant ions to form a P-type well region 103.

[0059] Step 4: Remove the barrier layer 100 from Step 3, reform the barrier layer 100, etch the barrier layer 100 to form a via, and implant ions to form a P-type base region 104.

[0060] Step 5: Remove the barrier layer 100 from step 4, reform the barrier layer 100, etch the barrier layer 100 to form a via, and implant ions to form a P-type source region 105.

[0061] Step 6: Remove the barrier layer 100 from step 5, reform the barrier layer 100, etch the barrier layer 100 to form a via, and implant ions to form an N-type source region 106.

[0062] Step 7: Remove the barrier layer 100 from step 6, reform the barrier layer 100, etch the barrier layer 100 to form a via, etch the drift layer 102 to the upper side of the N-type source region 106, deposit metal, and form the source metal layer 110.

[0063] Step 8: Remove the barrier layer 100 from step 7, reform the barrier layer 100, etch the barrier layer 100 to form a via, and etch the drift layer 102 to the upper side of the masking layer 107, and deposit to form an insulating dielectric layer 108.

[0064] Step 9: Remove the barrier layer 100 from step 8, reform the barrier layer 100, etch the barrier layer 100 to form a via, etch the insulating dielectric layer 108 to form a trench 1081, deposit metal to form a gate metal layer 109, remove the barrier layer 100, and complete the fabrication.

[0065] In another embodiment of this invention, the silicon carbide substrate 101 and the drift layer 102 are N-type, and the masking layer 107 is P-type; the doping concentration of the silicon carbide substrate 101 is 2-8e18cm. -3 The doping concentration of drift layer 102 is 6-10e15cm. -3 The doping concentration of the masking layer 107 is 1-5e16cm. -3 The doping concentration of the P-type well region 103 is 1-5e17cm. -3 The doping concentration of the P-type base region 104 is 1-5e18cm. -3 The doping concentration of the P-type source region 105 is 1-5e19cm. -3 The doping concentration of the N-type source region 106 is 2-8e18cm. -3 The insulating dielectric layer 108 can be made of silicon dioxide;

[0066] The doping concentration of the silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 111, reducing the overall on-resistance of the device. The doping concentration of the drift layer 102 is a trade-off between the reverse breakdown voltage and the on-resistance of the device. The doping concentration of the masking layer 107 is to improve the reliability of the bottom of the insulating dielectric layer 108, ensure that the leakage current is sufficiently small during reverse breakdown, shield the capacitance from the gate to the drain, and reduce the Miller capacitance of the device. The doping concentration of the P-type well region 103 is designed to protect the source of the device and ensure the low drive voltage characteristics of the gate control region. The doping concentration of the P-type base region 104 is to reduce the downward extension of the space charge region formed by the N-type source region 106 and ensure the turn-off characteristics of the device. The doping concentration of the P-type source region 105 is designed to reduce the loss of the parasitic pn junction diode. The doping concentrations of the N-type source region 106 and the P-type source region 105 are designed to reduce the contact resistance of the device, thereby reducing the on-resistance of the device.

[0067] The silicon carbide substrate 101 of the device has a thickness of 1 μm to ensure support during device fabrication. The drift layer 102 has a thickness of 50-100 μm, adjusted within this range according to different requirements for the device's breakdown voltage characteristics. The source metal layer 110 has a thickness of 300 nm, the P-type well region 103 has a thickness of 500 nm and a width of 1.12 μm, the P-type base region 104 has a thickness of 300 nm and a width of 1.15 μm, the P-type source region 105 has a thickness of 200 nm and a width of 600 nm, the N-type source region 106 has a thickness of 200 nm and a width of 550 nm, the insulating dielectric layer 108 has a width of 1.2 μm, the gate metal layer 109 has a width of 1.1 μm, a thickness of 1.4 μm, and the bottom insulating dielectric layer of the gate metal layer 109 has a thickness of [missing information]. The width of the gate metal layer 109 is 100nm, the width of the insulating dielectric on both sides is 50nm, the width of the masking layer 107 is 1.2μm, and the thickness is 200nm. The tops of the N-type source region 106 and the P-type source region 105 are in direct contact with the source metal layer 110. The top of the P-type base region 104 is in direct contact with the N-type source region 106 and the P-type source region 105. The top of the P-type well region 103 is in direct contact with the top of the P-type base region 104. The P-type source region 105, the P-type base region 104, and the P-type well region 103 are aligned on the side away from the device gate. The device masking layer 107 is in direct contact with the bottom of the device insulating dielectric layer 108. The width, thickness, and relative relationship of the above structure are to construct a low drive voltage structure for the device. Its interaction with the doping concentration can achieve a low drive voltage for the device under low reverse leakage current conditions, thereby improving device performance and reliability.

[0068] This invention constructs a P-type base region 104 and a P-type well region 103 with gradually decreasing concentration gradients. The highly doped P-type base region 104 ensures that the space charge region formed by the N-type source region 106 in the vertical direction does not affect the diffusion of the space charge region to the device gate in the lateral direction, thus ensuring the gate-controlled turn-off characteristics of the device. The P-type base region 104 also shields the space charge region of the N-type source region 106. The space charge region formed at the bottom of the low-doped P-type well region 103 in the P-type base region 104 ensures the gate turn-off characteristics of the device. With the gradually decreasing concentration gradients of the P-type base region 104 and P-type well region 103, during reverse breakdown voltage testing, the two P-type doped structures can form a structure with a gradually increasing electric field near the N-type source region 106, thereby improving the breakdown voltage capability of the device source region.

[0069] An N-type source region 106 and a P-type base region 104 are formed on the left and right sides of the device, with a distance of 50 nm from the insulating dielectric layer 108. This part is the drift layer 102. The P-type well region 103 below the P-type base region 104 is 80 nm away from the insulating dielectric layer 108, forming a trapezoidal structure with increased gap. This structure forms a space charge region with the P-type well region 103 and the P-type base region 104 and the drift layer 102 in the gap, realizing turn-off during reverse withstand voltage. The gap structure can reduce the inversion drive voltage, thereby reducing the drive voltage of the device. This structure is designed to reduce the drive charge in the part far away from the N-type source region 106 and reduce switching losses.

[0070] To ensure the reliability of the device's gate, a 200nm thick masking layer 107 with the same width as the insulating dielectric layer 108 is constructed directly below the device's insulating dielectric layer 108 to avoid the influence of the device's gate structure during reverse breakdown voltage.

[0071] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A low-drive-voltage trench-gate silicon carbide VDMOS, characterized in that: include: silicon carbide substrate, A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate; the drift layer has a protrusion, and the protrusion has a groove; The lower side of the P-type well region is connected to the upper side of the drift layer, and the inner side of the P-type well region is connected to the outer side of the protrusion. The lower side of the P-type base region is connected to the upper side of the P-type well region, and the inner side of the P-type base region is connected to the outer side of the protrusion. P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the P-type base region; The N-type source region has its lower side connected to the upper side of the P-type base region, its outer side connected to the inner side of the P-type source region, and its inner side connected to the outer side of the protrusion. A masking layer is disposed within the groove; An insulating dielectric layer is disposed within the groove, and the lower side of the insulating dielectric layer is connected to the upper side of the masking layer; the insulating dielectric layer protrudes from the groove, and grooves are provided within the insulating dielectric layer; A gate metal layer is disposed within the trench; A source metal layer, wherein the source metal layer is respectively connected to the upper side of the protrusion, the upper side of the P-type source region and the upper side of the N-type source region; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

2. The low-drive-voltage trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The distance between the inner side of the P-type well region and the outer side of the insulating dielectric layer is greater than the distance between the inner side of the P-type base region and the outer side of the insulating dielectric layer.

3. The low-drive-voltage trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The lower side of the gate metal layer is located on the same plane as the lower side of the P-type well region.

4. The low-drive-voltage trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the P-type base region is greater than the doping concentration of the P-type well region.

5. A low-drive-voltage trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the P-type well region is greater than that of the drift layer.

6. A low-drive-voltage trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the P-type source region is greater than that of the N-type source region.

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