A DFN lead frame and integrated package module

By employing a symmetrical design and semi-etching technology with a DFN lead frame, the issues of moisture intrusion and material cost in miniaturized optocoupler products are resolved, resulting in a packaging structure with high reliability and high space utilization.

CN224306313UActive Publication Date: 2026-05-29四川明泰微电子有限公司

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
四川明泰微电子有限公司
Filing Date
2025-08-07
Publication Date
2026-05-29

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Abstract

A DFN lead frame and an integrated package module, the package unit of the lead frame comprises a base island arranged in the middle region along the width direction of the package unit, a first pin and a second pin spaced on one side of the base island, and a third pin and a fourth pin spaced on the other side of the base island, the first pin and the second pin are spaced, and the third pin and the fourth pin are spaced. The integrated package module comprises a plastic package shell and a DFN lead frame, a light sensing control chip is arranged on the first pin, the second pin and the base island, a first MOS chip is arranged on the fourth pin, a second MOS chip is arranged on the third pin, an LED chip is arranged on the light sensing control chip, and the plastic package shell wraps the package unit and the chips. The layout of the base island and the pins facilitates the integration of multiple chips and realizes electrical spacing, and is beneficial to maintaining the consistency of the bonding wire during later packaging; the pins and the base island are provided with chips, the pins are provided with chips, and the chips are stacked, which improves the utilization rate of small space and has high integration.
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Description

Technical Field

[0001] This application relates to semiconductor technology, specifically to a DFN lead frame and integrated packaging module. Background Technology

[0002] Most existing miniaturized optocoupler products use the LGA package form factor. LGA packaged products use a substrate, resulting in high material costs. Because the molding compound is only bonded to the substrate top and bottom, it cannot effectively prevent moisture intrusion, making it difficult to achieve high reliability levels. Therefore, it is necessary to develop optocoupler products with other packaging forms to improve the stability and reliability of the packaging structure while meeting miniaturization requirements. This requires simultaneous design considerations for both the lead frame structure and the package body structure. Utility Model Content

[0003] To meet the needs of existing product development, this application provides a DFN lead frame and integrated packaging module. By placing a base island in the middle of a single packaging unit and distributing four spaced pins on both sides of the base island, electrical spacing is achieved, which is conducive to maintaining the consistency of bonding wires during packaging. Furthermore, by having two pins on one side share a chip with the base island and two pins on the other side have separate chips, the utilization rate of the small space is improved, the integration is high, and it is suitable for packaging miniaturized optocoupler products.

[0004] To achieve the above objectives, the present invention employs the following technology:

[0005] A DFN lead frame includes packaging units formed in a rectangular array on the frame body. The packaging unit includes a base island arranged in the middle region along the width direction of the packaging unit, a first pin and a second pin spaced apart on one side of the base island, and a third pin and a fourth pin spaced apart on the other side of the base island. The first pin and the second pin are spaced apart, and the third pin and the fourth pin are spaced apart. At least a portion of the back of the base island and at least one of the first pin, the second pin, the third pin and the fourth pin is a semi-etched area. After packaging, the bottom surface of each pin is exposed.

[0006] Furthermore, the first pin, second pin, third pin, and fourth pin are arranged along the length of the package unit.

[0007] Furthermore, the first and second pins extend from one end of the package unit along its length and are connected to the frame body via connecting ribs, while the third and fourth pins extend from the other end of the package unit along its length and are connected to the frame body via connecting ribs.

[0008] Furthermore, the first and fourth pins extend out from one side of the package unit along its length and are connected to the frame body via connecting ribs, while the second and third pins extend out from the other side of the package unit along its length and are connected to the frame body via connecting ribs.

[0009] Furthermore, the two ends of the base island extend to both sides of the packaging unit along its length and are connected to the main frame body by connecting ribs.

[0010] Furthermore, at least a portion of the back of the base island, the first pin, the second pin, the third pin, and the fourth pin is a semi-etched area.

[0011] An integrated packaging module includes a plastic shell and the DFN lead frame. A photosensitive control chip is disposed on the first pin, the second pin and the base island. A first MOS chip is disposed on the fourth pin and a second MOS chip is disposed on the third pin. An LED chip is disposed on the photosensitive control chip. The plastic shell encapsulates the packaging unit and each chip, and the bottom surface of each pin is exposed outside the plastic shell.

[0012] The beneficial effects of this utility model are as follows:

[0013] 1. The packaging unit of the DFN lead frame is designed. It forms an overall symmetrical structure design through the layout of a central base island and four pins distributed on both sides. This not only facilitates the integration of multiple chips and achieves electrical spacing, but also helps to maintain the consistency of bonding wires during later packaging.

[0014] 2. The integrated packaging module formed by the DFN lead frame of this utility model makes full use of the fact that two pins and the base island share a chip, and then stack chips on this chip, and then set chips separately on other pins, which improves the utilization rate of narrow space, realizes the integration of more chips in limited space, and, based on the symmetrical layout of the pin and base island positions, facilitates the consistency of the bonding wire length between the photosensitive control chip and the dual MOS chip after bonding connection, thereby improving the electrical performance of the product.

[0015] 3. By setting semi-etching around the base island and pins, a stepped design is formed, which can effectively grip and hold the molding compound, enhance the bonding force between the molding compound and the base island, reduce the risk of delamination, and change the moisture intrusion path to a right angle, blocking moisture intrusion and improving reliability requirements; and optionally, a heat sink without semi-etching can be left on the back of the base island to adapt to higher heat dissipation requirements according to application needs, and also optimize the stability of the base island bonding operation.

[0016] 4. The DFN shape used in this utility model is similar to that of LGA, and a frame with lower material cost is used to form a PIN TO PIN DFN frame and packaging structure to replace the existing product. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall partial structure of the DFN lead frame according to an embodiment of this application.

[0018] Figure 2This is a schematic diagram of an example of the packaging unit in an embodiment of this application.

[0019] Figure 3 This is a schematic diagram of another example of the packaging unit in this application.

[0020] Figure 4 This is a schematic diagram of the chip arrangement and bonding connection inside the integrated packaging module of this application embodiment. Detailed Implementation

[0021] To make the objectives, technical solutions and advantages of the present utility model clearer, the implementation methods of the present utility model will be described in detail below with reference to the accompanying drawings. However, the embodiments described in the present utility model are only some embodiments of the present utility model, and not all embodiments.

[0022] One aspect of this application provides a DFN lead frame, such as... Figure 1 As shown, it includes encapsulation units formed in a rectangular array on the frame body.

[0023] Specifically, such as Figure 2 As shown, the packaging unit includes a base island A5 arranged in the middle region along the width direction of the packaging unit, a first pin A1 and a second pin A2 spaced apart on one side of the base island A5, and a third pin A3 and a fourth pin A4 spaced apart on the other side of the base island A5. The first pin A1 and the second pin A2 are spaced apart, and the third pin A3 and the fourth pin A4 are spaced apart. The overall structure of the packaging unit is symmetrical. It can be seen that the first pin A1 and the second pin A2 are located in the left part of the packaging unit, and the third pin A3 and the fourth pin A4 are located in the right part of the packaging unit.

[0024] As a more specific implementation method, the first pin A1, the second pin A2, the third pin A3, and the fourth pin A4 are arranged along the length direction of the packaging unit. The first pin A1 and the second pin A2 extend out from one end of the length direction of the packaging unit, and the third pin A3 and the fourth pin A4 extend out from the other end of the length direction of the packaging unit. The first pin A1 and the fourth pin A4 extend out from one side of the length direction of the packaging unit, and the second pin A2 and the third pin A3 extend out from the other side of the length direction of the packaging unit. The length direction of the base island A5 is consistent with the width direction of the packaging unit. The two ends of the base island A5 extend out from both sides of the length direction of the packaging unit and are connected to the frame body by connecting ribs. After packaging, the bottom surface of each pin is exposed.

[0025] To improve the adhesion between the molding compound and the frame during packaging and reduce the risk of delamination, at least a portion of the back surface of the base island A5 and at least one of the four pins is partially etched. The stepped design created by the partial etching effectively grips and secures the molding compound, and changes the moisture intrusion path to a right angle, thus blocking moisture penetration. Preferably, at least a portion of the back surface of the base island A5 and the first pin A1, second pin A2, third pin A3, and fourth pin A4 is partially etched.

[0026] Optionally, the entire back of the A5 island can be partially etched, such as... Figure 2 As shown; alternatively, the middle area on the back of the base island A5 can be designated as heatsink A6, with the area outside heatsink A6 being a semi-etched area, as shown. Figure 3 As shown, after encapsulation, heat sink A6 is exposed. The design of heat sink 6 is to adapt to higher heat dissipation requirements according to application needs, and also to optimize the stability of base island wire bonding operations.

[0027] Optional, such as Figure 2 As shown, the back side of the first pin A1 and the second pin A2 adjacent to each other, the back side of the third pin A3 and the fourth pin A4 adjacent to each other, and the back side of each pin extending outward from the package unit have a half-etched area.

[0028] The packaging unit in this example can form a conventional layout of 38 rows and 89 columns on the frame body, which follows the existing DFN frame layout. A large number of jigs and molds are compatible, reducing the equipment investment cost caused by the frame design.

[0029] In another aspect of this application, an integrated packaging module is provided, including a plastic casing and the DFN lead frame described in the previous embodiment. A photosensitive control chip 1 is commonly disposed on the first pin A1, the second pin A2 and the base island A5. A first MOS chip 3 is disposed on the fourth pin A4, and a second MOS chip 4 is disposed on the third pin A3. An LED chip 2 is disposed on the photosensitive control chip 1. The plastic casing encapsulates the packaging unit and each chip, and the bottom surface of each pin is exposed outside the plastic casing.

[0030] The packaging process can follow the standard DFN packaging procedure. After attaching DAF to the back of the photosensitive control chip 1, it is bonded to the base island A5, the first pin A1, and the second pin A2. Transparent adhesive is applied to the photosensitive area of ​​the photosensitive control chip 1 to bond the LED chip 2. Silver paste is applied to the fourth pin A4 and the third pin A3, and the first MOS chip 3 and the second MOS chip 4 are bonded thereafter, followed by baking and curing. After baking and curing, bonding is performed using relevant soldering techniques such as ultrasonic bonding, employing gold, copper, or alloy wires. The positive electrode of the LED chip 2 is bonded to the first pin A1, and the negative electrode is bonded to the second pin A2. The photosensitive control chip 1 is bonded to the gates of the first MOS chip 3 and the second MOS chip 4. The sources of the first MOS chip 3 and the second MOS chip 4 are bonded together. The drain of the first MOS chip 3 is connected to the fourth pin A4 via silver paste, and the drain of the second MOS chip 4 is connected to the third pin A3 via silver paste, completing the electrical connection between chips and between chips and their corresponding pins. Then, through injection molding and other related processes, a plastic shell is formed. After that, it can be baked to release stress, then electroplated with tin to prevent oxidation and enhance solderability, and finally cut into individual products.

[0031] The above description is only a preferred embodiment of this application and is not intended to limit this application. Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application.

Claims

1. A DFN lead frame, comprising packaging units formed in a rectangular array on the frame body, characterized in that, The package unit includes a base island (A5) arranged in the middle region along the width direction of the package unit, a first pin (A1) and a second pin (A2) spaced apart on one side of the base island (A5), and a third pin (A3) and a fourth pin (A4) spaced apart on the other side of the base island (A5). The first pin (A1) and the second pin (A2) are spaced apart, and the third pin (A3) and the fourth pin (A4) are spaced apart. The back of the base island (A5) and at least one of the first pin (A1), the second pin (A2), the third pin (A3) and the fourth pin (A4) has at least a partial area that is a semi-etched area. After packaging, the bottom surface of each pin is exposed.

2. The DFN lead frame according to claim 1, characterized in that, The first pin (A1), the second pin (A2), the third pin (A3), and the fourth pin (A4) are arranged along the length of the package unit.

3. The DFN lead frame according to claim 1, characterized in that, The first pin (A1) and the second pin (A2) extend from one end of the package unit along its length and are connected to the frame body via connecting ribs. The third pin (A3) and the fourth pin (A4) extend from the other end of the package unit along its length and are connected to the frame body via connecting ribs.

4. The DFN lead frame according to claim 3, characterized in that, The first pin (A1) and the fourth pin (A4) extend from one side of the package unit along its length and are connected to the frame body via connecting ribs. The second pin (A2) and the third pin (A3) extend from the other side of the package unit along its length and are connected to the frame body via connecting ribs.

5. The DFN lead frame according to claim 4, characterized in that, The base island (A5) extends to both sides of the packaging unit along its length and is connected to the main frame body by connecting ribs.

6. The DFN lead frame according to claim 1, characterized in that, The back of the base island (A5), first pin (A1), second pin (A2), third pin (A3) and fourth pin (A4) all have at least a partial area that is half-etched.

7. The DFN lead frame according to claim 6, characterized in that, The entire back of the base island (A5) is a semi-etched area, or the middle area of ​​the back of the base island (A5) is a heat sink (A6), and the area outside the heat sink (A6) is a semi-etched area. After packaging, the bottom surface of the heat sink (A6) is exposed.

8. The DFN lead frame according to claim 6, characterized in that, The back side of the first pin (A1) and the second pin (A2) adjacent to each other, the back side of the third pin (A3) and the fourth pin (A4) adjacent to each other, and the back side of each pin extending outward from the package unit have a half-etched area.

9. An integrated packaging module, characterized in that, The package includes a plastic encapsulation shell and a DFN lead frame as described in any one of claims 1-8. A photosensitive control chip (1) is provided on the first pin (A1), the second pin (A2), and the base island (A5). A first MOS chip (3) is provided on the fourth pin (A4), and a second MOS chip (4) is provided on the third pin (A3). An LED chip (2) is provided on the photosensitive control chip (1). The plastic encapsulation shell encapsulates the packaging unit and each chip, and the bottom surface of each pin is exposed outside the plastic encapsulation shell.

10. The integrated packaging module according to claim 9, characterized in that, The positive electrode of the LED chip (2) is bonded to the first pin (A1), and the negative electrode is bonded to the second pin (A2). The photosensitive control chip (1) is bonded to the gate of the first MOS chip (3) and the second MOS chip (4). The source of the first MOS chip (3) and the source of the second MOS chip (4) are bonded together. The drain of the first MOS chip (3) is connected to the fourth pin (A4) through conductive adhesive. The drain of the second MOS chip (4) is connected to the third pin (A3) through conductive adhesive.