Driver circuit, driver chip and display device

Abstract

This disclosure relates to a driving circuit, a driving chip, and a display device. The driving circuit includes a clock module and M channel modules. The clock module generates N first clock signals with a phase difference between each pair of signals. Each channel module includes a phase adjustment module, a PWM generation module, and a selection module. The phase adjustment module is connected to the clock module and is used to phase-shift the N first clock signals to obtain N second clock signals. The PWM generation module is connected to the clock module and the phase adjustment module and is used to generate a first PWM signal based on a reference clock signal and a PWM fundamental frequency, and to generate a second PWM signal based on the reference clock signal, a target clock signal, and the PWM fundamental frequency. The selection module is connected to the PWM generation module and is used to select either the first PWM signal or the second PWM signal for output based on a first selection signal, as the target PWM signal. This disclosure simplifies the circuit structure and reduces the circuit footprint.

Description

Technical Field

[0001] This disclosure relates to the field of display driver technology, and in particular to a driver circuit, driver chip and display device. Background Technology

[0002] PWM (Pulse-width modulation) is a technique that adjusts display brightness by controlling the ratio of the time a display unit is on to the time it is off. Taking LED (Light Emitting Diode) chips as an example, after the display data is input to the driver chip, the driver chip generates a PWM signal based on the display data and outputs a constant current (provided by a constant current source) to the LED chips during the pulse time of the PWM signal to drive the LED chips to emit light. Therefore, the duty cycle of the PWM signal affects the display brightness of the LED chips, and the accuracy of the PWM signal determines the accuracy of the display brightness adjustment.

[0003] In related technologies, to achieve higher display accuracy at a fixed display frame rate, the bit width of the PWM signal can usually be increased. However, this method requires increasing the frequency of the clock signal, which can easily increase system power consumption and necessitates a smaller manufacturing process, significantly increasing the production cost of the driver chip.

[0004] Furthermore, the current method of increasing the integer bit width of the PWM signal leads to an increase in clock frequency, and this method has reached its limit. If we consider increasing the fractional bit width, the existing method of using a phase-locked loop (PLL) to output multi-phase clocks requires more clock signal lines to display the same number of fractional bits. For example, to display 2-bit fractional data, four clock signal lines are needed for the PLL to output different clock signals to the constant current output channel. However, the more constant current output channels there are, the more complex the driver circuit design becomes, and the larger the trace area of ​​the driver circuit, resulting in a complex circuit structure and a large footprint. Utility Model Content

[0005] Based on this, the present disclosure provides a driving circuit, a driving chip, and a display device, which can effectively reduce the number of clock signal lines, thereby simplifying the circuit structure and reducing the circuit area occupied, while improving display accuracy.

[0006] To achieve the above objectives, in a first aspect, some embodiments of this disclosure provide a driving circuit, including: a clock module and M channel modules. The clock module is used to generate N first clock signals with a phase difference between each pair. Each channel module includes a phase adjustment module, a PWM generation module, and a selection module. The phase adjustment module is connected to the clock module and is used to phase-shift the N first clock signals to obtain N second clock signals. The PWM generation module is connected to the clock module and the phase adjustment module and is used to generate a first PWM signal based on a reference clock signal and a PWM fundamental frequency, and to generate a second PWM signal based on a reference clock signal, a target clock signal, and a PWM fundamental frequency. The selection module is connected to the PWM generation module and is used to select either the first PWM signal or the second PWM signal for output based on a first selection signal as the target PWM signal. Wherein, any two clock signals among the N first clock signals and the N second clock signals have different phases; the reference clock signal is any one of the N first clock signals, and the target clock signal is selected from the first clock signal and the second clock signal other than the reference clock signal based on the second selection signal; N is an integer ≥ 2, and M is an integer ≥ 1.

[0007] According to some embodiments of this disclosure, the driving circuit further includes N first signal lines for transmitting a first clock signal. Each phase adjustment module includes N inverting units. The N inverting units are connected one-to-one with the N first signal lines, and are used to invert the first clock signal transmitted by each first signal line to generate a corresponding second clock signal.

[0008] According to some embodiments of this disclosure, the PWM generation module includes a first generation submodule and a second generation submodule. The first generation submodule is connected to the clock module and configured to generate a first PWM signal by sampling the PWM fundamental wave based on a reference clock signal. The second generation submodule is connected to the clock module, the phase adjustment module, and the first generation submodule and configured to generate an intermediate signal by sampling the PWM fundamental wave based on a target clock signal or by sampling the first PWM signal, and to generate a second PWM signal based on the intermediate signal and the first PWM signal.

[0009] According to some embodiments of this disclosure, the selection module is configured to: select to output a first PWM signal when the displayed data is an integer, and select to output a second PWM signal when the displayed data is not an integer.

[0010] According to some embodiments of this disclosure, the second generation submodule includes a selection unit, a sampling unit, and a logic unit. The selection unit is connected to the clock module and the phase adjustment module, and is configured to select one of a first clock signal (excluding the reference clock signal) and a second clock signal as the target clock signal based on a second selection signal. The sampling unit is connected to the selection unit and is configured to sample the PWM fundamental wave or sample the first PWM signal based on the target clock signal to generate an intermediate signal. The logic unit is connected to the first generation submodule and the sampling unit, and is configured to perform logical operations on the intermediate signal and the first PWM signal to generate a second PWM signal.

[0011] According to some embodiments of this disclosure, the logic unit includes: an OR circuit, an OR circuit, and an AND circuit.

[0012] According to some embodiments of this disclosure, any two adjacent first clock signals among the N first clock signals have the same phase difference.

[0013] According to some embodiments of this disclosure, N equals 2, and the phase difference between the two first clock signals generated by the clock module is 90°.

[0014] Secondly, this disclosure also provides a driver chip according to some embodiments, including: the driver circuit as described in any of the above embodiments.

[0015] Thirdly, this disclosure also provides a display device according to some embodiments. The display device includes: a display panel, and a plurality of cascaded driver chips as described in the above embodiments. Each driver chip's channel module is connected to the display panel to output a display drive signal to the display panel based on a target PWM signal.

[0016] In summary, the unexpected effects that the driving circuit, driving chip, and display device provided in this disclosure embodiment can achieve are:

[0017] In this embodiment, a clock module generates N first clock signals with phase differences between each other, and M channel modules connected to the clock module are set up. Not only can the phase adjustment module in the channel module shift the N first clock signals to obtain N second clock signals to double the clock signal, but the PWM generation module can also generate a first PWM signal based on the reference clock signal and the PWM fundamental wave, and generate a second PWM signal based on the reference clock signal, the target clock signal and the PWM fundamental wave. This allows the selection module to select the first PWM signal or the second PWM signal as the target PWM signal output based on the first selection signal, thereby achieving selective output of the target PWM signal. Since any two of the N first clock signals and N second clock signals have different phases, and the reference clock signal is any one of the N first clock signals, while the target clock signal is selected from the first and second clock signals other than the reference clock signal based on the second selection signal, the target clock signal in this embodiment can have more choices. For example, it can be obtained by selecting one from (N-1) first clock signals and N second clock signals based on the second selection signal, thereby ensuring that the second PWM signal in this embodiment can match a larger number (2N-1) different decimal data, improving display accuracy. Simultaneously, this application configures a phase adjustment module for each channel module to perform phase shifting processing on the received first clock signal to obtain the second clock signal, thereby reducing the number of clock signal transmission lines between the clock module and the channel module by half. Therefore, compared to the prior art, this application can effectively reduce the number of signal lines for transmitting clock signals while achieving the same bit decimal, simplifying the circuit structure and reducing the circuit area occupied.

[0018] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features, objects, and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a structural block diagram of a driving circuit provided in some embodiments;

[0021] Figure 2 This is a block diagram of another driving circuit provided in some embodiments;

[0022] Figure 3 This is a block diagram of yet another driving circuit provided in some embodiments;

[0023] Figure 4 This is a schematic diagram of the structure of a first generation submodule provided in some embodiments;

[0024] Figure 5 This is a schematic diagram of the structure of a second generation submodule provided in some embodiments;

[0025] Figure 6 This is a schematic diagram of another second generation submodule provided in some embodiments;

[0026] Figure 7 This is a schematic diagram of the structure of yet another second generation submodule provided in some embodiments;

[0027] Figure 8 This is a schematic diagram of the structure of yet another second generation submodule provided in some embodiments;

[0028] Figure 9 This is a schematic diagram illustrating the working principle of a driving circuit provided in some embodiments;

[0029] Figure 10 for Figure 9 A waveform diagram of the driving circuit shown;

[0030] Figure 11 for Figure 9 Another waveform diagram of the driving circuit shown.

[0031] Explanation of reference numerals in the attached figures:

[0032] 1-Clock module, 2-Channel module, 21-Phase adjustment module, 211-Inverting unit, 22-PWM generation module, 221-First generation sub-module, 222-Second generation sub-module, 23-Selection module, 3-First signal line, 41-Selection unit, 42-Sampling unit, 43-Logic unit. Detailed Implementation

[0033] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0035] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0036] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0037] Please see Figure 1 This disclosure provides a driving circuit in some embodiments, including: a clock module 1 and M channel modules 2, where M is an integer ≥ 1. The clock module 1 generates N first clock signals with a phase difference between each pair, where N is an integer ≥ 2. Each channel module 2 includes a phase adjustment module 21, a PWM generation module 22, and a selection module 23. The phase adjustment module 21 is connected to the clock module 1 and is used to phase-shift the N first clock signals to obtain N second clock signals. The PWM generation module 22 is connected to the clock module 1 and the phase adjustment module 21, and is used to generate a first PWM signal based on a reference clock signal and a PWM fundamental frequency, and to generate a second PWM signal based on the reference clock signal, a target clock signal, and the PWM fundamental frequency. The selection module 23 is connected to the PWM generation module 22 and is used to select either the first PWM signal or the second PWM signal for output based on a first selection signal, as the target PWM signal.

[0038] It should be noted here that the first selection signal can be generated to match the data type of the displayed data. For example, when the displayed data is an integer, the first selection signal is used to select the first PWM signal as the target PWM signal for output; for example, when the displayed data is not an integer, that is, when the displayed data contains a decimal part, the first selection signal is used to select the second PWM signal as the target PWM signal for output.

[0039] Optionally, the selection module 23 is configured to: select to output a first PWM signal when the displayed data is an integer, and select to output a second PWM signal when the displayed data is not an integer.

[0040] Optionally, any two of the N first clock signals and N second clock signals may have different phases. The reference clock signal is any one of the N first clock signals. The target clock signal is selected from the first and second clock signals other than the reference clock signal based on a second selection signal.

[0041] It should be noted here that the second selection signal can be generated based on the decimal value in the displayed data when the displayed data is not an integer, so as to select different target clock signals for different decimal data.

[0042] In some examples, the phase difference between any two adjacent first clock signals among the N first clock signals is the same, for example, 90°.

[0043] In some examples, the N second clock signals are obtained by performing the same phase shift operation on the N first clock signals. For example, the N second clock signals are obtained by shifting the phase of each of the N first clock signals by 180 degrees.

[0044] In some examples, the second clock signal is a clock signal with the first clock signal phase-shifted by 180°.

[0045] In this embodiment, a clock module 1 generates N first clock signals with phase differences between each pair, and M channel modules 2 connected to the clock module 1 are configured. Not only can the phase adjustment module 21 in the channel modules 2 shift the N first clock signals to obtain N second clock signals, thus doubling the clock signal, but the PWM generation module 22 can also generate a first PWM signal based on a reference clock signal and a PWM fundamental frequency, and generate a second PWM signal based on the reference clock signal, a target clock signal, and the PWM fundamental frequency. This allows the selection module 23 to select either the first PWM signal or the second PWM signal as the target PWM signal output based on a first selection signal, thereby achieving selective output of the target PWM signal. In this embodiment, a phase adjustment module 21 is configured for each channel module 2 to shift the phase of the N first clock signals with different phases generated by the clock module 1, thereby obtaining another N second clock signals with different phases. Compared to the prior art, achieving the same bit fraction can save half the wiring between the clock module 1 and the channel modules 2.

[0046] In other words, since any two of the N first clock signals and N second clock signals have different phases, and the reference clock signal is any one of the N first clock signals, while the target clock signal is selected from the first and second clock signals other than the reference clock signal based on the second selection signal, the target clock signal in this embodiment can have more choices. For example, it can be obtained by selecting one from (N-1) first clock signals and N second clock signals based on the second selection signal, thereby ensuring that the second PWM signal in this embodiment can match a larger number (2N-1) different decimal data, improving display accuracy. Simultaneously, this application configures a phase adjustment module for each channel module to perform phase shifting processing on the received first clock signal to obtain the second clock signal, thereby reducing the number of clock signal transmission lines between the clock module and the channel module by half. Therefore, compared to the prior art, this application can effectively reduce the number of signal lines for transmitting clock signals while achieving the same bit decimal, simplifying the circuit structure and reducing the circuit area occupied.

[0047] Please see Figure 2 In some embodiments of this disclosure, the driving circuit further includes N first signal lines 3 for transmitting a first clock signal. Each phase adjustment module 21 includes N inverting units 211. The N inverting units 211 are connected one-to-one with the N first signal lines 3, and are used to invert the first clock signal transmitted by each first signal line 3 to generate a corresponding second clock signal.

[0048] For example, clock module 1 includes, but is not limited to, a phase-locked loop (PLL) clock generator.

[0049] For example, the inverting unit 211 includes, but is not limited to, an inverter.

[0050] In this embodiment, the phase adjustment module 21 is constructed using inverting units 211 directly connected to each of the first signal lines 3. This simplifies the structure and wiring of the phase adjustment module 21, further reducing the design difficulty of the drive circuit and making it easier to implement. Furthermore, with the number of constant current output channels (i.e., channel modules 2) remaining unchanged, the total number of first signal lines 3 in the drive circuit can be reduced by half compared to the prior art. Since each first signal line 3 needs to be connected to a channel module, and constant current drive chips generally include multiple channels, saving half of the first signal lines 3 can greatly simplify chip routing.

[0051] Please continue reading. Figure 2 In some embodiments of this disclosure, the PWM generation module 22 includes a first generation submodule 221 and a second generation submodule 222. The first generation submodule 221 is connected to the clock module 1 and configured to generate a first PWM signal by sampling the PWM fundamental wave based on a reference clock signal. The second generation submodule 222 is connected to the clock module 1, the phase adjustment module 21, and the first generation submodule 221, and configured to generate an intermediate signal by sampling the PWM fundamental wave based on a target clock signal or by sampling the first PWM signal, and to generate a second PWM signal based on the intermediate signal and the first PWM signal.

[0052] It can be understood that when the displayed data is an integer, the first PWM signal is generated by sampling the PWM fundamental wave based on the reference clock signal. When the displayed data is not an integer, depending on the different values ​​of the fractional part of the displayed data, a target clock signal of different phases can be selected to generate the second PWM signal corresponding to the displayed data by sampling the PWM fundamental wave or the first PWM signal based on the selected target clock signal.

[0053] It is understood that in the PWM generation module 22 provided in the embodiments of this disclosure, the circuit structures of the first generation submodule 221 and the second generation submodule 222 are different, and they can be formed by using a variety of circuit components to match their functions.

[0054] In some embodiments, please refer to Figure 4 The first generation submodule 221 includes, but is not limited to, a pulse generator; for example, it can be selected as a trigger, including but not limited to: D trigger, T trigger or other triggers. Figure 4 The first generation submodule 221 is used as an example to illustrate the D flip-flop. The D flip-flop can be based on a reference clock signal. CLKSample PWM fundamental wave PWM Generate the first PWM signal PWM1 .

[0055] In some embodiments, please refer to Figure 3 and Figures 5-8 The second generation submodule 222 includes a selection unit 41, a sampling unit 42, and a logic unit 43. The selection unit 41 is connected to the clock module 1 and the phase adjustment module 21, and is configured to select one of a first clock signal (excluding the reference clock signal) and a second clock signal as the target clock signal based on a second selection signal. The sampling unit 42 is connected to the selection unit 41 and is configured to sample the PWM fundamental wave or the first PWM signal based on the target clock signal to generate an intermediate signal. The logic unit 43 is connected to the first generation submodule 221 and the sampling unit 42, and is configured to perform logical operations on the intermediate signal and the first PWM signal to generate a second PWM signal.

[0056] For example, please refer to Figures 5-8 The selection unit 41 includes, but is not limited to, a multiplexer, such as a data selector that can select 1 from 2N-1 signals; that is, the (N-1) first clock signals and N second clock signals other than the reference clock signal can be sequentially arranged as CLK1, CLK2, CLK3...CLK(2N-1) and input as (2N-1) input signals to the data selector, so that the data selector selects the corresponding input signal as the target clock signal according to the value of the decimal part of the displayed data. CLKm .

[0057] For example, please continue reading Figures 5-8 The sampling unit 42 includes, but is not limited to, a pulse sampling circuit; for example, it can be selected as a flip-flop, including but not limited to: D flip-flop, T flip-flop or other flip-flops. Figures 5-8 The example shown is a D flip-flop with sampling unit 42. Figure 5 and Figure 7 In this context, the D flip-flop can be based on the target clock signal. CLKm Sample PWM fundamental wave PWM Generate intermediate signals PWMm . Figure 6 and Figure 8 In this context, the D flip-flop can be based on the target clock signal. CLKm Sample the first PWM signal PWM1 Generate intermediate signals PWMm .

[0058] For example, please continue reading Figures 5-8 Logic unit 43 includes: an OR circuit, an OR gate, and an AND circuit. The OR circuit includes, but is not limited to, an OR gate, and the AND circuit includes, but is not limited to, an AND gate. Figure 5 and Figure 6 In the middle, logic unit 43 uses an OR gate, which can process intermediate signals. PWMm and the first PWM signal PWM1 Perform an OR operation to generate a second PWM signal. PWM2 . Figure 7 and Figure 8 In the middle, logic unit 43 uses an AND gate, which can process intermediate signals. PWMm and the first PWM signal PWM1 Perform an AND operation to generate a second PWM signal. PWM2 .

[0059] To more clearly illustrate the driving circuit provided in the embodiments of this disclosure, please refer to... Figures 9-11 Taking N equal to 2 and the phase difference between the two first clock signals generated by clock module 1 as an example, the working principle and timing of the driving circuit are described in detail in the following embodiments.

[0060] Please see Figure 9 Clock module 1 is a PLL clock generator. The two first clock signals generated by clock module 1 are GCLK and GCLK90, where GCLK can be used as a reference clock signal. CLK GCLK90 represents a clock signal that is 90 degrees out of phase with GCLK, such as a signal that is 90 degrees lagging behind GCLK. The phase adjustment module 21 (e.g., inverting unit 211) inverts each of the first clock signals to obtain two second clock signals, GCLK180 and GCLK270. GCLK180 represents a clock signal that is 180 degrees out of phase with GCLK, such as a signal that is 180 degrees lagging behind GCLK. GCLK270 represents a clock signal that is 180 degrees out of phase with GCLK90, such as a signal that is 180 degrees lagging behind GCLK90. The target clock signal can be obtained by selecting one of GCLK90, GCLK180, or GCLK270.

[0061] Optionally, when the displayed data is an integer, the first PWM signal is selected to be output. PWM1 For the target PWM signal PWMS That is, based on the reference clock signal CLK (e.g., GCLK) Samples the PWM fundamental frequency PWM Generate the first PWM signal PWM1 and in response to the first selection signal SEL Select the first PWM signal PWM1 The output is the target PWM signal. PWMS .

[0062] Optionally, when the displayed data is not an integer (i.e. contains a decimal part), a second PWM signal is output. PWM2For the target PWM signal PWMS That is: based on the target clock signal CLKm (e.g., GCLK90, GCLK180, or GCLK270) Samples the PWM fundamental frequency. PWM Or the first PWM signal PWM1 Generate intermediate signals PWMm Then through the intermediate signal PWMm and the first PWM signal PWM1 Perform logical operations to generate a second PWM signal PWM2 and in response to the first selection signal SEL Select the second PWM signal PWM2 The output is the target PWM signal. PWMS For example, if the decimal parts of the displayed data are 0.25, 0.5, and 0.75, then GCLK90 can be selected as the target clock signal corresponding to decimal 0.25, GCLK180 as the target clock signal corresponding to decimal 0.5, and GCLK270 as the target clock signal corresponding to decimal 0.75.

[0063] Based on the above embodiments, Figure 10 and Figure 11 Two different waveform diagrams of the drive circuit are illustrated. GCLK has the same clock frequency as GCK90, GCLK180, and GCLK270, but a different clock phase. Taking grayscale values ​​of displayed data as 1, 1.25, 1.5, or 1.75 as examples: when the grayscale value of the displayed data is 1, PWM_PRA_DATA_0 is the output waveform of its target PWM signal (PWMS); when the grayscale value of the displayed data is 1.25, PWM_PRA_DATA_1 is the output waveform of its target PWM signal (PWMS); when the grayscale value of the displayed data is 1.5, PWM_PRA_DATA_2 is the output waveform of its target PWM signal (PWMS); and when the grayscale value of the displayed data is 1.75, PWM_PRA_DATA_3 is the output waveform of its target PWM signal (PWMS).

[0064] and, Figure 10 China and Israel based on target clock signal CLKm (e.g., GCLK90, GCLK180, or GCLK270) Sample the first PWM signal PWM1 Forming intermediate signals PWMm and through intermediate signals PWMm and the first PWM signal PWM1 Perform an OR operation to generate a second PWM signal PWM2 An example is provided. Figure 10In the above, the output waveforms of PWM_PRA_DATA_0, PWM_PRA_DATA_1, PWM_PRA_DATA_2 and PWM_PRA_DATA_3 are positively broadened with PWM_PRA_DATA_0 as the reference.

[0065] For example, such as Figure 10 As shown, PWM_PRA_DATA_0 is the PWM fundamental frequency. PWM The first PWM signal obtained after GCLK sampling PWM1 Its pulse width is equal to the fundamental frequency of the PWM. PWM The pulse width. PWM_PRA_DATA_1 is the first PWM signal. PWM1 The intermediate signal obtained after sampling by GCLK90 PWMm In relation to the first PWM signal PWM1 The second PWM signal generated after OR operation PWM2 Its pulse width is equal to 1.25 PWM fundamental waves. PWM The pulse width. PWM_PRA_DATA_2 is the first PWM signal. PWM1 The intermediate signal obtained after sampling by GCLK180 PWMm In relation to the first PWM signal PWM1 The second PWM signal generated after OR operation PWM2 Its pulse width is equal to 1.5 PWM fundamental waves. PWM The pulse width. PWM_PRA_DATA_3 is the first PWM signal. PWM1 The intermediate signal obtained after sampling by GCLK270 PWMm In relation to the first PWM signal PWM1 The second PWM signal generated after OR operation PWM2 Its pulse width is equal to 1.75 PWM fundamental waves. PWM The pulse width.

[0066] in addition, Figure 11 China and Israel based on target clock signal CLKm (e.g., GCLK90, GCLK180, or GCLK270) Samples the PWM fundamental frequency. PWM Forming intermediate signals PWMm and through intermediate signals PWMm and the first PWM signal PWM1 Perform an OR operation to generate a second PWM signal PWM2 An example is provided. Figure 11In this model, the output waveforms of PWM_PRA_DATA_0, PWM_PRA_DATA_1, PWM_PRA_DATA_2, and PWM_PRA_DATA_3 are widened in reverse relative to PWM_PRA_DATA_0.

[0067] For example, such as Figure 11 As shown, PWM_PRA_DATA_0 is the PWM fundamental frequency. PWM The first PWM signal obtained after GCLK sampling PWM1 Its pulse width is equal to the fundamental frequency of the PWM. PWM The pulse width. PWM_PRA_DATA_1 is the fundamental frequency of the PWM. PWM The intermediate signal obtained after sampling by GCLK270 PWMm In relation to the first PWM signal PWM1 The second PWM signal generated after OR operation PWM2 Its pulse width is equal to 1.25 PWM fundamental waves. PWM The pulse width. PWM_PRA_DATA_2 is the fundamental frequency of the PWM. PWM The intermediate signal obtained after sampling by GCLK180 PWMm In relation to the first PWM signal PWM1 The second PWM signal generated after OR operation PWM2 Its pulse width is equal to 1.5 PWM fundamental waves. PWM The pulse width. PWM_PRA_DATA_3 is the fundamental frequency of the PWM. PWM The intermediate signal obtained after sampling by GCLK90 PWMm In relation to the first PWM signal PWM1 The second PWM signal generated after OR operation PWM2 Its pulse width is equal to 1.75 PWM fundamental waves. PWM The pulse width.

[0068] As can be seen, in the embodiment where N equals 2, the bit width of the target PWM signal (PWMS) can be effectively extended by two bits without increasing the clock frequency. That is, two gray levels can be added to the fractional part of the displayed data, thereby improving the display accuracy.

[0069] This disclosure also provides a driver chip in some embodiments, including the driver circuit described in any of the preceding embodiments. The driver chip also possesses all the technical advantages of the aforementioned driver circuits, and will not be repeated here.

[0070] This disclosure also provides a display device in some embodiments. The display device includes a display panel and a plurality of cascaded driver chips as described in the above embodiments. Each driver chip's channel module is connected to the display panel to output a display drive signal (such as a constant current) to the display panel based on a target PWM signal. The display device also possesses the technical advantages of the aforementioned driver circuit, and will not be elaborated upon here.

[0071] For example, display devices include, but are not limited to, advertising screens with display functions, televisions, instruments, mobile phones or computers, etc.

[0072] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0073] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] The embodiments described above are merely examples of several implementation methods of this disclosure, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure.

Claims

1. A driving circuit, characterized in that, include: Clock module and M channel modules; The clock module is used to generate N first clock signals that have a phase difference between each other; Each of the aforementioned channel modules includes a phase adjustment module, a PWM generation module, and a selection module; The phase adjustment module is connected to the clock module and is used to phase-shift N first clock signals to obtain N second clock signals; The PWM generation module is connected to the clock module and the phase adjustment module, and is used to generate a first PWM signal based on the reference clock signal and the PWM fundamental wave, and to generate a second PWM signal based on the reference clock signal, the target clock signal and the PWM fundamental wave. The selection module is connected to the PWM generation module and is used to select the first PWM signal or the second PWM signal to be output based on the first selection signal, so as to serve as the target PWM signal; Wherein, any two clock signals among the N first clock signals and the N second clock signals have different phases; the reference clock signal is any one of the N first clock signals, and the target clock signal is selected from the first clock signals and the second clock signals other than the reference clock signal based on the second selection signal; N is an integer ≥ 2, and M is an integer ≥ 1.

2. The driving circuit according to claim 1, characterized in that, Also includes: N first signal lines used to transmit the first clock signal; Each phase adjustment module includes N inverting units; The N inverting units are connected one-to-one with the N first signal lines to invert the first clock signal transmitted on each of the first signal lines in order to generate the corresponding second clock signal.

3. The driving circuit according to claim 1, characterized in that, The PWM generation module includes: a first generation submodule and a second generation submodule; wherein... The first generation submodule is connected to the clock module and is configured to: sample the PWM fundamental wave based on the reference clock signal to generate a first PWM signal; The second generation submodule is connected to the clock module, the phase adjustment module, and the first generation submodule, and is configured to: sample the PWM fundamental wave based on the target clock signal or sample the first PWM signal to generate an intermediate signal, and generate the second PWM signal based on the intermediate signal and the first PWM signal.

4. The driving circuit according to claim 3, characterized in that, The selection module is configured to output the first PWM signal when the displayed data is an integer, and to output the second PWM signal when the displayed data is not an integer.

5. The driving circuit according to claim 3, characterized in that, The second generation submodule includes: The selection unit, connected to the clock module and the phase adjustment module, is configured to select one of the first clock signal and the second clock signal (excluding the reference clock signal) as the target clock signal based on the second selection signal. A sampling unit, connected to the selection unit, is configured to: sample the PWM fundamental wave or sample the first PWM signal based on the target clock signal to generate the intermediate signal; The logic unit, connected to the first generation submodule and the sampling unit, is configured to perform logical operations on the intermediate signal and the first PWM signal to generate the second PWM signal.

6. The driving circuit according to claim 5, characterized in that, The logic unit includes: an OR circuit, an OR circuit, and an AND circuit.

7. The driving circuit according to any one of claims 1 to 6, characterized in that, The phase difference between any two adjacent first clock signals among the N first clock signals is the same.

8. The driving circuit according to any one of claims 1 to 6, characterized in that, N equals 2; the phase difference between the two first clock signals generated by the clock module is 90°.

9. A driver chip, characterized in that, include: The driving circuit as described in any one of claims 1 to 8.

10. A display device, characterized in that, include: Display panel; as well as, A cascaded plurality of driver chips as described in claim 9; The channel module of each driver chip is connected to the display panel to output a display drive signal to the display panel based on the target PWM signal.

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