A modular half duplex 2FSK low error rate communication circuit
By using a modularly designed half-duplex 2FSK low-error communication circuit, modulation and demodulation integration was achieved, solving the problems of high system integration complexity and transient interference during switching, reducing the bit error rate, and improving the system reliability and integration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- WU XI JING LI YUAN WEI DIAN ZI JI SHU YOU XIAN GONG SI
- Filing Date
- 2025-06-11
- Publication Date
- 2026-06-05
AI Technical Summary
The existing 2FSK communication system has a fragmented design of modulation and demodulation modules, which leads to high system integration complexity. It only supports unidirectional data transmission and cannot complete communication independently. Furthermore, the distortion and switching transient interference introduced by the isolator have not been effectively resolved.
A modular half-duplex 2FSK low-error communication circuit was designed, including a modulation module, a demodulation module, and a logic control module. The logic control module realizes half-duplex communication mode control and achieves electrical and physical isolation of the module at the moment of demodulation/modulation state switching, blocking the coupling noise path.
It achieves integrated half-duplex 2FSK modulation and demodulation, reduces the communication bit error rate, improves the system reliability and integration, and solves the problems of distortion and switching transient interference introduced by isolators.
Smart Images
Figure CN224329474U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of communication circuits, and in particular to a modular half-duplex 2FSK low error communication circuit. Background Technology
[0002] With the rapid development of wireless communication technology, signal modulation technology plays an increasingly important role in information transmission, becoming one of the core factors determining the quality of information transmission. In modern communication systems, digital modulation technology is particularly widely used; it can convert digital signals into analog waveforms suitable for transmission through communication channels, thus making information transmission more stable and reliable.
[0003] Common digital modulation methods include Amplitude Shift Keying (ASK), Phase Shift Keying (PSK), and Frequency Shift Keying (FSK). FSK transmits digital signals by changing the carrier frequency. Its core advantages are simple hardware cost, strong noise immunity, and high compatibility. Compared to ASK, it is less sensitive to amplitude interference, and compared to PSK, it does not require complex phase synchronization. This makes it widely used in medium- and low-speed data transmission, such as Bluetooth communication systems, medical implantable microelectronic devices, and portable communication devices.
[0004] Among them, binary frequency shift keying (2FSK) is the most basic modulation method in FSK. It is a modulation method that uses baseband signals to select two carriers of different frequencies. The demodulation methods are mainly divided into incoherent detection method and coherent detection method.
[0005] In existing technologies, 2FSK communication typically employs separate modulation and demodulation modules. These modules are responsible for converting digital signals into frequency signals for transmission (modulation), and the receiving end demodulates the received frequency signals to recover the original digital information. In this way, 2FSK communication systems can achieve reliable data transmission, making them particularly suitable for applications with strict frequency requirements.
[0006] However, due to the separate design of the modulation and demodulation modules, the modulation and demodulation circuits are separate and cannot complete communication independently. They require external complementary modules and separate debugging of the modulation and demodulation circuits, resulting in high system integration complexity. They only support unidirectional data transmission, which limits their practical application scenarios.
[0007] Meanwhile, modems / demodulators typically need to be used in conjunction with digital isolators. Currently, isolation effectiveness is mainly achieved by improving the isolator's own performance parameters, such as bandwidth and CMTI level. However, this approach is not only costly but also limited by physical constraints. Furthermore, these solutions lack effective means at the communication protocol and modulation / demodulation levels to address the distortion introduced by the isolator, especially for the transient interference during handover in half-duplex communication. Utility Model Content
[0008] In response to the aforementioned problems and technical requirements, the applicant has proposed a modular half-duplex 2FSK low-error communication circuit.
[0009] The technical solution of this utility model is as follows:
[0010] A modular half-duplex 2FSK low-error communication circuit includes a modulation module, a demodulation module, and a logic control module, wherein...
[0011] The logic control module is connected to the modulation module and the demodulation module, and is used to control the modulation module or the demodulation module to be in working state.
[0012] The demodulation module includes a waveform conversion circuit, a time-to-voltage conversion circuit, a sample-and-hold circuit, a low-pass filter, and a comparator, all of which are connected in an adaptive manner.
[0013] The waveform conversion circuit is used to convert the 2FSK signal into a detection signal. The time-voltage conversion circuit generates a voltage signal based on the detection signal. The sample-and-hold circuit is used to sample the voltage signal under the control of the detection signal. The voltage signal sampled by the sample-and-hold circuit is output to a comparator and a low-pass filter. The low-pass filter is used to filter the voltage signal to generate a reference voltage signal. The comparator is used to compare the voltage signal and the reference voltage signal to generate a demodulated signal.
[0014] A further technical solution is that the modulation module includes a bandgap reference voltage circuit for providing reference voltages Vref1 and Vref2, and a voltage-frequency conversion circuit, wherein,
[0015] The voltage-to-frequency conversion circuit includes a PMOS transistor M1, an NMOS transistor M2, buffers B1 and B2, resistors R1, R2, R3, R4, R5, R6, and R7, operational amplifiers U1 and U2, capacitor C1, and transistor Q1.
[0016] The gates of PMOS transistor M1 and NMOS transistor M2 are connected to form a modulation input terminal. The source of PMOS transistor M1 is connected to a reference voltage Vref1, and the source of NMOS transistor M2 is connected to a reference voltage Vref2. The drains of PMOS transistor M1 and NMOS transistor M2 are both connected to the input terminal of buffer B1. The output terminal of buffer B1 is connected to one end of resistor R1 and one end of resistor R2.
[0017] The other end of resistor R1 is grounded through resistor R4, and the other end of resistor R1 is connected to the non-inverting input terminal of operational amplifier U1. The other end of resistor R2 is connected to the collector of transistor Q1 through resistor R3. The other end of resistor R2 is also connected to one end of capacitor C1 and the inverting input terminal of operational amplifier U1.
[0018] The emitter of transistor Q1 is grounded, and the base of transistor Q1 is connected to the output of operational amplifier U2 through resistor R7. The other end of capacitor C1 is connected to the output of operational amplifier U1 and the input of buffer B2. The output of operational amplifier U1 is connected to the inverting input of operational amplifier U2. The non-inverting input of operational amplifier U2 is connected to one end of resistor R5 and one end of resistor R6. The other end of resistor R5 is connected to the positive terminal of voltage source U2'. The negative terminal of voltage source U2' is grounded, and the other end of resistor R6 is connected to the output of operational amplifier U2.
[0019] A further technical solution is that the voltage-frequency conversion circuit also includes capacitor C2, resistors R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, transistors Q3, Q4, Q5, and Q6.
[0020] The output terminal of the buffer B2 is connected to one end of the resistor R8 through the capacitor C2. The other end of the resistor R8 is connected to one end of the resistor R11, one end of the resistor R12, and the base of the transistor Q5. The other end of the resistor R11 is connected to one end of the resistors R9 and R10. The other end of the resistor R9 is connected to the power supply voltage VDD. The other end of the resistor R10 is connected to the power supply voltage VEE. The other end of the resistor R12 is grounded.
[0021] A further technical solution is that the emitter of the transistor Q5 is connected to one end of resistor R17 and one end of resistor R16 through resistor R15, the other end of resistor R17 is connected to the power supply voltage VEE, and the other end of resistor R16 is connected to the emitter of transistor Q6.
[0022] The collector of transistor Q5 is connected to the collector and base of transistor Q3. The emitter of transistor Q3 is connected to the power supply voltage VDD through resistor R13. The base of transistor Q6 is grounded and connected to one end of resistor R18. The collector of transistor Q6 is connected to the collector of transistor Q4 and the other end of resistor R18, forming the output terminal of the voltage-frequency conversion circuit. The emitter of transistor Q4 is connected to the power supply voltage VDD through resistor R14.
[0023] A further technical solution is that the time-voltage conversion circuit includes an inverter I1, an inverter I2, a PMOS transistor M3, a PMOS transistor M4, a PMOS transistor M5, an NMOS transistor M6, and a capacitor C3.
[0024] The input terminals of inverters I1 and I2 are connected to the output terminal of the waveform conversion circuit. The output terminal of inverter I1 is connected to the gate of PMOS transistor M5. The drain of PMOS transistor M5 is connected to one end of capacitor C3 and the drain of NMOS transistor M6, forming the output terminal of the time-voltage conversion circuit. The other end of capacitor C3 is grounded. The output terminal of inverter I2 is connected to the gate of NMOS transistor M6, and the source of NMOS transistor M6 is grounded.
[0025] A further technical solution is that the source of the PMOS transistor M5 is connected to the drain of the PMOS transistor M4, the gate of the PMOS transistor M4 is connected to the gate and drain of the PMOS transistor M3, and is connected to the positive terminal of the current source, the negative terminal of the current source is grounded, and the sources of the PMOS transistors M3 and M4 are both connected to the power supply voltage VDD.
[0026] A further technical solution is that the sample-and-hold circuit includes a buffer B3, inverter I3, inverter I4, inverter I5, capacitor C4, capacitor C5, PMOS transistor M7, NMOS transistor M8, PMOS transistor M9, and NMOS transistor M10, wherein...
[0027] The output of the time-voltage conversion circuit is connected to the drain of PMOS transistor M7 and the drain of NMOS transistor M8 through buffer B3. The output of the waveform conversion circuit is connected to the input of inverter I3, the input of inverter I4 and the gate of NMOS transistor M8. The output of inverter I3 is connected to the gate of PMOS transistor M7. The output of inverter I4 is connected to the input of inverter I5 and the gate of NMOS transistor M10.
[0028] The sources of PMOS transistor M7 and NMOS transistor M8 are grounded through capacitor C4 and connected to the drains of PMOS transistor M9 and NMOS transistor M10. The output of inverter I5 is connected to the gate of PMOS transistor M9. The sources of PMOS transistor M9 and NMOS transistor M10 are grounded through capacitor C5 and form the output of the sample-and-hold circuit.
[0029] The output of the sample-and-hold circuit is connected to the input of the low-pass filter and the non-inverting input of the comparator, and the output of the low-pass filter is connected to the inverting input of the comparator.
[0030] A further technical solution is that the logic control module includes a modulation control module and a demodulation control module, wherein,
[0031] The modulation control module includes an inverter I6, a PMOS transistor M11, an NMOS transistor M12, and an NMOS transistor M13;
[0032] The output terminal of the voltage-frequency conversion circuit is connected to the drain of PMOS transistor M11 and NMOS transistor M12. The gate of NMOS transistor M12 is connected to the output terminal of inverter I6. The gate of PMOS transistor M11 is connected to the input terminal of inverter I6. The input terminal of inverter I6 forms the control terminal of the modulation control module.
[0033] The gate of the PMOS transistor M11 is connected to the gate of the NMOS transistor M13. The source of the NMOS transistor M13 is connected to the source of the PMOS transistor M11 and the source of the NMOS transistor M12, forming a modulation output terminal. The source of the NMOS transistor M13 is grounded.
[0034] A further technical solution is that the demodulation control module includes an inverter I7, a PMOS transistor M14, an NMOS transistor M15, and an NMOS transistor M16, wherein...
[0035] The input terminal of the inverter I7 forms the control terminal of the demodulation control module. The input terminal of the inverter I7 is connected to the gate of the NMOS transistor M15. The output terminal of the comparator is connected to the drain of the PMOS transistor M14 and the NMOS transistor M15. The gate of the PMOS transistor M14 is connected to the output terminal of the inverter I7 and the gate of the NMOS transistor M16. The source of the PMOS transistor M14 is connected to the source of the NMOS transistor M15 and the drain of the NMOS transistor M16 to form the demodulation output terminal. The source of the NMOS transistor M16 is grounded.
[0036] A further technical solution includes a carrier detection module, which is connected to the input of the demodulation module and is used to detect the input status of the demodulation module's input.
[0037] The beneficial technical effects of this utility model are:
[0038] This invention designs a half-duplex 2FSK modulation and demodulation integrated circuit for electrical isolation communication systems, breaking through the limitations of traditional discrete module architecture. The logic control module can realize the control of half-duplex communication mode, and can realize electrical and physical isolation between the module's transmitting end and subsequent circuits at the moment of demodulation / modulation state switching, effectively blocking the coupling noise path caused by state switching. This makes it an ideal core technology module for solving the inherent reliability problem in digital isolated communication systems, while significantly reducing the communication bit error rate in such systems. Attached Figure Description
[0039] Figure 1 This is a modular schematic diagram of one embodiment of the half-duplex 2FSK low error communication circuit provided by this utility model.
[0040] Figure 2 This is a functional link diagram of one embodiment of the half-duplex 2FSK low error communication circuit provided by this utility model.
[0041] Figure 3 This is a structural block diagram of one embodiment of the half-duplex 2FSK low error communication circuit provided by this utility model.
[0042] Figure 4 This is a circuit diagram of one embodiment of the voltage-frequency conversion circuit provided by this utility model.
[0043] Figure 5 This is a circuit diagram of one embodiment of the time-voltage conversion circuit provided by this utility model.
[0044] Figure 6 This is a circuit schematic diagram of one embodiment of the sample-and-hold circuit provided by this utility model.
[0045] Figure 7 This is a circuit schematic diagram of one embodiment of the modulation control module provided by this utility model.
[0046] Figure 8 This is a circuit diagram of one embodiment of the demodulation control module provided by this utility model.
[0047] Figure 9 This is a schematic diagram showing the connection between the logic control module and the digital isolator in one embodiment of the present invention.
[0048] Figure 10 This is a simulation result diagram of the half-duplex 2FSK low-error communication circuit provided by this utility model when the input signal is a periodic code digital code.
[0049] Figure 11 This is a simulation result diagram of the half-duplex 2FSK low-error communication circuit provided by this utility model when the input signal is a pseudo-random binary sequence. Detailed Implementation
[0050] The specific embodiments of this utility model will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.
[0051] This invention provides a modular half-duplex 2FSK low-error communication circuit, such as... Figure 1 and Figure 2 As shown, it includes a modulation module, a demodulation module, and a logic control module, wherein,
[0052] The logic control module is connected to the modulation module and the demodulation module, and is used to control the modulation module or the demodulation module to be in working state.
[0053] The demodulation module includes a waveform conversion circuit, a time-to-voltage conversion circuit, a sample-and-hold circuit, a low-pass filter, and a comparator, all of which are connected in an adaptive manner.
[0054] The waveform conversion circuit is used to convert the 2FSK signal into a detection signal. The time-voltage conversion circuit generates a voltage signal based on the detection signal. The sample-and-hold circuit is used to sample the voltage signal under the control of the detection signal. The voltage signal sampled by the sample-and-hold circuit is output to a comparator and a low-pass filter. The low-pass filter is used to filter the voltage signal to generate a reference voltage signal. The comparator is used to compare the voltage signal and the reference voltage signal to generate a demodulated signal.
[0055] Specifically, the logic control module can switch between the modulation and demodulation states of the half-duplex 2FSK low-error communication circuit. When the half-duplex 2FSK low-error communication circuit is in the modulation state, the modulation module is in operation and is used to modulate the input baseband signal into a 2FSK signal. When the half-duplex 2FSK low-error communication circuit is in the demodulation state, the demodulation module is in operation and is used to demodulate the 2FSK signal into the original digital signal, i.e., the demodulated signal.
[0056] Figure 2 The combined diagram shows the functional links between the modulation module and the demodulation module. Figure 3 A block diagram of a half-duplex 2FSK low-error communication circuit is shown, such as... Figure 2-3As shown, the modulation module includes a bandgap reference voltage circuit and a voltage-frequency conversion circuit connected together; in the demodulation module, the waveform conversion circuit is connected to the time-voltage conversion circuit and the sample-and-hold circuit, the time-voltage conversion circuit is connected to the sample-and-hold circuit, the sample-and-hold circuit is connected to the comparator and the low-pass filter, and the low-pass filter is connected to the comparator.
[0057] Specifically, the bandgap reference voltage circuit provides reference voltages Vref1 and Vref2. The specific form of the bandgap reference voltage circuit can be consistent with existing technology. The voltage-frequency conversion circuit (VFC circuit) modulates the baseband signal into a 2FSK signal. Please refer to [reference needed]. Figure 4 The voltage-to-frequency conversion circuit includes a PMOS transistor M1, an NMOS transistor M2, buffers B1 and B2, resistors R1, R2, R3, R4, R5, R6, and R7, operational amplifiers U1 and U2, capacitor C1, and transistor Q1.
[0058] The gates of PMOS transistor M1 and NMOS transistor M2 are connected to form a modulation input terminal (D_IN). The source of PMOS transistor M1 is connected to a reference voltage Vref1, and the source of NMOS transistor M2 is connected to a reference voltage Vref2. The drains of both PMOS transistor M1 and NMOS transistor M2 are connected to the input terminal of buffer B1. The output terminal of buffer B1 is connected to one end of resistor R1 and one end of resistor R2. The other end of resistor R1 is grounded through resistor R4 and connected to the non-inverting input terminal of operational amplifier U1. The other end of resistor R2 is connected to the collector of transistor Q1 through resistor R3. One end is also connected to one end of capacitor C1 and the inverting input terminal of operational amplifier U1; the emitter of transistor Q1 is grounded, the base of transistor Q1 is connected to the output terminal of operational amplifier U2 through resistor R7, the other end of capacitor C1 is connected to the output terminal of operational amplifier U1 and the input terminal of buffer B2, the output terminal of operational amplifier U1 is connected to the inverting input terminal of operational amplifier U2, the non-inverting input terminal of operational amplifier U2 is connected to one end of resistor R5 and one end of resistor R6, the other end of resistor R5 is connected to the positive terminal of voltage source U2', the negative terminal of voltage source U2' is grounded, and the other end of resistor R6 is connected to the output terminal of operational amplifier U2.
[0059] The voltage-frequency conversion circuit also includes capacitor C2, resistors R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, transistors Q3, Q4, Q5, and Q6. Transistors Q3 and Q4 are PNP transistors, while transistors Q1, Q5, and Q6 are NPN transistors.
[0060] The output terminal of the buffer B2 is connected to one end of the resistor R8 through the capacitor C2. The other end of the resistor R8 is connected to one end of the resistor R11, one end of the resistor R12, and the base of the transistor Q5. The other end of the resistor R11 is connected to one end of the resistors R9 and R10. The other end of the resistor R9 is connected to the power supply voltage VDD. The other end of the resistor R10 is connected to the power supply voltage VEE. The other end of the resistor R12 is grounded. The emitter of transistor Q5 is connected to one end of resistor R17 and one end of resistor R16 via resistor R15. The other end of resistor R17 is connected to the power supply voltage VEE, and the other end of resistor R16 is connected to the emitter of transistor Q6. The collector of transistor Q5 is connected to the collector and base of transistor Q3. The emitter of transistor Q3 is connected to the power supply voltage VDD via resistor R13. The base of transistor Q6 is grounded and connected to one end of resistor R18. The collector of transistor Q6 is connected to the collector of transistor Q4 and the other end of resistor R18, forming the output terminal of the voltage-frequency conversion circuit. The emitter of transistor Q4 is connected to the power supply voltage VDD via resistor R14.
[0061] A voltage-to-frequency conversion circuit makes the oscillation frequency of the output waveform proportional to the voltage of the input signal, such as... Figure 4 As shown, the voltage of the input signal (baseband signal) controls the magnitudes of the voltages at the non-inverting and inverting input terminals of operational amplifier U1, thereby controlling the output waveform of the voltage-frequency conversion circuit to switch between two different frequencies, thus achieving phase-continuous 2FSK modulation without an external frequency source. In this embodiment, the output waveform of the voltage-frequency conversion circuit is a sine wave.
[0062] During demodulation, the waveform conversion circuit (Waveform_switch circuit) first converts the 2FSK signal into a detector signal that varies between two different frequencies. The waveform conversion circuit can employ a form commonly used by those skilled in the art. The input terminal of the waveform conversion circuit is the demodulation input terminal (FSK_IN). In this embodiment, the detector signal is a square wave signal. Then, the time-to-voltage conversion circuit (TVC circuit) generates a voltage signal based on the detector signal. Please refer to [reference needed]. Figure 5The time-voltage conversion circuit includes inverter I1, inverter I2, PMOS transistors M3, M4, M5, and M6, and capacitor C3. The input terminals of inverters I1 and I2 are connected to the output terminal of the waveform conversion circuit. The output terminal of inverter I1 is connected to the gate of PMOS transistor M5. The drain of PMOS transistor M5 is connected to one end of capacitor C3 and the drain of NMOS transistor M6, forming the output terminal of the time-voltage conversion circuit. The other end of capacitor C3 is grounded. The output terminal of inverter I2 is connected to the gate of NMOS transistor M6, and the source of NMOS transistor M6 is grounded. The source of PMOS transistor M5 is connected to the drain of PMOS transistor M4. The gate of PMOS transistor M4 is connected to the gate and drain of PMOS transistor M3, and is connected to the positive terminal of a current source. The negative terminal of the current source is grounded. The sources of both PMOS transistors M3 and M4 are connected to the power supply voltage VDD. The current source is mirrored from PMOS transistor M4 to the source of PMOS transistor M5. During each positive half-cycle of the square wave signal output by the waveform conversion circuit, the mirrored current source charges capacitor C3. The output of the time-voltage conversion circuit outputs the voltage on capacitor C3. The voltage of capacitor C3 corresponds to the frequency of the square wave signal, i.e., the frequency of the 2FSK signal.
[0063] Due to the nature of capacitor charging in the time-to-voltage conversion circuit, the output voltage corresponding to the 2FSK signal frequency does not remain constant throughout the entire cycle, but only appears at the end of each positive half-cycle of the square wave signal. To obtain more accurate demodulation results, this technical solution introduces a sample-and-hold circuit (S / H circuit), such as... Figure 6 As shown, the sample-and-hold circuit includes buffer B3, inverter I3, inverter I4, inverter I5, capacitor C4, capacitor C5, PMOS transistor M7, NMOS transistor M8, PMOS transistor M9, and NMOS transistor M10, wherein...
[0064] The output of the time-to-voltage conversion circuit is connected to the drain of PMOS transistor M7 and the drain of NMOS transistor M8 through buffer B3. The output of the waveform conversion circuit is connected to the input of inverter I3, the input of inverter I4, and the gate of NMOS transistor M8. The output of inverter I3 is connected to the gate of PMOS transistor M7. The output of inverter I4 is connected to the input of inverter I5 and the gate of NMOS transistor M10. The input of inverter I4 serves as the control terminal (SAMPLE) of the sample-and-hold circuit, and receives the square wave signal output by the waveform conversion circuit.
[0065] The sources of PMOS transistors M7 and M8 are grounded through capacitor C4 and connected to the drains of PMOS transistors M9 and M10. The output of inverter I5 is connected to the gate of PMOS transistor M9. The sources of PMOS transistors M9 and M10 are grounded through capacitor C5, forming the output of a sample-and-hold circuit. The output of the sample-and-hold circuit is connected to the input of a low-pass filter and the non-inverting input of a comparator. The output of the low-pass filter is connected to the inverting input of the comparator.
[0066] The sample-and-hold circuit samples the peak value of the output waveform of the TVC circuit and holds the corresponding voltage value at the end of each positive half-cycle of the square wave signal. The voltage signal sampled by the sample-and-hold circuit is output to a comparator and a low-pass filter. The low-pass filter filters the voltage signal, removes high-frequency noise and interference, extracts the DC component of the voltage signal, and forms a reference voltage signal. The comparator compares the relative magnitudes of the voltage signal and the reference voltage signal to generate a demodulated signal, thereby restoring the 2FSK signal to the original digital signal. Since the reference voltage signal is not a fixed value, but changes slightly with the output waveform of the time-voltage conversion circuit and the sample-and-hold circuit, the two input signals of the comparator have synchronous small-amplitude fluctuation characteristics when the comparator performs voltage comparison, which greatly reduces the probability of misjudgment by the comparator in the critical state, and ultimately reduces the bit error rate. The low-pass filter (LPF) can adopt a form commonly used by those skilled in the art.
[0067] Furthermore, the logic control module includes a modulation control module (Logic1) and a demodulation control module (Logic2); please refer to... Figure 7-8 The modulation control module includes an inverter I6, a PMOS transistor M11, an NMOS transistor M12, and an NMOS transistor M13; the output terminal of the voltage-frequency conversion circuit is connected to the drains of the PMOS transistor M11 and the NMOS transistor M12, the gate of the NMOS transistor M12 is connected to the output terminal of the inverter I6, the gate of the PMOS transistor M11 is connected to the input terminal of the inverter I6, and the input terminal of the inverter I6 forms the control terminal of the modulation control module;
[0068] The gate of the PMOS transistor M11 is connected to the gate of the NMOS transistor M13. The source of the NMOS transistor M13 is connected to the source of the PMOS transistor M11 and the source of the NMOS transistor M12, forming a modulation output terminal (FSK_OUT). The source of the NMOS transistor M13 is grounded.
[0069] The demodulation control module includes an inverter I7, a PMOS transistor M14, an NMOS transistor M15, and an NMOS transistor M16. The input terminal of the inverter I7 forms the control terminal of the demodulation control module. The input terminal of the inverter I7 is connected to the gate of the NMOS transistor M15. The output terminal of the comparator is connected to the drains of the PMOS transistor M14 and the NMOS transistor M15. The gate of the PMOS transistor M14 is connected to the output terminal of the inverter I7 and the gate of the NMOS transistor M16. The source of the PMOS transistor M14 is connected to the source of the NMOS transistor M15 and the drain of the NMOS transistor M16 to form a demodulation output terminal (D_OUT). The source of the NMOS transistor M16 is grounded.
[0070] Specifically, the control terminals of both the modulation control module and the demodulation control module are connected to the main control terminal (RTS'). The modulation control module and the demodulation control module operate on the same principle. Taking the modulation control module as an example, PMOS transistor M11 and NMOS transistor M12 form a transmission gate, which functions as a switch to control whether a signal can pass through. To ensure that the voltage at the output terminal of the transmission gate can be correctly pulled low to logic 0 when the signal cannot pass through, an NMOS transistor M13 is connected to the output terminal of the transmission gate as a pull-down element. The RTS' signal is input to the main control terminal. In this embodiment, when the RTS' signal is high, the demodulation module is in operation, while the modulation module is disabled; when the RTS' signal is low, the modulation module is started, and the demodulation module is disabled.
[0071] In specific implementation, such as Figure 9 As shown, the modulation output can be connected to the demodulation input via a digital isolator. The modulation control module can be connected in series between the modulation module output and the digital isolator input. When the transmission gate in the modulation control module is closed, it physically cuts off the path for any possible residual output of the modulation module (such as shutting down transient oscillations or parasitic coupling noise) to enter the digital isolator.
[0072] Meanwhile, the output of the digital isolator is connected to the demodulation module, and the demodulation output is connected to the subsequent circuit through the demodulation control module. When the transmission gate in the demodulation control module is closed, any digital noise (jitter, ground bounce) that may be generated in the output stage of the demodulation module can be completely isolated, preventing it from contaminating the sensitive transmitting analog circuit (modulation module) or digital isolator interface through power supply, ground or spatial coupling, thus significantly improving signal purity.
[0073] Furthermore, the modular half-duplex 2FSK low error communication circuit also includes a carrier detection module (Carrier_detection), which is connected to the input terminal (FSK_IN) of the demodulation module and is used to detect the input status of the demodulation module input terminal.
[0074] Specifically, the carrier detection module can take the same form as existing technologies. Generally, the carrier detection module extracts and processes the signal from the input of the demodulation module, compares the processed signal with a reference voltage, and determines whether there is a signal input to the input of the demodulation module based on the comparison result. The reference voltage can be provided by the aforementioned bandgap reference voltage circuit. In this embodiment, when there is an input signal at the input of the demodulation module, the carrier detection module outputs a high-level CD signal; if there is no input signal at the input of the demodulation module, the CD signal remains low.
[0075] To verify the operational performance of the modular half-duplex 2FSK low-error communication circuit, this application conducted simulation experiments on the circuit. Figure 10 and Figure 11 The simulation results of the circuit are shown for inputs of periodic digital codes and pseudo-random binary sequences, respectively. Figure 10 and Figure 11 In the diagram, the waveforms from top to bottom represent the RTS' signal waveform, the input waveform of the modulation module, the output waveform of the modulation module, the input waveform of the demodulation module, the output waveform of the demodulation module, and the CD signal waveform, respectively.
[0076] Simulation results show that the circuit can adapt well to different types of data formats and can successfully modulate and demodulate the input signal with a low bit error rate. On this basis, the RTS' signal can effectively control the switching between the modulation module and the demodulation module, thereby realizing data transmission in half-duplex communication scenarios. The CD signal can accurately detect the signal status at the input of the demodulation module, making it easy to monitor whether the signal input is normal.
[0077] The above descriptions are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that can be directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.
Claims
1. A modular half-duplex 2FSK low-error communication circuit, characterized in that, It includes a modulation module, a demodulation module, and a logic control module, among which, The logic control module is connected to the modulation module and the demodulation module, and is used to control the modulation module or the demodulation module to be in working state. The demodulation module includes a waveform conversion circuit, a time-to-voltage conversion circuit, a sample-and-hold circuit, a low-pass filter, and a comparator, all of which are connected in an adaptive manner. The waveform conversion circuit is used to convert the 2FSK signal into a detection signal. The time-voltage conversion circuit generates a voltage signal based on the detection signal. The sample-and-hold circuit is used to sample the voltage signal under the control of the detection signal. The voltage signal sampled by the sample-and-hold circuit is output to a comparator and a low-pass filter. The low-pass filter is used to filter the voltage signal to generate a reference voltage signal. The comparator is used to compare the voltage signal and the reference voltage signal to generate a demodulated signal.
2. The modular half-duplex 2FSK low-error communication circuit according to claim 1, characterized in that, The modulation module includes a bandgap reference voltage circuit for providing reference voltages Vref1 and Vref2, and a voltage-frequency conversion circuit, wherein... The voltage-to-frequency conversion circuit includes a PMOS transistor M1, an NMOS transistor M2, buffers B1 and B2, resistors R1, R2, R3, R4, R5, R6, and R7, operational amplifiers U1 and U2, capacitor C1, and transistor Q1. The gates of PMOS transistor M1 and NMOS transistor M2 are connected to form a modulation input terminal. The source of PMOS transistor M1 is connected to a reference voltage Vref1, and the source of NMOS transistor M2 is connected to a reference voltage Vref2. The drains of PMOS transistor M1 and NMOS transistor M2 are both connected to the input terminal of buffer B1. The output terminal of buffer B1 is connected to one end of resistor R1 and one end of resistor R2. The other end of resistor R1 is grounded through resistor R4, and the other end of resistor R1 is connected to the non-inverting input terminal of operational amplifier U1. The other end of resistor R2 is connected to the collector of transistor Q1 through resistor R3. The other end of resistor R2 is also connected to one end of capacitor C1 and the inverting input terminal of operational amplifier U1. The emitter of transistor Q1 is grounded, and the base of transistor Q1 is connected to the output of operational amplifier U2 through resistor R7. The other end of capacitor C1 is connected to the output of operational amplifier U1 and the input of buffer B2. The output of operational amplifier U1 is connected to the inverting input of operational amplifier U2. The non-inverting input of operational amplifier U2 is connected to one end of resistor R5 and one end of resistor R6. The other end of resistor R5 is connected to the positive terminal of voltage source U2'. The negative terminal of voltage source U2' is grounded, and the other end of resistor R6 is connected to the output of operational amplifier U2.
3. The modular half-duplex 2FSK low-error communication circuit according to claim 2, characterized in that, The voltage-frequency conversion circuit also includes capacitor C2, resistors R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, transistors Q3, Q4, Q5, and Q6. The output terminal of the buffer B2 is connected to one end of the resistor R8 through the capacitor C2. The other end of the resistor R8 is connected to one end of the resistor R11, one end of the resistor R12, and the base of the transistor Q5. The other end of the resistor R11 is connected to one end of the resistors R9 and R10. The other end of the resistor R9 is connected to the power supply voltage VDD. The other end of the resistor R10 is connected to the power supply voltage VEE. The other end of the resistor R12 is grounded.
4. The modular half-duplex 2FSK low-error communication circuit according to claim 3, characterized in that, The emitter of transistor Q5 is connected to one end of resistor R17 and one end of resistor R16 through resistor R15. The other end of resistor R17 is connected to the power supply voltage VEE, and the other end of resistor R16 is connected to the emitter of transistor Q6. The collector of transistor Q5 is connected to the collector and base of transistor Q3. The emitter of transistor Q3 is connected to the power supply voltage VDD through resistor R13. The base of transistor Q6 is grounded and connected to one end of resistor R18. The collector of transistor Q6 is connected to the collector of transistor Q4 and the other end of resistor R18, forming the output terminal of the voltage-frequency conversion circuit. The emitter of transistor Q4 is connected to the power supply voltage VDD through resistor R14.
5. The modular half-duplex 2FSK low-error communication circuit according to claim 4, characterized in that, The time-voltage conversion circuit includes inverter I1, inverter I2, PMOS transistor M3, PMOS transistor M4, PMOS transistor M5, NMOS transistor M6, and capacitor C3. The input terminals of inverters I1 and I2 are connected to the output terminal of the waveform conversion circuit. The output terminal of inverter I1 is connected to the gate of PMOS transistor M5. The drain of PMOS transistor M5 is connected to one end of capacitor C3 and the drain of NMOS transistor M6, forming the output terminal of the time-voltage conversion circuit. The other end of capacitor C3 is grounded. The output terminal of inverter I2 is connected to the gate of NMOS transistor M6, and the source of NMOS transistor M6 is grounded.
6. The modular half-duplex 2FSK low-error communication circuit according to claim 5, characterized in that, The source of PMOS transistor M5 is connected to the drain of PMOS transistor M4. The gate of PMOS transistor M4 is connected to the gate and drain of PMOS transistor M3 and is connected to the positive terminal of the current source. The negative terminal of the current source is grounded. The sources of PMOS transistors M3 and M4 are both connected to the power supply voltage VDD.
7. The modular half-duplex 2FSK low-error communication circuit according to claim 5, characterized in that, The sample-and-hold circuit includes buffer B3, inverter I3, inverter I4, inverter I5, capacitor C4, capacitor C5, PMOS transistor M7, NMOS transistor M8, PMOS transistor M9, and NMOS transistor M10, wherein... The output of the time-voltage conversion circuit is connected to the drain of PMOS transistor M7 and the drain of NMOS transistor M8 through buffer B3. The output of the waveform conversion circuit is connected to the input of inverter I3, the input of inverter I4 and the gate of NMOS transistor M8. The output of inverter I3 is connected to the gate of PMOS transistor M7. The output of inverter I4 is connected to the input of inverter I5 and the gate of NMOS transistor M10. The sources of PMOS transistor M7 and NMOS transistor M8 are grounded through capacitor C4 and connected to the drains of PMOS transistor M9 and NMOS transistor M10. The output of inverter I5 is connected to the gate of PMOS transistor M9. The sources of PMOS transistor M9 and NMOS transistor M10 are grounded through capacitor C5 and form the output of the sample-and-hold circuit. The output of the sample-and-hold circuit is connected to the input of the low-pass filter and the non-inverting input of the comparator, and the output of the low-pass filter is connected to the inverting input of the comparator.
8. The modular half-duplex 2FSK low-error communication circuit according to claim 7, characterized in that, The logic control module includes a modulation control module and a demodulation control module, wherein... The modulation control module includes an inverter I6, a PMOS transistor M11, an NMOS transistor M12, and an NMOS transistor M13; The output terminal of the voltage-frequency conversion circuit is connected to the drain of PMOS transistor M11 and NMOS transistor M12. The gate of NMOS transistor M12 is connected to the output terminal of inverter I6. The gate of PMOS transistor M11 is connected to the input terminal of inverter I6. The input terminal of inverter I6 forms the control terminal of the modulation control module. The gate of the PMOS transistor M11 is connected to the gate of the NMOS transistor M13. The source of the NMOS transistor M13 is connected to the source of the PMOS transistor M11 and the source of the NMOS transistor M12, forming a modulation output terminal. The source of the NMOS transistor M13 is grounded.
9. The modular half-duplex 2FSK low-error communication circuit according to claim 8, characterized in that, The demodulation control module includes an inverter I7, a PMOS transistor M14, an NMOS transistor M15, and an NMOS transistor M16, wherein... The input terminal of the inverter I7 forms the control terminal of the demodulation control module. The input terminal of the inverter I7 is connected to the gate of the NMOS transistor M15. The output terminal of the comparator is connected to the drain of the PMOS transistor M14 and the NMOS transistor M15. The gate of the PMOS transistor M14 is connected to the output terminal of the inverter I7 and the gate of the NMOS transistor M16. The source of the PMOS transistor M14 is connected to the source of the NMOS transistor M15 and the drain of the NMOS transistor M16 to form the demodulation output terminal. The source of the NMOS transistor M16 is grounded.
10. The modular half-duplex 2FSK low-error communication circuit according to claim 8, characterized in that, It also includes a carrier detection module, which is connected to the input terminal of the demodulation module and is used to detect the input status of the demodulation module's input terminal.