Packaging structure

Abstract

The application provides a packaging structure, which comprises a substrate, an electronic element arranged above the substrate, and a plurality of first bumps electrically connected between the electronic element and the substrate and located at an edge region of the electronic element, wherein the longitudinal section of the first bump is in the shape of being narrow at the top and wide at the bottom. By improving the shape of the bump to be narrow at the top and wide at the bottom, the maximum current density in the bump can be significantly reduced, the maximum current that the bump can withstand is improved, and the electrical performance is improved. The application can also achieve the effects of reducing the process temperature and reducing the structural stress, and finally achieve the purposes of improving the reliability and service life of the bump. In addition, the application can also improve the warping problem of the packaging structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, specifically to a packaging structure. Background Technology

[0002] With the rapid development of automotive electronics, power management integrated circuits (PMICs) are constantly evolving towards miniaturization, leading to a sharp increase in current density within their packages, posing significant challenges to related design and manufacturing. Quad Flat No-lead (QFN) packages, with their low cost, high reliability, and excellent heat dissipation capabilities, have become the preferred packaging solution for PMICs. However, with the increasing complexity of circuit designs, traditional wire bonding technology can no longer meet the demands in terms of electrical performance and connection density. Therefore, the industry has introduced flip-chip technology to address this issue. Flip-chip technology involves flipping the chip and electrically connecting it using bumps. Flip-chip technology not only provides better electrical performance but also effectively addresses the challenges of future miniaturization.

[0003] Currently, the key to improving the electrical performance of QFN packages lies in the maximum current density within the bumps. If the maximum current density is too high, atomic electromigration will occur within the bumps, causing cracks and reducing the bump cross-sectional area. This reduction in bump cross-sectional area will then lead to a further increase in current density, further exacerbating atomic electromigration, creating a vicious cycle.

[0004] Currently, PMICs require increasingly larger maximum currents. However, to fully meet product design requirements, simply increasing the size of conductive components, such as increasing the size of the under bump metallization (UBM), cannot increase the maximum current that the bumps can withstand. Therefore, there is an urgent need for an innovative solution to increase the maximum current that the bumps can withstand and improve the electrical performance of the package. Utility Model Content

[0005] The purpose of this application is to propose a packaging structure for improving electrical performance.

[0006] This application proposes a packaging structure comprising: a substrate; an electronic component disposed above the substrate; and a plurality of first bumps electrically connected between the electronic component and the substrate and located at the edge region of the electronic component, wherein the longitudinal cross-section of the first bumps is narrow at the top and wide at the bottom.

[0007] In some alternative implementations, the longitudinal section of the first protrusion is trapezoidal.

[0008] In some alternative implementations, the first bump is a tin-silver alloy.

[0009] In some alternative embodiments, the edge region of the lower surface of the electronic component has a first bump base metal, the first bump being connected to the first bump base metal, the width of the first bump base metal being smaller than the bottom width of the first bump.

[0010] In some alternative embodiments, the packaging structure further includes a plurality of second bumps electrically connected between the electronic component and the substrate and located in the central region of the electronic component, wherein the top width and bottom width of the second bumps are substantially equal.

[0011] In some alternative embodiments, the lower surface of the electronic component has a central region with a second bump base metal, the second bump being connected to the second bump base metal, the width of the second bump base metal being substantially equal to the bottom width of the second bump.

[0012] In some alternative implementations, the width of the first bump base metal and the width of the second bump base metal are substantially equal.

[0013] In some alternative implementations, the width of the first bump base metal is smaller than the width of the second bump base metal.

[0014] In some alternative embodiments, the first bump base metal includes a copper pillar connected to the electronic component and a nickel layer disposed on the lower surface of the copper pillar.

[0015] In some alternative implementations, the ratio of the top width to the bottom width of the first bump is between 0.6 and 0.9.

[0016] In some alternative implementations, the ratio of the top width to the bottom width of the first bump is 0.8.

[0017] In some alternative embodiments, the packaging structure further includes a molding layer that encapsulates the electronic component.

[0018] In some alternative implementations, the substrate is a lead frame.

[0019] In some alternative implementations, the package structure is a square flat leadless package structure.

[0020] To improve the electrical performance of the package structure by increasing the maximum current that the bumps can withstand, this application proposes a package structure where the first bump is modified to be narrower at the top and wider at the bottom. This significantly reduces the maximum current density within the first bump, thereby increasing the maximum current that the first bump can withstand and improving electrical performance. Furthermore, the narrow-at-the-top, wide-at-the-bottom shape of the first bump in this application also reduces the optimal process temperature and the maximum structural stress, ultimately improving the reliability and lifespan of the bump. In addition, considering the greater warpage at the edges during packaging, the application of the narrow-at-the-top, wide-at-the-bottom shape of the first bump at the edges of electronic components in this application also serves as reinforcement, thus mitigating the warpage problem of the package structure. Attached Figure Description

[0021] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0022] Figure 1 This is a schematic diagram of the longitudinal cross-section of an existing QFN package structure;

[0023] Figure 2 yes Figure 1 A schematic diagram of the bump formation process in the image;

[0024] Figure 3 yes Figure 1 A schematic diagram of the actual appearance of the bumps in the diagram;

[0025] Figure 4 yes Figure 1 The diagram shows a simulated warpage of the QFN package structure.

[0026] Figure 5 This is a longitudinal cross-sectional structural diagram of a packaging structure according to an embodiment of this application;

[0027] Figure 6 yes Figure 5 A schematic diagram of the formation process of the first bump in the image;

[0028] Figure 7 yes Figure 5 A schematic diagram of the actual appearance of the first bump in the diagram;

[0029] Figure 8 yes Figure 5 A schematic diagram showing the various possible forms of the first bump in the diagram;

[0030] Figure 9 yes Figure 5 A schematic diagram of the electromigration of the first bump in different electron flow directions;

[0031] Figure 10 This is a longitudinal cross-sectional view of the packaging structure according to another embodiment of this application;

[0032] Figure 11 This is a schematic diagram comparing the overall effect of the first bump in the packaging structure of this application with the bump in the existing packaging structure;

[0033] Figure 12 This is a schematic diagram comparing the electromigration effect of the first bump in the packaging structure of this application with that of the bump in an existing packaging structure;

[0034] Figure 13 This is a reliability diagram of the first bump in the packaging structure of this application and the bump in the existing packaging structure.

[0035] Explanation of reference numerals / symbols in the attached diagram:

[0036] 10: Substrate; 11: Electronic component; 12: First bump; 13: First bump base metal; 131: Copper pillar; 132: Nickel layer; 14: Second bump; 15: Second bump base metal; 16: Mold sealing layer; 17: Tin-silver solder; 18: Silver-plated solder pad;

[0037] 90: Lead frame; 91: Electronic component; 92: Bump base metal; 93: Bump; 94: Molding material; 931: Tin-silver solder; 932: Silver-plated solder pad. Detailed Implementation

[0038] The specific embodiments of this application will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this application and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely for explaining the relevant invention and are not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0039] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this application should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0040] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0041] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0042] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

[0043] As used herein, the terms “substantially,” “materially,” “approximately,” and “about” are used to indicate and explain minor variations. For example, when used in conjunction with numerical values, the above terms may refer to a range of variation less than or equal to ±10% of the corresponding numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another embodiment, the thickness of a film or layer being “substantially uniform” may refer to the average thickness of the film or layer being less than or equal to ±10% of the standard deviation, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" can refer to two surfaces that lie within 50 μm along the same plane (such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm along the same plane). If, for example, two components overlap or overlap within 200 μm, 150 μm, 100 μm, 50 μm, 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm, then the two components can be considered "substantially aligned." If the angle between two surfaces or components is, for example, 90° ± 10° (such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°), then the two surfaces or components can be considered "substantially perpendicular." When used in conjunction with an event or situation, the terms "substantially," "substantially," "approximately," and "about" can refer to the exact occurrence of the event or situation as well as the very close approximation of its occurrence.

[0044] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the contents described in the specification. They are not intended to limit the scope of this application and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives of this application, should still fall within the scope of the technical content disclosed in this application. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0045] It should also be noted that the longitudinal section corresponding to the embodiment of this application can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0046] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0047] refer to Figure 1 , Figure 1 This is a schematic diagram of the longitudinal cross-sectional structure of an existing QFN package structure 1a. (See diagram below.) Figure 1 As shown, the QFN package structure 1a includes a lead frame 90, an electronic component 91, and a molding compound 94. The electronic component 91 has a bottom bump metal (UBM) 92 on its lower surface, and a bump 93 is located below the UBM 92. The electronic component 91 is electrically connected to the lead frame 90 via the UBM 92 and the bump 93. The molding compound 94 covers the electronic component 91, the UBM 92, and the bump 93. Here, the bump 93 is an electrical connector, serving both electrical connection and mechanical support functions, and is typically made of tin-silver alloy, tin-lead alloy, or lead-free alloy.

[0048] refer to Figure 2 , Figure 2 yes Figure 1 A schematic diagram illustrating the formation process of bump 93. (See diagram below.) Figure 2 As shown, before component bonding, a barrier material (not shown) is typically placed on the leadframe 90, and silver-plated openings are formed in the barrier material. Silver is electroplated within these openings to form silver-plated pads 932. Tin-silver solder 931 is then placed before the bump base metal 92 and the silver-plated pads 932 on the electronic component 91. A high-temperature process, such as reflow soldering, melts the tin-silver solder 931 and the silver-plated pads 932 to form a tin-silver alloy, which solidifies to form bumps 93, thereby achieving electrical connection between the electronic component 91 and the leadframe 90. The width of the silver-plated openings on the leadframe 90, or the width of the silver-plated pads 932, is approximately equal to the width of the bump base metal 92.

[0049] refer to Figure 3 , Figure 3 yes Figure 1 A schematic diagram of the actual appearance of bump 93. Given that the width of the silver-plated solder pad 932 and the width of the bump base metal 92 are approximately equal, the final cross-sectional shape of bump 93 is as follows... Figure 3 As shown, its upper and lower ends are basically the same width, and its sides bulge slightly outward in an arc shape. The shape of its upper surface is conformal to the shape of the lower surface of the bump base metal 92 (it can be flat or curved). Generally, this type of bump 93 with bulging sides can be called an arc-shaped bump.

[0050] Currently, the electrical performance of the QFN package structure 1a is difficult to improve effectively due to the limitation of the maximum current density within the bump 93. If the maximum current density is too high, atomic electromigration will occur within the bump 93, causing cracks in the bump 93 and reducing its cross-sectional area. This reduction in the cross-sectional area of ​​the bump 93 will further increase the current density, exacerbating atomic electromigration and creating a vicious cycle. Moreover, to fully meet product design requirements, it is not possible to increase the current that the bump 93 can withstand simply by increasing the size of the conductive components, such as increasing the size of the bump base metal 92.

[0051] In addition, refer to Figure 4 , Figure 4 yes Figure 1 The diagram shows a simulated warpage of the QFN package structure. Figure 4 As shown, the warping of the edge region of the QFN package structure 1a is greater than that of the central region. Warping can cause problems such as deformation and cracking of the bumps 93 in the edge region, resulting in a decrease in package strength, a decrease in the maximum current density inside the bumps 93, and a decrease in the maximum current that the bumps 93 can withstand. This further limits the electrical performance of the QFN package structure 1a.

[0052] Therefore, there is an urgent need for an innovative solution to increase the maximum current that the bump 93 can withstand, thereby improving its electrical performance.

[0053] refer to Figure 5 , Figure 5 This is a longitudinal cross-sectional structural diagram of the packaging structure 5a according to an embodiment of this application. Figure 5 As shown, the packaging structure 5a of this application includes:

[0054] Substrate 10;

[0055] Electronic component 11 is disposed above substrate 10;

[0056] Multiple first bumps 12 are electrically connected between the electronic component 11 and the substrate 10 and are located in the edge region of the electronic component 11. The longitudinal cross-section of the first bump 12 is narrow at the top and wide at the bottom.

[0057] Here, substrate 10 can be a lead frame. A lead frame, also known as a pin frame, is one of the core components of semiconductor packaging. As a carrier for the integrated circuit chip, it mainly consists of die paddles and lead fingers. During the packaging process, the die paddles provide mechanical support for the chip, while the lead fingers serve as electrical pathways connecting the internal circuitry of the chip to external circuitry. The lead frame is typically made of copper (Cu).

[0058] Here, electronic component 11 can be various types of chips, specifically various types of bare dies. For example, it can include logic function chips, memory chips, communication chips, microprocessor chips, graphics chips, micro-electro-mechanical system (MEMS) chips, radio frequency chips, bare die or chip-scale packages, inserts, or combinations thereof. This application does not specifically limit it in this regard.

[0059] Here, the first bump 12 has a shape that is narrower at the top and wider at the bottom (i.e., the top width is smaller than the bottom width), unlike the arc-shaped bumps in the prior art. Typically, the current density inside a bump is greatly affected by its shape. Compared to an arc-shaped bump, the first bump 12 with its narrower top and wider bottom shape can significantly reduce its maximum internal current density, thereby increasing the maximum current it can withstand and improving its electrical performance. Furthermore, the narrower top and wider bottom shape of the first bump 12 can also reduce the optimal process temperature and the maximum structural stress, ultimately improving the reliability and lifespan of the first bump 12.

[0060] Furthermore, the first bump 12 is typically located in the edge region of the electronic component 11. The reason for this arrangement is that the edge region of the package structure 5a has a greater degree of warpage. By applying this first bump 12 to the edge region of the electronic component 11, it can serve as a reinforcement, which can not only improve electrical performance but also alleviate the warpage problem of the package structure 5a.

[0061] Here, the edge region of electronic component 11 refers to the region closer to the edge of electronic component 11 relative to its center point. For example, it can be defined as follows: in a top-view direction, if the distance L1 from a location to the edge of electronic component 11 is less than its distance L2 to the center point of electronic component 11, or the ratio L1 / L2 is less than a constant such as 1, 0.9, 0.8, 0.7, 0.6, or 0.5, then that location is defined as part of the edge region. The area surrounded by the edge region can be defined as the central region.

[0062] In some alternative embodiments, the longitudinal cross-section of the first protrusion 12 is trapezoidal. From a perspective view, the overall shape of the first protrusion 12 can resemble a frustum. Therefore, the first protrusion 12 can be referred to as a frustum protrusion to distinguish it from the arc-shaped protrusions of the prior art.

[0063] In some alternative embodiments, the first bump 12 is made of solder (i.e., a solder bump). Specifically, the first bump 12 can be a tin-silver alloy (Sn-Ag alloy).

[0064] In some alternative embodiments, the edge region of the lower surface of the electronic component 11 has a first bump bottom metal 13, a first bump 12 connected to the first bump bottom metal 13, and the width of the first bump bottom metal 13 is smaller than the bottom width of the first bump 12.

[0065] refer to Figure 6 , Figure 6 yes Figure 5 A schematic diagram illustrating the formation process of the first protrusion 12. (See diagram below.) Figure 6 As shown in (a), before the electronic component 11 and the substrate 10 are bonded, the lower surface of the electronic component 11 has a bump base metal 13. The bump base metal 13 typically includes a copper pillar 131 connected to the electronic component 11 and a nickel layer 132 disposed on the lower surface of the copper pillar 131. A silver-plated solder pad 18 is disposed on the substrate 10. A tin-silver solder 17 is disposed between the bump base metal 13 and the silver-plated solder pad 18. In terms of process, the silver-plated solder pad 18 can be formed by providing a barrier material (not shown) on the substrate 10 and forming silver-plated openings on the barrier material, and electroplating metallic silver in the silver-plated openings. For example, the tin-silver solder 17 can be Sn1.8Ag.

[0066] In some alternative embodiments, the width of the first bump base metal 13 can be adjusted so that the width of the first bump base metal 13 is smaller than the width of its silver-plated pad 18 (or, smaller than the width of the silver-plated opening). In this way, the tin-silver solder 17 and the silver-plated pad 18 located between them can naturally form the first bump 12, which is narrower at the top and wider at the bottom, after a high-temperature process.

[0067] In some alternative embodiments, the ratio of the width of the bump base metal 13 to the width of the silver-plated solder pad 18 (or silver-plated opening) is between 0.6 and 0.9, further between 0.7 and 0.9, even further between 0.75 and 0.85, and still further between 0.8. Alternatively, the ratio of the top width to the bottom width of the first bump 12 is between 0.6 and 0.9, further between 0.7 and 0.9, even further between 0.75 and 0.85, and still further between 0.8.

[0068] like Figure 6 As shown in (b), after a high-temperature process such as reflow soldering, the tin-silver solder 17 and the silver-plated pad 18 melt and mix together to form a tin-silver metal alloy, which solidifies to form the first bump 12. Because the width of the bump base metal 13 is smaller than the width of the silver-plated pad 18, the formed first bump 12 has a top width smaller than its bottom width. The top width of the first bump 12 is substantially equal to the width of the bump base metal 13, and the bottom width of the first bump 12 is substantially equal to the width of the silver-plated pad 18.

[0069] refer to Figure 7 , Figure 7 yes Figure 5 A schematic diagram of the actual appearance of the first protrusion 12 in the diagram. (See attached diagram.) Figure 7 As shown, the longitudinal cross-section of the first bump 12 is narrower at the top and wider at the bottom. The lower surface of the first bump 12 conforms to the upper surface of the substrate 10 and is usually flat; the upper surface of the first bump 12 conforms to the lower surface of the bump base metal 13 and can usually be flat, or it can be a shape that bulges upward in the middle as shown in Figure 7 (corresponding to the concave lower surface of the bump base metal 13). The side surface of the first bump 12 can be as shown in Figure 7. Figure 7 The inclined plane shown.

[0070] refer to Figure 8 , Figure 8 yes Figure 5 A schematic diagram of various possible configurations of the first bump 12. This is based on whether the positions of the bump base metal 13 and the silver-plated solder pad 18 are center-aligned (see...). Figure 6 Due to the influence of other factors, the longitudinal cross-section of the final first protrusion 12 may have a variety of different shapes, such as... Figure 6 The isosceles trapezoid shown in (b) can also be as follows: Figure 8 The isosceles trapezoid shown in (a), or as shown in (a) Figure 8 The right trapezoid shown in (b), or as shown in Figure 8 The isosceles trapezoid shown in (c) has an upward convexity in the middle of its upper surface. In summary, this application does not limit the specific shape of the first protrusion 12.

[0071] refer to Figure 9 , Figure 9 yes Figure 5 A schematic diagram of the electromigration of the first bump 12 under different electron flow directions. For example, Figure 9 The electromigration experiment was conducted at an ambient temperature of 180°C.

[0072] Figure 9 In the diagram, (a) shows the case where electrons flow downwards, and (b) shows the case where electrons flow upwards; however, both cases can occur in practical applications. It can be seen that when electrons flow upwards, the first bump 12 has better integrity, is less prone to atomic electromigration, and is less likely to develop cracks. Therefore, in some alternative embodiments, the lower substrate 10 can be used as the negative electrode, and the upper bump base metal 13 as the positive electrode, thereby achieving the effect of electrons flowing upwards.

[0073] Continue to refer to Figure 5In some alternative embodiments, the package structure 5a further includes: a plurality of second bumps 14 electrically connected between the electronic component 11 and the substrate 10 and located in the central region of the electronic component 11, wherein the top width and bottom width of the second bumps 14 are substantially equal.

[0074] In some alternative embodiments, the central region of the lower surface of the electronic component 11 has a second bump base metal 15, to which a second bump 14 is connected, the width of the second bump base metal 15 being substantially equal to the bottom width of the second bump 14. (Refer to...) Figure 6 As shown in the formation process of the first bump 12, a second bump 14 with a top width substantially equal to its bottom width can be formed by making the widths of the bottom metal 15 and the silver-plated solder pad 18 substantially equal. Optionally, the actual shape of the second bump 14 can refer to existing technologies. Figure 3 That is, the second protrusion 14 can be an arc-shaped protrusion protruding from the side.

[0075] In some alternative embodiments, the width of the first bump base metal 13 is smaller than the width of the second bump base metal 15. In terms of manufacturing process, the width of the second bump base metal 15 can be as normally designed, while the width of the first bump base metal 13 can be smaller than normally designed. For example, the width of the second bump base metal 15 can be 100 micrometers (μm), and the width of the first bump base metal 13 can be 80 micrometers.

[0076] In some optional embodiments, the encapsulation structure 5a further includes: a molding layer 16, encapsulating the electronic component 11, the first bump 12, the second bump 14, and the upper surface of the substrate 10. Optionally, the sides of the molding layer 16 are substantially flush with the sides of the substrate 10. Here, the molding layer 16 can be formed of various molding compounds. Exemplary molding compounds may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0077] In some alternative implementations, package structure 5a is a square flat no-lead (QFN) type package structure.

[0078] refer to Figure 10 , Figure 10This is a schematic diagram of the longitudinal cross-sectional structure of the encapsulation structure 10a according to another embodiment of this application. Figure 10 As shown, the width of the first bump base metal 13 and the width of the second bump base metal 15 are substantially equal. For example, in the manufacturing process, the widths of the first bump base metal 13 and the second bump base metal 15 are both designed normally, and the silver-plated solder pad 18 below the second bump base metal 15 (see...) Figure 6 The width of the first bump base metal 13 is designed as normal, while the width of the silver-plated solder pad 18 below the first bump base metal 13 can be larger than the normal design.

[0079] For example, the width of the first bump base metal 13, the width of the second bump base metal 15, and the width of the silver-plated solder pad 18 below them are all 80 micrometers; the width of the silver-plated solder pad 18 below the first bump base metal 13 is 100 micrometers. Alternatively, the width of the first bump base metal 13, the width of the second bump base metal 15, and the width of the silver-plated solder pad 18 below them are all 100 micrometers; the width of the silver-plated solder pad 18 below the first bump base metal 13 is 120 micrometers.

[0080] refer to Figure 11 , Figure 11 This is a comparison diagram showing the combined effect of the first bump 12 (frustum bump) in the packaging structure 5a of this application and the bump 93 (arch bump) in the existing packaging structure 1a.

[0081] like Figure 11 As shown, compared to the bow-shaped bump (UBM: 100μm), the frustum bump (UBM: 80μm) under the same conditions (same tin-silver alloy, same current density, and downward electron flow direction), exhibits a 29% reduction in maximum current density, a 35% reduction in maximum stress, and an increase in Mean Time To Failure (MTTF) from 350.6 hours to 373.8 hours (a 6% increase), while the average temperature decreases slightly by 0.03℃. This demonstrates that the frustum bump offers significant advantages in reducing current density and stress, while simultaneously improving the reliability of the package structure and extending its service life.

[0082] refer to Figure 12 , Figure 12 This is a schematic diagram comparing the electromigration effect of the first bump 12 (frustum bump) in the packaging structure 5a of this application with the bump 93 (arch bump) in the existing packaging structure 1a.

[0083] Figure 12In the figure, RS / R0 represents the ratio of the current resistance to the initial resistance (i.e., the rate of resistance increase), which increases with the degree of electromigration. When RS / R0 reaches 10% and 50%, a significant crack appears under the bow-shaped bump, while the crack growth of the frustum bump is relatively mild. This indicates that, under the same current density conditions, the frustum bump has a lower probability of first failure and a longer lifespan. These experimental results verify the stability and reliability advantages of the frustum bump during electromigration.

[0084] refer to Figure 13 , Figure 13 This is a schematic diagram comparing the reliability of the first bump 12 (frustum bump) in the packaging structure 5a of this application with the bump 93 (arch bump) in the existing packaging structure 1a.

[0085] like Figure 13 As shown, this paper presents a comparison of the reliability of a frustum bump with a bottom metal width of 80 μm and an arc-shaped bump with a bottom metal width of 100 μm based on a log-normal distribution in electromigration experiments under the same current density. Figure 13 The horizontal axis represents time (t), and the vertical axis represents the failure probability (Unreliability F(t)). The results show that, under the same (equally short) electromigration test time, the failure probability of the 100μm arc-shaped bump package structure is significantly higher than that of the 80μm frustum bump. This indicates that the 80μm frustum bump exhibits higher reliability and a longer lifespan under the same current density conditions.

[0086] The packaging structure proposed in this application has been described above. By modifying the first bump 12 into a shape that is narrower at the top and wider at the bottom, this application can significantly reduce the maximum current density inside and increase the maximum current it can withstand, thereby improving electrical performance. Furthermore, it can also achieve the effect of reducing process temperature and structural stress, ultimately improving reliability and service life. For example, by applying the first bump 12, the packaging structure of this application can increase the lifespan (mean time to failure) by more than 5%, reduce the current density at the maximum by more than 20%, and reduce the stress concentration at the maximum by more than 20%.

[0087] The packaging structure of this application includes, but is not limited to, a QFN packaging structure, which can be applied to products including, but not limited to, PMICs. Generally, semiconductor packages that use bumps to terminate a component to a plane can also utilize the technical solutions of this application.

[0088] Although this application has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not limiting of this application. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this application as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this application and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this application may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this application. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this application.

Claims

1. A packaging structure, characterized in that, include: Substrate; Electronic components are disposed above the substrate; Multiple first bumps are electrically connected between the electronic component and the substrate and are located in the edge region of the electronic component. The longitudinal cross-section of the first bumps is narrow at the top and wide at the bottom.

2. The packaging structure according to claim 1, characterized in that, The longitudinal cross-section of the first protrusion is trapezoidal.

3. The packaging structure according to claim 1, characterized in that, The first bump is made of tin-silver alloy.

4. The packaging structure according to claim 1, characterized in that, The lower surface edge region of the electronic component has a first bump base metal, the first bump being connected to the first bump base metal, and the width of the first bump base metal being smaller than the bottom width of the first bump.

5. The packaging structure according to claim 4, characterized in that, The packaging structure further includes: a plurality of second bumps electrically connected between the electronic component and the substrate, and located in the central region of the electronic component, wherein the top width and bottom width of the second bumps are substantially equal.

6. The packaging structure according to claim 5, characterized in that, The electronic component has a second bump base metal in the central region of its lower surface, the second bump being connected to the second bump base metal, and the width of the second bump base metal being substantially equal to the bottom width of the second bump.

7. The packaging structure according to claim 4, characterized in that, The first bump base metal includes a copper pillar connected to the electronic component and a nickel layer disposed on the lower surface of the copper pillar.

8. The packaging structure according to claim 1, characterized in that, The ratio of the top width to the bottom width of the first protrusion is between 0.6 and 0.

9.

9. The packaging structure according to claim 1, characterized in that, The packaging structure further includes: a molding layer for encapsulating the electronic component.

10. The packaging structure according to claim 1, characterized in that, The substrate is a lead frame.

Images