A battery pack sampling detection circuit
By designing a battery pack sampling and detection circuit, the voltage and temperature of the battery pack are monitored in real time, abnormal individual cells are quickly identified and balanced, solving the problem of heat generation and damage to marine battery packs during charging and discharging, and improving the service life and safety of the battery pack.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHENJIANG MARINE ELECTRICAL APPLIANCE CO LTD
- Filing Date
- 2025-05-30
- Publication Date
- 2026-06-09
AI Technical Summary
During the charging and discharging process, marine battery packs may overheat, catch fire, or suffer damage to electrode materials, shortening their lifespan. Existing technologies make it difficult to effectively monitor and control the status of battery packs.
A battery pack sampling and detection circuit was designed, including voltage detection, temperature detection, voltage equalization and anti-interference sub-circuits. It is connected to an external terminal via CAN communication to monitor the voltage and temperature of the battery pack in real time, quickly identify abnormal individual cells and perform equalization control.
It enables precise detection and control of individual cells within the ship's battery pack, improving the battery pack's lifespan and safety.
Smart Images
Figure CN224341650U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of battery pack monitoring technology, specifically relating to a battery pack sampling and detection circuit. Background Technology
[0002] Battery packs are an important component of a ship's electrical system, primarily used to provide power, energy storage, and emergency power. Types include lead-acid and alkaline battery packs. During operation, these battery packs require continuous charging and discharging. Excessive charging voltage or prolonged charging time can cause the batteries to overheat or even catch fire, while excessively low discharge voltage can lead to irreversible damage to the electrode materials, shortening battery life. Utility Model Content
[0003] Purpose of the utility model: To provide a battery pack sampling and detection circuit that solves the above-mentioned problems existing in the prior art.
[0004] Technical Solution: A battery pack sampling and detection circuit includes a marine battery pack and several voltage detection sub-circuits. The input terminal of each voltage detection sub-circuit is connected to a single cell within the battery pack. The output terminal of the voltage detection sub-circuit is connected to the input terminal of chip U2. The output terminal of chip U2 is connected to the input terminal of chip U3. The input terminal of chip U3 is simultaneously connected to the output terminals of several temperature detection sub-circuits. The input terminal of each temperature detection sub-circuit is connected to a single cell within the battery pack. The output terminal of chip U3 is connected to an external terminal via CAN communication.
[0005] Preferably, it also includes several voltage equalization sub-circuits, the input terminal of each group of voltage equalization sub-circuits is connected to a single cell in the battery pack, and the output terminal of each group of voltage equalization sub-circuits is connected to the input terminal of chip U2. The voltage equalization sub-circuits are used for overvoltage discharge of single cells.
[0006] Preferably, the voltage equalization sub-circuit includes a resistor R2, a Zener diode D1, a transistor Q1, and a resistor R1. One end of the resistor R2 is connected to pin 20 of the chip U2, and the other end of the resistor R2 is connected to both the anode of the Zener diode D1 and the base of the transistor Q1. The emitter of the transistor is connected to both the cathode of the Zener diode D1 and one end of the single cell. The collector of the transistor Q1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the other end of the single cell.
[0007] Preferably, it further includes an anti-interference sub-circuit. The input terminal of the anti-interference sub-circuit is connected to the output terminal of chip U3, and the output terminal of the anti-interference sub-circuit is connected to an external terminal via CAN communication. The anti-interference sub-circuit includes chip U1, capacitor C10, capacitor C42, suppression diode D5, and suppression diode D6. One end of capacitor C10 is connected to both the positive terminal of capacitor C42 and pin 8 of chip U1. The other end of capacitor C10 is connected to the negative terminal of capacitor C42. One end of suppression diode D5 is connected to pin 6 of chip U1. The other end of suppression diode D5 is connected to one end of suppression diode D6. The other end of suppression diode D6 is connected to pin 7 of chip U1. Pin 2 of chip U1 is connected to pin 14 of chip U3, and pin 3 of chip U1 is connected to pin 13 of chip U3.
[0008] Preferably, chip U1 is an ISO1050 chip, chip U2 is an LTC6802 chip, and chip U3 is an MC9S08DZ60 chip.
[0009] Preferably, the voltage detection sub-circuit includes an optocoupler OC1, an optocoupler OC2, a diode D30, an adjusting resistor RT30, an amplifier A50, resistors R31, R32, and R33, and a capacitor C32. The positive terminal of the diode D30 is connected to one end of the single battery cell, and pin 2 of the optocoupler OC1 is connected to the other end of the single battery cell. The negative terminal of the diode D30 is connected to one end of the adjusting resistor RT30, and the other end of the adjusting resistor RT30 is connected to pin 1 of the optocoupler OC1. Pin 4 of the optocoupler OC1 is simultaneously connected to the positive input terminal of the amplifier A50 and pin 3 of the optocoupler OC2. The negative input terminal of the amplifier A50 is simultaneously connected to one end of resistor R32 and capacitor C32. The output terminal of the amplifier A50 is simultaneously connected to the other end of capacitor C32 and pin 1 of the optocoupler OC2. Pin 2 of the optocoupler OC2 is simultaneously connected to resistor R33 and the voltage detection input pin of chip U2.
[0010] Preferably, the temperature detection sub-circuit includes amplifiers LM258B and LM258A, resistors RT10, RT8, RT6, RT5, RT4, RT2, RT1, an adjusting resistor RMDZ1, and capacitors CT1, CT2, CT3, and CT4. Pin 7 of amplifier LM258B is simultaneously connected to one end of resistor RT10 and pin 25 of chip U3. Pin 6 of amplifier LM258B is simultaneously connected to the other end of resistor RT10 and one end of resistor RT8. The other end of resistor RT8 is simultaneously connected to pin 1 of amplifier LM258A and one end of resistor RT5. The other end of pin 5 is simultaneously connected to pin 2 of the amplifier LM258A and resistor RT6. Pin 3 of the amplifier LM258A is simultaneously connected to one end of capacitor CT1, the positive terminal of capacitor CT2, one end of resistor RT1, and one end of resistor RT2. The other end of resistor RT2 is simultaneously connected to the other end of capacitor CT1, the negative terminal of capacitor CT2, one end of adjusting resistor RMDZ1, one end of capacitor CT4, and the negative terminal of capacitor CT3. The other end of resistor RT1 is connected to one end of resistor RT4. The other end of resistor RT4 is simultaneously connected to the other end of adjusting resistor RMDZ1, the other end of capacitor CT4, the positive terminal of capacitor CT3, and pin 5 of amplifier LM258B.
[0011] Beneficial Effects: This utility model relates to a battery pack sampling and detection circuit. It utilizes a temperature detection sub-circuit to obtain the temperature of individual cells within the marine battery pack. By monitoring the temperature difference between the upper and lower wiring terminals, the temperature difference between individual cells can be calculated, allowing for the rapid identification of abnormal individual cells. Furthermore, a voltage detection sub-circuit detects the voltage of individual cells within the marine battery pack. Combined with a voltage balancing sub-circuit, it balances and controls over-voltage cells, adjusting them to a normal state. Through the combined use of the voltage and temperature detection sub-circuits, precise detection and control of individual cells within the marine battery pack can be achieved, thereby extending the battery pack's lifespan. Attached Figure Description
[0012] Figure 1 This is the overall circuit diagram of this utility model. Detailed Implementation
[0013] like Figure 1As shown, this utility model provides a technical solution: a battery pack sampling and detection circuit, including a marine battery pack, and several voltage detection sub-circuits. The input terminal of each voltage detection sub-circuit is connected to a single cell within the battery pack. The output terminal of each voltage detection sub-circuit is connected to the input terminal of chip U2. The output terminal of chip U2 is connected to the input terminal of chip U3. The input terminal of chip U3 is simultaneously connected to the output terminals of several temperature detection sub-circuits. The input terminal of each temperature detection sub-circuit is connected to a single cell within the battery pack. The output terminal of chip U3 is connected to an external terminal via CAN communication. The battery pack includes several voltage equalization sub-circuits. The input of each sub-circuit is connected to a single cell within the battery pack, and the output is connected to the input of chip U2. These voltage equalization sub-circuits are used for overvoltage discharge of individual cells. The pack also includes an anti-interference sub-circuit. The input of this anti-interference sub-circuit is connected to the output of chip U3, and its output is connected to an external terminal via CAN communication. The anti-interference sub-circuit includes chip U1, capacitors C10 and C42, a suppression diode D5, and a suppression diode D6. One end of capacitor C10 is simultaneously connected to the positive terminal of capacitor C42. The capacitor C10 is connected to pin 8 of chip U1, and the other end of capacitor C10 is connected to the negative terminal of capacitor C42. One end of the suppression diode D5 is connected to pin 6 of chip U1, and the other end of suppression diode D5 is connected to one end of suppression diode D6. The other end of suppression diode D6 is connected to pin 7 of chip U1. Pin 2 of chip U1 is connected to pin 14 of chip U3, and pin 3 of chip U1 is connected to pin 13 of chip U3. Chip U1 is an ISO1050 type chip, chip U2 is an LTC6802 type chip, and chip U3 is an MC9 type chip. The S08DZ60 chip uses a temperature detection subcircuit to obtain the temperature of individual cells within the marine battery pack. By monitoring the temperature difference between the upper and lower terminals, it calculates the temperature difference between individual cells, allowing for quick identification of abnormal cells. It also uses a voltage detection subcircuit to detect the voltage of individual cells within the pack, and in conjunction with a voltage balancing subcircuit, it balances and adjusts over-voltage cells to normal conditions. Through this combination of voltage and temperature detection subcircuits, precise detection and control of individual cells within the marine battery pack can be achieved, extending the battery pack's lifespan.
[0014] In a further embodiment, each group of individual batteries is connected to a separate voltage equalization sub-circuit. The voltage equalization sub-circuit includes a resistor R2, a Zener diode D1, a transistor Q1, and a resistor R1. One end of the resistor R2 is connected to pin 20 of the chip U2, and the other end of the resistor R2 is connected to both the anode of the Zener diode D1 and the base of the transistor Q1. The emitter of the transistor is connected to both the cathode of the Zener diode D1 and one end of the individual battery. The collector of the transistor Q1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the other end of the individual battery. When an individual battery experiences overvoltage, the transistor Q1 conducts to discharge the overvoltaged individual battery. The discharged electrical energy is consumed through the resistor R1, restoring the overvoltaged individual battery to its normal state.
[0015] In a further embodiment, the voltage detection sub-circuit includes an optocoupler OC1, an optocoupler OC2, a diode D30, a regulating resistor RT30, an amplifier A50, resistors R31, R32, and R33, and a capacitor C32. The positive terminal of the diode D30 is connected to one end of the single battery cell, and pin 2 of the optocoupler OC1 is connected to the other end of the single battery cell. The negative terminal of the diode D30 is connected to one end of the regulating resistor RT30, and the other end of the regulating resistor RT30 is connected to pin 1 of the optocoupler OC1. Pin 4 of the optocoupler OC1 is simultaneously connected to the positive input terminal of the amplifier A50 and pin 3 of the optocoupler OC2. The negative input terminal of amplifier A50 is simultaneously connected to resistor R32, one end of resistor R32 and capacitor C32, and the output terminal of amplifier A50 is simultaneously connected to the other end of capacitor C32 and pin 1 of optocoupler OC2. Pin 2 of optocoupler OC2 is simultaneously connected to resistor R33 and the voltage detection input pin of chip U2. When the voltage of a single cell is detected, the voltage of the single cell forms a circuit with the light-emitting diode in optocoupler OC1 through resistor RT30, converting the voltage signal into a current signal. The amplifier A50 compares and provides feedback, and by observing the conduction state of optocoupler OC2 and optocoupler OC1, the overvoltage status of the current single cell can be directly obtained.
[0016] In a further embodiment, the temperature detection subcircuit includes amplifiers LM258B and LM258A, resistors RT10, RT8, RT6, RT5, RT4, RT2, RT1, an adjusting resistor RMDZ1, and capacitors CT1, CT2, CT3, and CT4. The adjusting resistor RMDZ1 is a thermistor, attached to the outside of the individual battery cell. Pin 7 of amplifier LM258B is connected to one end of resistor RT10 and pin 25 of chip U3. Pin 6 of amplifier LM258B is connected to the other end of resistor RT10 and one end of resistor RT8. The other end of resistor RT8 is connected to pin 1 of amplifier LM258A. One end of resistor RT5 is connected to the other end of the amplifier LM258A and resistor RT6. One end of the amplifier LM258A is connected to one end of capacitor CT1, the positive terminal of capacitor CT2, one end of resistor RT1 and one end of resistor RT2. The other end of resistor RT2 is connected to the other end of capacitor CT1, the negative terminal of capacitor CT2, one end of regulating resistor RMDZ1, one end of capacitor CT4 and the negative terminal of capacitor CT3. The other end of resistor RT1 is connected to one end of resistor RT4. The other end of resistor RT4 is connected to the other end of regulating resistor RMDZ1, the other end of capacitor CT4, the positive terminal of capacitor CT3 and one end of amplifier LM258B.
[0017] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and all such equivalent transformations fall within the protection scope of the present invention.
Claims
1. A battery pack sampling and detection circuit, comprising a marine battery pack, characterized in that, It also includes several voltage detection sub-circuits. The input terminal of each voltage detection sub-circuit is connected to a single cell in the battery pack. The output terminal of the voltage detection sub-circuit is connected to the input terminal of chip U2. The output terminal of chip U2 is connected to the input terminal of chip U3. The input terminal of chip U3 is simultaneously connected to the output terminals of several temperature detection sub-circuits. The input terminal of each temperature detection sub-circuit is connected to a single cell in the battery pack. The output terminal of chip U3 is connected to an external terminal via CAN communication.
2. The battery pack sampling and detection circuit according to claim 1, characterized in that, It also includes several voltage equalization sub-circuits. The input terminal of each voltage equalization sub-circuit is connected to a single cell in the battery pack, and the output terminal of each voltage equalization sub-circuit is connected to the input terminal of chip U2. The voltage equalization sub-circuit is used for overvoltage discharge of a single cell.
3. The battery pack sampling and detection circuit according to claim 2, characterized in that, The voltage equalization sub-circuit includes a resistor R2, a Zener diode D1, a transistor Q1, and a resistor R1. One end of the resistor R2 is connected to pin 20 of the chip U2, and the other end of the resistor R2 is connected to both the anode of the Zener diode D1 and the base of the transistor Q1. The emitter of the transistor is connected to both the cathode of the Zener diode D1 and one end of the single cell. The collector of the transistor Q1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the other end of the single cell.
4. The battery pack sampling and detection circuit according to claim 1, characterized in that, It also includes an anti-interference sub-circuit. The input terminal of the anti-interference sub-circuit is connected to the output terminal of chip U3, and the output terminal of the anti-interference sub-circuit is connected to an external terminal via CAN communication. The anti-interference sub-circuit includes chip U1, capacitor C10, capacitor C42, suppression diode D5, and suppression diode D6. One end of capacitor C10 is connected to both the positive terminal of capacitor C42 and pin 8 of chip U1, and the other end of capacitor C10 is connected to the negative terminal of capacitor C42. One end of suppression diode D5 is connected to pin 6 of chip U1, and the other end of suppression diode D5 is connected to one end of suppression diode D6. The other end of suppression diode D6 is connected to pin 7 of chip U1. Pin 2 of chip U1 is connected to pin 14 of chip U3, and pin 3 of chip U1 is connected to pin 13 of chip U3.
5. A battery pack sampling and detection circuit according to claim 1, characterized in that, Chip U1 is an ISO1050 chip, chip U2 is an LTC6802 chip, and chip U3 is an MC9S08DZ60 chip.
6. A battery pack sampling and detection circuit according to claim 1, characterized in that, The voltage detection sub-circuit includes optocoupler OC1, optocoupler OC2, diode D30, regulating resistor RT30, amplifier A50, resistors R31, R32, and R33, and capacitor C32. The positive terminal of diode D30 is connected to one end of the single cell, and pin 2 of optocoupler OC1 is connected to the other end of the single cell. The negative terminal of diode D30 is connected to one end of regulating resistor RT30, and the other end of regulating resistor RT30 is connected to pin 1 of optocoupler OC1. Pin 4 of optocoupler OC1 is simultaneously connected to the positive input terminal of amplifier A50 and pin 3 of optocoupler OC2. The negative input terminal of amplifier A50 is simultaneously connected to one end of resistor R32 and capacitor C32. The output terminal of amplifier A50 is simultaneously connected to the other end of capacitor C32 and pin 1 of optocoupler OC2. Pin 2 of optocoupler OC2 is simultaneously connected to resistor R33 and the voltage detection input pin of chip U2.
7. A battery pack sampling and detection circuit according to claim 1, characterized in that, The temperature detection sub-circuit includes amplifiers LM258B and LM258A, resistors RT10, RT8, RT6, RT5, RT4, RT2, RT1, an adjusting resistor RMDZ1, and capacitors CT1, CT2, CT3, and CT4. Pin 7 of amplifier LM258B is connected to one end of resistor RT10 and pin 25 of chip U3. Pin 6 of amplifier LM258B is connected to the other end of resistor RT10 and one end of resistor RT8. The other end of resistor RT8 is connected to pin 1 of amplifier LM258A and one end of resistor RT5. The resistor RT5... The other end is connected to pin 2 of the amplifier LM258A and resistor RT6. Pin 3 of the amplifier LM258A is connected to one end of capacitor CT1, the positive terminal of capacitor CT2, one end of resistor RT1, and one end of resistor RT2. The other end of resistor RT2 is connected to the other end of capacitor CT1, the negative terminal of capacitor CT2, one end of adjusting resistor RMDZ1, one end of capacitor CT4, and the negative terminal of capacitor CT3. The other end of resistor RT1 is connected to one end of resistor RT4. The other end of resistor RT4 is connected to the other end of adjusting resistor RMDZ1, the other end of capacitor CT4, the positive terminal of capacitor CT3, and pin 5 of amplifier LM258B.