Display device

Abstract

The application relates to a display device, which comprises a main chip, a signal conversion circuit and a display platform. The main chip outputs a 16-channel V-by-One signal carrying a target picture; the signal conversion circuit comprises a first signal conversion module, a second signal conversion module and a signal splicing module; the first signal conversion module is connected with the main chip and is used for converting the 16-channel V-by-One signal into a 16-channel LVDS differential signal; the second signal conversion module is connected with the first signal conversion module and is used for converting the 16-channel LVDS differential signal into a plurality of 4-channel first HDMI signals; the signal splicing module is connected with the second signal conversion module and is used for splicing the plurality of 4-channel first HDMI signals to output a second HDMI signal, and the bit number of the second HDMI signal comprises 10 bits; the display platform is connected with the signal conversion circuit and is used for receiving the second HDMI signal to display the target picture. The application can convert the 16-channel V-by-One signal into the 10-bit second HDMI signal at low cost.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to display devices. Background Technology

[0002] As the resolution and performance of display devices continue to improve, the demands for data transmission and signal conversion are becoming increasingly complex. V-by-One is a high-speed serial interface widely used in high-resolution display devices, capable of efficiently transmitting large amounts of image data. However, in some applications, it is necessary to convert V-by-One signals (a high-speed serial interface standard) to other standard interface signals, such as HDMI (High-Definition Multimedia Interface) signals, to ensure compatibility with existing display devices.

[0003] Currently, converting 16-channel V-by-One signals to HDMI signals is typically achieved using FPGA (Field-Programmable Gate Array) technology. FPGAs offer high flexibility and programmability, enabling rapid processing and conversion of complex signals. By writing specific logic programs, FPGAs can receive, decode, and encode and output V-by-One signals as HDMI signals.

[0004] However, FPGA technology has a significant disadvantage in terms of cost. On the one hand, the price of FPGA chips themselves is relatively high. On the other hand, FPGA development and debugging require specialized technical personnel and a complex development environment, which further increases development costs and time costs. Utility Model Content

[0005] Therefore, it is necessary to address the issue of high cost in converting V-by-One signals to HDMI signals by providing a display device that can reduce the cost of this conversion.

[0006] In a first aspect, this application provides a display device, comprising:

[0007] The main chip is used to output 16 channels of V-by-One signals carrying the target image; the number of bits of the 16 channels of V-by-One signals includes 10 bits.

[0008] The signal conversion circuit includes a first signal conversion module, a second signal conversion module, and a signal splicing module;

[0009] The first signal conversion module is connected to the main chip and is used to access the 16-channel V-by-One signal;

[0010] The second signal conversion module is connected to the first signal conversion module and is used to receive 16 channels of LVDS differential signals; the 16 channels of LVDS differential signals are generated by the first signal conversion module by converting the 16 channels of V-by-One signals.

[0011] The signal splicing module is connected to the second signal conversion module and is used to access multiple 4-channel first HDMI signals; the first HDMI signal has 8 bits; the 4-channel first HDMI signal is generated by the second signal conversion module by converting the 16-channel LVDS differential signal.

[0012] The display platform is connected to the signal conversion circuit and is used to receive the second HDMI signal to display the target image; the second HDMI signal has 10 bits; the second HDMI signal is generated by the signal splicing module by splicing multiple 4-channel first HDMI signals.

[0013] Beneficial Effects: The aforementioned display device includes a main chip, a signal conversion circuit, and a display platform. The main chip outputs 16 channels of V-by-One signals carrying the target image. The signal conversion circuit includes a first signal conversion module, a second signal conversion module, and a signal splicing module. The first signal conversion module is connected to the main chip and receives the 16 channels of V-by-One signals, converting them into 16 channels of LVDS differential signals. The second signal conversion module is connected to the first signal conversion module and receives the 16 channels of LVDS differential signals, converting them into multiple 4-channel first HDMI signals. The first HDMI signal has 8 bits. The signal splicing module is connected to the second signal conversion module and splices the multiple 4-channel first HDMI signals to output a second HDMI signal, which has 10 bits. The display platform is connected to the signal conversion circuit and receives the second HDMI signal to display the target image. As can be seen, by connecting the signal splicing module and the second signal conversion module in this application, multiple 8-bit first HDMI signals can be converted into 10-bit second HDMI signals, which can effectively improve the display performance of the display device, and eliminates the need to use high-cost FPGA chips, thus reducing the cost of signal conversion.

[0014] In one embodiment, the first signal conversion module includes:

[0015] The system comprises four first sub-modules, each equipped with a V-By-One signal input interface and an LVDS differential signal output interface. The V-By-One signal input interface is connected to the main chip to receive 16 channels of the V-by-One signal, and the LVDS differential signal output interface is connected to the second signal conversion module to output 16 channels of the LVDS differential signal to the second signal conversion module.

[0016] Beneficial effects: By processing 16 channels of V-by-One signals through four first sub-modules, each first sub-module can process 4 channels of V-by-One signals, which can speed up the conversion speed of V-by-One signals by the display device and improve the overall signal conversion efficiency.

[0017] In one embodiment, the second signal conversion module includes:

[0018] The system comprises four second sub-modules, each equipped with an LVDS differential signal input interface and an HDMI signal output interface. The LVDS differential signal input interface of one second sub-module is connected to the LVDS differential signal output interface of one first sub-module, and the HDMI signal output interface of each second sub-module is connected to the signal splicing module for transmitting four channels of the first HDMI signal.

[0019] Beneficial effects: The main chip outputs complete 16-channel V-By-One signals corresponding to 4K 120Hz (16-channel) image data. These 16 channels are divided into four groups of four, transmitted to a first submodule 211. Each submodule receives 25% of the image data. The first submodule converts the four-channel V-By-One signals into LVDS differential signals and outputs them to the corresponding connected second submodules. Each second submodule receives 25% of the LVDS image data and converts the corresponding LVDS differential signal into a first HDMI signal. This process does not require FPGA implementation, reducing signal conversion costs.

[0020] In one embodiment, each of the first submodules is configured with a first configuration pin; each of the second submodules is configured with a second configuration pin; the signal splicing module is configured with a third configuration pin; and the signal conversion circuit further includes:

[0021] The main control module is connected to the first configuration pin of each first sub-module, the second configuration pin of each second sub-module, and the third configuration pin of the signal splicing module, respectively, and is used to output corresponding configuration signals to each first configuration pin, second configuration pin, and third configuration pin; the configuration signals are used to configure the working state of each first sub-module, each second sub-module, and the signal splicing module.

[0022] Beneficial effects: The main control module configures each first sub-module, each second sub-module, and the signal splicing module, ensuring the normal operation of each first sub-module, each second sub-module, and the signal splicing module 230, and ensuring the stable output of the 10-bit second HDMI signal.

[0023] In one embodiment, the different configuration signals include a first configuration signal, a second configuration signal, and a third configuration signal; the main control module includes:

[0024] The main control unit is connected to the first configuration pin of each of the first sub-modules and is used to output the first configuration signal to each of the first sub-modules.

[0025] The control unit is connected to the second configuration pin of the signal splicing module and each of the second sub-modules, respectively, for outputting the third configuration signal to the signal splicing module and the second configuration signal to each of the second sub-modules.

[0026] Beneficial effects: The main control module can include a main control unit and a slave control unit. The main control unit is connected to the first configuration pin of each first submodule and is used to output a first configuration signal to each first submodule. The slave control unit is connected to the second configuration pin of the signal splicing module and each second submodule and is used to output a third configuration signal to the signal splicing module and a second configuration signal to each second submodule, thereby achieving efficient configuration of each first submodule, each second submodule, and the signal splicing module.

[0027] In one embodiment, the slave control unit is configured with a first slave I2C port; the second configuration pin is of the type including an I2C communication pin, and the second configuration pin is connected to the first slave I2C port of the slave control unit through an I2C bus to transmit the second configuration signal output by the slave control unit to each of the second sub-modules.

[0028] Beneficial effects: The second configuration signal is transmitted between the control unit and each second sub-module via the I2C bus. The I2C bus only requires two lines, namely the serial data line and the serial clock line, which can simplify the circuit structure and reduce the complexity and cost of the display device.

[0029] In one embodiment, each of the second submodules is configured with an address configuration pin, the address configuration pin being connected to the second configuration pin; the signal conversion circuit further includes:

[0030] The first voltage divider module includes a first voltage divider unit, a second voltage divider unit, a third voltage divider unit, and a fourth voltage divider unit. The first terminals of the first voltage divider unit and the second voltage divider unit are both used to receive a first voltage signal. The second terminal of the first voltage divider unit is connected to the address configuration pin of the third voltage divider unit and one of the four second sub-modules. The second terminal of the second voltage divider unit is connected to the first terminal of the fourth voltage divider unit and the address configuration pins of the other three second sub-modules. The second terminals of the third voltage divider unit and the fourth voltage divider unit are connected to an equivalent ground terminal.

[0031] Among them, at least two of the first voltage divider unit, the second voltage divider unit, the third voltage divider unit and the fourth voltage divider unit have different voltage division parameters, so that after the first voltage signal is divided, the corresponding voltage is configured to the second configuration pin through the address configuration pin.

[0032] Beneficial effects: By configuring the voltage of the address configuration pins of each second submodule through the first voltage divider unit, the second voltage divider unit, the third voltage divider unit, and the fourth voltage divider unit, the four second submodules can be managed independently, improving the configuration efficiency of the address configuration pins.

[0033] In one embodiment, the slave control unit is configured with a second slave I2C port; the third configuration pin is of the type of I2C communication pin, and the third configuration pin is connected to the second slave I2C port via a 2C bus to transmit the third configuration signal output by the slave control unit to each of the signal splicing modules.

[0034] Beneficial effects: The transmission of the third configuration signal between the control unit and the signal splicing module is achieved through the I2C bus. The I2C bus only requires two lines, namely the serial data line and the serial clock line, which can simplify the circuit structure and reduce the complexity and cost of the display device.

[0035] In one embodiment, the first signal conversion module is configured with a power supply pin; the signal conversion circuit further includes:

[0036] The second voltage divider module is connected to the power supply pin and is used to convert the input second voltage signal into a power supply signal of the target voltage, and output the power supply signal to the power supply pin to supply power to the first signal conversion module.

[0037] Beneficial effects: By connecting the second voltage divider module to the power supply pin, the input second voltage signal is converted into a power supply signal that meets the target voltage required for the normal operation of the first signal conversion module. This power supply signal is then output to the power supply pin to power the first signal conversion module, providing a foundation for its normal operation. For example, the second voltage divider module can convert a 3.3V second voltage signal into a target voltage of 1.8V, ensuring the safe operation of the first signal conversion module.

[0038] In one embodiment, the display platform includes a liquid crystal display screen.

[0039] Beneficial effects: The LCD screen receives a 10-bit second HDMI signal, which can provide 1024 levels of grayscale for the LCD screen, enabling the LCD screen to present the color changes of the target image more delicately and improve the display performance of the display device. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is one of the schematic block diagrams of the display device in one embodiment of this application;

[0042] Figure 2 This is a schematic block diagram of the structure of the first signal conversion module in one embodiment of this application;

[0043] Figure 3 This is a schematic diagram of clock signal transmission between the first signal conversion module and the second signal conversion module in one embodiment of this application;

[0044] Figure 4 This is a schematic block diagram of the structure of the second signal conversion module in one embodiment of this application;

[0045] Figure 5 This is a schematic diagram of the operation of the first submodule, the second submodule, and the signal splicing module in one embodiment of this application;

[0046] Figure 6 This is a second schematic block diagram of the structure of a display device in one embodiment of this application;

[0047] Figure 7 This is a schematic block diagram of the main control module in one embodiment of this application;

[0048] Figure 8 This is a schematic diagram of the structure of the first voltage divider module in one embodiment of this application;

[0049] Figure 9 This is the third schematic block diagram of the display device in one embodiment of this application.

[0050] Explanation of icon numbers:

[0051] 100: Main chip; 200: Signal conversion circuit; 210: First signal conversion module; 211: First sub-module; 220: Second signal conversion module; 221: Second sub-module; 230: Signal splicing module; 240: Main control module; 241: Main control unit; 242: Slave control unit; 250: First voltage divider module; 251: First voltage divider unit; 252: Second voltage divider unit; 253: Third voltage divider unit; 254: Fourth voltage divider unit; 260: Second voltage divider module; 300: Display platform. Detailed Implementation

[0052] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0053] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0054] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0055] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0056] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0057] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0058] See Figure 1 , Figure 1 This illustration shows one of the structural schematic diagrams of a display device according to an embodiment of this application. The display device provided in this embodiment includes a main chip 100, a signal conversion circuit 200, and a display platform 300. The main chip 100 is used to output a 16-channel V-by-One signal carrying a target image. The signal conversion circuit 200 includes a first signal conversion module 210, a second signal conversion module 220, and a signal splicing module 230.

[0059] The first signal conversion module 210 is connected to the main chip 100 and is used to access 16 channels of V-by-One signals.

[0060] The second signal conversion module 220 is connected to the first signal conversion module 210 and is used to access 16 channels of LVDS (Low-Voltage Differential Signaling) differential signals.

[0061] The 16-channel LVDS differential signal is generated by the first signal conversion module 210 by converting the 16-channel V-by-One signal.

[0062] The signal splicing module 230 is connected to the second signal conversion module 220 and is used to receive multiple 4-channel first HDMI signals. The first HDMI signal has 8 bits.

[0063] Multiple 4-channel first HDMI signals are generated by the second signal conversion module 220 by converting 16-channel LVDS differential signals.

[0064] The display platform 300 is connected to the signal conversion circuit 200 and is used to receive the second HDMI signal to display the target image. The second HDMI signal has 10 bits.

[0065] The second HDMI signal is generated by the signal splicing module 230 by splicing multiple 4-channel first HDMI signals.

[0066] The 16-channel V-by-One signal output by the main chip 100, carrying the target image, can include multiple multi-channel V-by-One signals. For example, the main chip 100 can output four 4-channel V-by-One signals to the signal conversion circuit 200. The V-by-One signals can be 4K, 120Hz signals, enabling the display device to provide a higher resolution image. The 16-channel V-by-One signal can have 10 bits.

[0067] The first signal conversion module 210 can be any module capable of converting a V-by-One signal to an LVDS differential signal. For example, the THCV216 chip, the THCV226 chip, etc., are not limited to this.

[0068] The first signal conversion module 210 supports 4 channels of V-by-One signal input and 6 pairs of LVDS differential signal input, including 1 pair of clock signals and 5 pairs of data signals. According to the LVDS protocol standard, one data signal pair can transmit 7 bits of data in one clock cycle. The 5 data signal pairs output by the first signal conversion module 210 can transmit a maximum of 35 bits of signal in one clock cycle. Since a 10-bit color depth signal requires the transmission of 30 bits of data at a time, the first signal conversion module 210 can fully realize the transmission of 10-bit data, providing a foundation for realizing 10-bit second HDMI signal conversion and transmission. It can be understood that by defining the relevant functional pins of the first signal conversion module 210, 16 channels of V-by-One signal input and 16 channels of LVDS differential signal output can be achieved.

[0069] The second signal conversion module 220 can be any module capable of converting LVDS differential signals into first HDMI signals. Examples include ADV7613 chips, IT6263 chips, a combination of DS90CR486 and TFP410 chips, LT2611UXE chips, etc., and are not limited to these.

[0070] The first HDMI signal can be either an HDMI 1.0 signal or an HDMI 2.0 signal, but is not limited to this.

[0071] The signal splicing module 230 can be any module capable of splicing signals to achieve the function of outputting a 10-bit second HDMI signal in the embodiments of this application. For example, the LT8642UXE chip, but not limited thereto.

[0072] In this embodiment, by connecting the signal splicing module 230 with the second signal conversion module 220, multiple 8-bit first HDMI signals can be converted into 10-bit second HDMI signals, which can effectively improve the display performance of the display device and reduce the cost of signal conversion without using high-cost FPGA chips.

[0073] Combination Figure 2 and attached Figure 3 As shown, Figure 2 A schematic block diagram of the structure of the first signal conversion module 210 in one embodiment of this application is shown, with appended... Figure 3 This diagram illustrates the clock signal transmission between a first signal conversion module 210 and a second signal conversion module 220 according to one embodiment of this application. In some embodiments, the second signal conversion module 220 may include four first sub-modules 211, namely first sub-module 211#1, first sub-module 211#2, first sub-module 211#3, and first sub-module 211#4. Each second sub-module 221 is configured with an LVDS differential signal input interface and an HDMI signal output interface. The LVDS differential signal input interface of one second sub-module 221 is connected to the LVDS differential signal output interface of one first sub-module 211, and the HDMI signal output interface of each second sub-module 221 is connected to the signal splicing module 230 for transmitting four channels of first HDMI signals respectively.

[0074] Each first submodule 211 can process 4 channels of V-By-One signals, convert them into 6 pairs of LVDS differential signals, and transmit 25% of the image data to the second signal conversion module 220. The second signal conversion module 220 has only 1 pair of clock inputs and 20 pairs of data inputs, therefore it can be configured as shown in the attached diagram. Figure 3As shown, any one of the four pairs of clock signals in the first submodule 211 can be selected and transmitted to the second signal conversion module 220. The six pairs of LVDS differential signals include one pair of clock signals and five pairs of data signals.

[0075] In this embodiment, 16 channels of V-by-One signals are processed by four first sub-modules 211. Each first sub-module 211 can process 4 channels of V-by-One signals, which can speed up the conversion speed of V-by-One signals by the display device and improve the overall signal conversion efficiency.

[0076] Combined with appendix Figure 4 and attached Figure 5 , attached Figure 4 A schematic block diagram of the structure of the second signal conversion module 220 in one embodiment of this application is shown, with appended... Figure 5 The diagram illustrates the operation of the first submodule 211, the second submodule 221, and the second splicing module in one embodiment of this application. The second signal conversion module 220 provided in this embodiment may include four second submodules 221, namely second submodule 221#1, second submodule 221#2, second submodule 221#3, and second submodule 221#4.

[0077] Each second submodule 221 is equipped with an LVDS differential signal input interface and an HDMI signal output interface. The LVDS differential signal input interface of one second submodule 221 is connected to the LVDS differential signal output interface of one first submodule 211 respectively. The HDMI signal output interface of each second submodule 221 is connected to the signal splicing module 230 for transmitting four channels of first HDMI signals respectively.

[0078] In this embodiment, the main chip 100 outputs 16 channels of V-By-One signals corresponding to the complete 4K 120Hz (16 channels) image data. These 16 channels of V-By-One signals are divided into four groups of four, each group containing four channels of V-By-One signals, and transmitted to a first submodule 211. Each submodule receives 25% of the image data. The first submodule 211 converts the four channels of V-By-One signals into LVDS differential signals and outputs them to the corresponding connected second submodule 221. Each second submodule 221 receives 25% of the LVDS image data and converts the corresponding LVDS differential signals into first HDMI signals. This process does not require FPGA implementation, thus reducing signal conversion costs.

[0079] Each second submodule 221 transmits the converted first HDMI signal to the splicing module. The first HDMI signals output by each second submodule 221 of the splicing module are spliced ​​together to complete the restoration and output of the complete image. In this embodiment, the signal splicing module 230 can support up to four input channels of first HDMI signals. During operation of the signal splicing module 230, the line connections between the four channels of first HDMI signals and second HDMI signals can be completed based on the preset definitions of the relevant functional pins in the signal splicing module 230.

[0080] In some embodiments, when the signal splicing module 230 is enabled, its voltage can also be configured. For example, a preset voltage (e.g., 0V) is connected to the address configuration pin ADDR of the signal splicing module 230 via a voltage divider unit, thereby completing the configuration of the signal splicing module 230. It is understood that other necessary functional circuits can also be set to perform necessary configurations on the signal splicing module 230 in this embodiment, and are not limited to the above example.

[0081] See appendix Figure 5 The signal splicing module 230 can splice and integrate the received four first HDMI signals and output a 10-bit second HDMI signal corresponding to the complete target image, avoiding the use of FPGA for signal conversion and achieving high-performance graphics display at low cost.

[0082] Combined with appendix Figure 6 , attached Figure 6 This is a second schematic block diagram of a display device according to an embodiment of the present application. In the display device provided in this embodiment, each first submodule 211 is configured with a first configuration pin; each second submodule 221 is configured with a second configuration pin; and the signal splicing module 230 is configured with a third configuration pin. The signal conversion circuit 200 may further include a main control module 240.

[0083] The main control module 240 is connected to the first configuration pin of each first submodule 211, the second configuration pin of each second submodule 221, and the third configuration pin of the signal splicing module 230, respectively, and is used to output corresponding configuration signals to each first configuration pin, second configuration pin, and third configuration pin; the configuration signals are used to configure the working state of each first submodule 211, each second submodule 221, and the signal splicing module 230.

[0084] The main control module 240 can be any microcomputer chip capable of signal transmission and processing. For example, the main control module 240 can be an MCU (Microcontroller Unit). The main control module 240 can communicate with an external host computer to configure each of the first sub-modules 211, each of the second sub-modules 221, and the signal splicing module 230, ensuring their normal operation.

[0085] For example, the main control module 240 can be configured with an I2C (Inter-Integrated Circuit) communication port to establish communication connections with each first submodule 211, each second submodule 221 and the signal splicing module 230 through the I2C communication port, so as to transmit corresponding configuration signals to each first submodule 211, each second submodule 221 and the signal splicing module 230, thereby realizing the functional configuration of each first submodule 211, each second submodule 221 and the signal splicing module 230.

[0086] Combined with appendix Figure 7 , attached Figure 7 A schematic block diagram of the main control module 240 in one embodiment of this application is shown.

[0087] The display device provided in this application embodiment includes a first configuration signal, a second configuration signal, and a third configuration signal.

[0088] The main control module 240 may include a main control unit 241 and a slave control unit 242. The main control unit 241 is connected to the first configuration pin of each first submodule 211 and is used to output a first configuration signal to each first submodule 211.

[0089] The control unit 242 is connected to the second configuration pins of the signal splicing module 230 and each of the second sub-modules 221 respectively, for outputting a third configuration signal to the signal splicing module 230 and a second configuration signal to each of the second sub-modules 221.

[0090] To improve the signal transmission efficiency between the main control module 240 and each first sub-module 211, each second sub-module 221 and the signal splicing module 230, a main control unit 241 and a slave control unit 242 are used to configure each first sub-module 211, each second sub-module 221 and the signal splicing module 230.

[0091] The main control unit 241 and the slave control unit 242 can be of the same type. For example, both the main control unit 241 and the slave control unit 242 can be MCUs. The main control unit 241 can also be connected to the slave control unit 242. After receiving a power-on signal, the main control unit 241 outputs a corresponding start signal to the slave control unit 242, causing the slave control unit 242 to start working.

[0092] Furthermore, the control unit 242 can adjust the amplitude of the first HDMI signal and the second HDMI signal output by correspondingly transmitting the second configuration signal and the third configuration signal to the signal splicing module 230 and each second sub-module 221. The transmission of the corresponding second configuration signal and the third configuration signal can be interrupted by outputting a preset level state (e.g., high level) control signal to the interrupt pins in the signal splicing module 230 and each second sub-module 221. The corresponding signal splicing module 230 and each second sub-module 221 can be reset by outputting a corresponding level state (e.g., high level) control signal to the reset pins in the splicing module and the second sub-module 221.

[0093] In this embodiment, the main control module 240 may include a main control unit 241 and a slave control unit 242. The main control unit 241 is connected to the first configuration pin of each first submodule 211 and is used to output a first configuration signal to each first submodule 211. The slave control unit 242 is connected to the second configuration pin of the signal splicing module 230 and each second submodule 221 and is used to output a third configuration signal to the signal splicing module 230 and a second configuration signal to each second submodule 221, thereby achieving efficient configuration of each first submodule 211, each second submodule 221 and the signal splicing module 230.

[0094] In some embodiments, the control unit is configured with a first slave I2C port; the second configuration pin is of the type of I2C communication pin, and the second configuration pin is connected to the first slave I2C port of the control unit via an I2C bus to transmit the second configuration signal output from the control unit to each second submodule.

[0095] In this embodiment, the transmission of the second configuration signal between the control unit and each second sub-module is achieved through the I2C bus. The I2C bus only requires two lines, namely the serial data line and the serial clock line, which can simplify the circuit structure and reduce the complexity and cost of the display device.

[0096] In some embodiments, the display device provided in this application includes a second submodule 221 configured with an address configuration pin ADDR, which is connected to a second configuration pin. The signal conversion circuit 200 may include a first voltage divider module 250. (See attached diagram.) Figure 8 , attachedFigure 8 A schematic diagram of the structure of the first voltage divider module 250 in one embodiment of this application is shown.

[0097] The first voltage divider module 250 may include a first voltage divider unit 251, a second voltage divider unit 252, a third voltage divider unit 253, and a fourth voltage divider unit 254. The first terminals of the first voltage divider unit 251 and the second voltage divider unit 252 are both used to connect to a first voltage signal V1. The second terminal of the first voltage divider unit 251 is connected to the address configuration pin ADDR of the third voltage divider unit 253 and one of the four second sub-modules 221, respectively. The second terminal of the second voltage divider unit 252 is connected to the first terminal of the fourth voltage divider unit 254 and the address configuration pin ADDR of the other three second sub-modules 221, respectively. The second terminals of the third voltage divider unit 253 and the fourth voltage divider unit 254 are connected to the equivalent ground terminal, respectively.

[0098] Among them, at least two of the first voltage divider unit 251, the second voltage divider unit 252, the third voltage divider unit 253 and the fourth voltage divider unit 254 have different voltage division parameters, so that after the first voltage signal V1 is divided, the corresponding voltage is configured to the second configuration pin via the address configuration pin ADDR.

[0099] The first voltage divider unit 251, the second voltage divider unit 252, the third voltage divider unit 253, and the fourth voltage divider unit 254 may include different or the same voltage divider devices. Exemplarily, they may include resistors, potentiometers, capacitors, inductors, etc., but are not limited thereto. The voltage dividing parameters in the embodiments of this application correspond to the types of voltage dividing devices included in the first voltage divider unit 251, the second voltage divider unit 252, the third voltage divider unit 253, and the fourth voltage divider unit 254. Exemplarily, the voltage dividing parameters may be resistors, capacitors, etc. Appendix Figure 8 The following example illustrates the voltage divider unit 251, the second voltage divider unit 252, the third voltage divider unit 253, and the fourth voltage divider unit 254, all of which include resistors. Correspondingly, the voltage divider parameters can be resistors.

[0100] In this embodiment, there are four second submodules 221. To prevent address conflicts among the I2C devices configured in the second submodules 221, the voltage of the address configuration pins (ADDR) of each second submodule 221 is configured using a first voltage divider unit 251, a second voltage divider unit 252, a third voltage divider unit 253, and a fourth voltage divider unit 254. The corresponding input voltage needs to be configured for the address configuration pins (ADDR) of each second submodule 221. Depending on the configuration requirements of each second submodule 221, the configuration voltages for different addresses may overlap. Therefore, at least two of the first voltage divider units 251, the second voltage divider unit 252, the third voltage divider unit 253, and the fourth voltage divider unit 254 have different voltage division parameters, although two of them may have the same voltage division parameters. For example, the voltage corresponding to the second configuration pin of one second submodule 221 may be 0V, while the voltages corresponding to the second configuration pins of the other three second submodules 221 may be 1.1V. This is not a limitation.

[0101] In this embodiment, the voltage configuration of the address configuration pins ADDR of each second submodule 221 is performed by the first voltage divider unit 251, the second voltage divider unit 252, the third voltage divider unit 253 and the fourth voltage divider unit 254, which allows for independent management of the four second submodules 221 and improves the configuration efficiency of the address configuration pins ADDR.

[0102] In some embodiments, the control unit is configured with a second slave I2C port; the type of the third configuration pin includes an I2C communication pin, and the third configuration pin is connected to the second slave I2C port via a 2C bus to transmit the third configuration signal output from the control unit to each signal splicing module.

[0103] In this embodiment, the third configuration signal is transmitted between the control unit and the signal splicing module via the I2C bus. The I2C bus only requires two lines, namely the serial data line and the serial clock line, which can simplify the circuit structure and reduce the complexity and cost of the display device.

[0104] Combined with appendix Figure 9 , attached Figure 9 This is shown as a third schematic block diagram of a display device according to an embodiment of the present application. In some embodiments, the display device provided in this application includes a first signal conversion module 210 configured with a power supply pin (not shown). The signal conversion circuit 200 may include a second voltage divider module 260.

[0105] The second voltage divider module 260 is connected to the power supply pin and is used to convert the input second voltage signal into a power supply signal of the target voltage and output the power supply signal to the power supply pin to supply power to the first signal conversion module 210.

[0106] In this embodiment, the second voltage divider module 260 is connected to the power supply pin to convert the incoming second voltage signal into a power supply signal that meets the target voltage required for the normal operation of the first signal conversion module 210. This power supply signal is then output to the power supply pin to supply power to the first signal conversion module 210, providing a foundation for its normal operation. For example, the second voltage divider module 260 can convert a 3.3V second voltage signal into a target voltage of 1.8V, ensuring the safe operation of the first signal conversion module 210.

[0107] In some embodiments, the display device provided in this application may include a liquid crystal display screen as its display platform.

[0108] In this embodiment, the display platform may include a liquid crystal display screen. The liquid crystal display screen receives a 10-bit second HDMI signal. The 10-bit second HDMI signal can provide 1024 levels of grayscale for the liquid crystal display screen, enabling the liquid crystal display screen to present the color changes of the target image more delicately and improve the display performance of the display device.

[0109] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0110] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. Therefore, the scope of protection of this patent application should be determined by the appended claims.

Claims

1. A display device, characterized in that, include: The main chip is used to output 16 channels of V-by-One signals carrying the target image; the number of bits of the 16 channels of V-by-One signals includes 10 bits. The signal conversion circuit includes a first signal conversion module, a second signal conversion module, and a signal splicing module; The first signal conversion module is connected to the main chip and is used to access the 16-channel V-by-One signal; The second signal conversion module is connected to the first signal conversion module and is used to receive 16 channels of LVDS differential signals; the 16 channels of LVDS differential signals are generated by the first signal conversion module by converting the 16 channels of V-by-One signals. The signal splicing module is connected to the second signal conversion module and is used to access multiple 4-channel first HDMI signals; the first HDMI signal has 8 bits; the 4-channel first HDMI signal is generated by the second signal conversion module by converting the 16-channel LVDS differential signal. The display platform, connected to the signal conversion circuit, is used to receive the second HDMI signal to display the target image; the second HDMI signal includes 10 bits. The second HDMI signal is generated by the signal splicing module by splicing multiple 4-channel first HDMI signals.

2. The display device according to claim 1, characterized in that, The first signal conversion module includes: The system comprises four first sub-modules, each equipped with a V-By-One signal input interface and an LVDS differential signal output interface. The V-By-One signal input interface is connected to the main chip to receive 16 channels of the V-by-One signal, and the LVDS differential signal output interface is connected to the second signal conversion module to output 16 channels of the LVDS differential signal to the second signal conversion module.

3. The display device according to claim 2, characterized in that, The second signal conversion module includes: The system comprises four second sub-modules, each equipped with an LVDS differential signal input interface and an HDMI signal output interface. The LVDS differential signal input interface of one second sub-module is connected to the LVDS differential signal output interface of one first sub-module, and the HDMI signal output interface of each second sub-module is connected to the signal splicing module for transmitting four channels of the first HDMI signal.

4. The display device according to claim 3, characterized in that, Each of the first submodules is configured with a first configuration pin; each of the second submodules is configured with a second configuration pin; the signal splicing module is configured with a third configuration pin; the signal conversion circuit further includes: The main control module is connected to the first configuration pin of each first sub-module, the second configuration pin of each second sub-module, and the third configuration pin of the signal splicing module, respectively, and is used to output corresponding configuration signals to each first configuration pin, second configuration pin, and third configuration pin; the configuration signals are used to configure the working state of each first sub-module, each second sub-module, and the signal splicing module.

5. The display device according to claim 4, characterized in that, The different configuration signals include a first configuration signal, a second configuration signal, and a third configuration signal; the main control module includes: The main control unit is connected to the first configuration pin of each of the first sub-modules and is used to output the first configuration signal to each of the first sub-modules. The control unit is connected to the second configuration pin of the signal splicing module and each of the second sub-modules, respectively, for outputting the third configuration signal to the signal splicing module and the second configuration signal to each of the second sub-modules.

6. The display device according to claim 5, characterized in that, The slave control unit is configured with a first slave I2C port; the second configuration pin includes an I2C communication pin, and the second configuration pin is connected to the first slave I2C port of the slave control unit through an I2C bus to transmit the second configuration signal output by the slave control unit to each of the second sub-modules.

7. The display device according to claim 6, characterized in that, Each of the second submodules is configured with an address configuration pin, which is connected to the second configuration pin; the signal conversion circuit further includes: The first voltage divider module includes a first voltage divider unit, a second voltage divider unit, a third voltage divider unit, and a fourth voltage divider unit. The first terminals of the first voltage divider unit and the second voltage divider unit are both used to receive a first voltage signal. The second terminal of the first voltage divider unit is connected to the address configuration pin of the third voltage divider unit and one of the four second sub-modules. The second terminal of the second voltage divider unit is connected to the first terminal of the fourth voltage divider unit and the address configuration pins of the other three second sub-modules. The second terminals of the third voltage divider unit and the fourth voltage divider unit are connected to an equivalent ground terminal. Among them, at least two of the first voltage divider unit, the second voltage divider unit, the third voltage divider unit and the fourth voltage divider unit have different voltage division parameters, so that after the first voltage signal is divided, the corresponding voltage is configured to the second configuration pin through the address configuration pin.

8. The display device according to claim 5, characterized in that, The slave control unit is configured with a second slave I2C port; the third configuration pin is of the type of I2C communication pin, and the third configuration pin is connected to the second slave I2C port through the 2C bus to transmit the third configuration signal output by the slave control unit to each of the signal splicing modules.

9. The display device according to claim 1, characterized in that, The first signal conversion module is equipped with a power supply pin; the signal conversion circuit further includes: The second voltage divider module is connected to the power supply pin and is used to convert the input second voltage signal into a power supply signal of the target voltage, and output the power supply signal to the power supply pin to supply power to the first signal conversion module.

10. The display device according to claim 1, characterized in that, The display platform includes a liquid crystal display screen.

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