silicon carbide power devices

Abstract

This invention provides a silicon carbide power device, comprising: a substrate; a silicon carbide epitaxial layer disposed on the surface of the substrate; a gate structure disposed on the surface of the silicon carbide epitaxial layer or within the silicon carbide epitaxial layer; a JFET region disposed on the silicon carbide epitaxial layer; and a high-resistivity region disposed in the JFET region and located below the gate structure, wherein the high-resistivity region is formed by doping with a deep-level dopant that matches silicon carbide. This application can improve the performance of silicon carbide power devices.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a silicon carbide power device. Background Technology

[0002] SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) power devices are widely used in new energy vehicles, rail transportation, and photovoltaic industries due to their advantages such as high voltage and high temperature resistance, high frequency, low power loss, and high switching speed.

[0003] Silicon carbide power devices employing Planar MOS (Planar MOS) structures are widely used in applications requiring high-performance power switching, such as power management, electric vehicle control, and frequency converters, due to their advantages of lower on-resistance, higher voltage withstand capability, and higher switching speed. However, with the further development of electronic control technology in new energy vehicles, higher requirements are being placed on silicon carbide power devices in terms of cost reduction and improved voltage withstand capability. Utility Model Content

[0004] To solve the above-mentioned technical problems, this utility model provides a silicon carbide power device, comprising:

[0005] Substrate;

[0006] A silicon carbide epitaxial layer is disposed on the surface of the substrate;

[0007] A gate structure is disposed on the surface of the silicon carbide epitaxial layer or in the silicon carbide epitaxial layer;

[0008] The JFET region is located in the silicon carbide epitaxial layer;

[0009] A high-resistivity region is located in the JFET region and is in contact with the gate structure. The high-resistivity region is formed by doping with a deep-level dopant that matches silicon carbide.

[0010] Optionally, the deep-level dopant includes any one or more of vanadium ions, iron ions, oxygen ions, and magnesium ions.

[0011] Optionally, the doping concentration of the high-resistivity region is 10. 16 ~10 20 / cm 3 .

[0012] Optionally, the silicon carbide power device is a planar gate power device, which includes a P-type body region, a source region, and a planar gate structure. The P-type body region is disposed in the silicon carbide epitaxial layer, the source region is disposed in the P-type body region, the JFET region is located between two adjacent P-type body regions, the planar gate structure is located on the JFET region, the high-resistivity region is located in the JFET region under the planar gate structure, and the high-resistivity region has a first preset distance from the P-type body regions on both sides.

[0013] Optionally, the width of the high-resistivity region is less than or equal to 80% of the width of the JFET region.

[0014] Optionally, the thickness of the high-resistivity region is 0.5 to 2 times the thickness of the P-type body region.

[0015] Optionally, the planar gate power device is a planar IGBT device or a planar MOS device.

[0016] Optionally, the silicon carbide power device is a trench gate power device, which includes a P-type body region, a source region, and a trench gate structure. The P-type body region is disposed in the silicon carbide epitaxial layer, and the trench gate structure penetrates the P-type body region. The source region is disposed in the P-type body region and contacts the outer wall of the trench gate structure. The JFET region is the area in the silicon carbide epitaxial layer surrounding the portion of the trench gate structure that extends out of the P-type body region. The high-resistivity region is located in the JFET region at the bottom of the trench gate structure and around it, and the high-resistivity region has a second preset distance from the P-type body region.

[0017] Optionally, the width of the high-resistivity region is 0.1 to 2 times the width of the trench gate.

[0018] Optionally, the trench gate power device is a trench IGBT device or a trench MOS device.

[0019] In summary, this utility model provides a silicon carbide power device, which includes a substrate, a silicon carbide epitaxial layer, a gate structure, a JFET region, and a high-resistivity region. The silicon carbide epitaxial layer is disposed on the surface of the substrate. The gate structure is disposed on the surface of the silicon carbide epitaxial layer or within the silicon carbide epitaxial layer. The JFET region is disposed within the silicon carbide epitaxial layer. The high-resistivity region is disposed within the JFET region and located below the gate structure, and is formed by doping with a deep-level dopant that matches silicon carbide. In this application, the high-resistivity region, located within the JFET region below the gate structure, has a higher resistance than the JFET region. This high-resistivity region can push the electric field on the lower surface of the gate structure towards the N-drift region, effectively suppressing excessively high electric field strength on the lower surface of the gate structure, thereby improving the reliability of the silicon carbide power device. More importantly, this high-resistivity region is formed by doping with corresponding deep-level dopants. The deep-level dopants in this high-resistivity region can act as recombination centers (or traps) for non-radiative recombination carriers. Its high-resistivity performance is intrinsic, rather than dependent on external factors to form a PN structure. Therefore, this high-resistivity region can exert a small influence on the surrounding region (such as the JFET region or the N-drift layer). That is, the high-resistivity region has a small impact on the current path around the high-resistivity region (it does not crowd out the current path of the JFET region and does not affect the current conduction capability). Thus, while improving the reliability of power devices (including improving the breakdown voltage), the on-resistance of power devices can be minimized or avoided. Attached Figure Description

[0020] Those skilled in the art will understand that the accompanying drawings are provided to better understand the present invention and do not constitute any limitation on the scope of the present invention.

[0021] Figure 1 This is a cross-sectional schematic diagram of a planar MOS device provided in an embodiment of this application;

[0022] Figure 2 This is a cross-sectional schematic diagram of a planar gate IGBT device provided in an embodiment of this application;

[0023] Figure 3 This is a cross-sectional schematic diagram of a trench MOS device provided in an embodiment of this application;

[0024] Figure 4 This is a cross-sectional schematic diagram of a trench gate IGBT device provided in an embodiment of this application;

[0025] Figure 5 A flowchart illustrating the fabrication method of the silicon carbide power device provided in the embodiments of this application;

[0026] Figure 6A This is a schematic diagram of the formation of a silicon carbide epitaxial layer provided in an embodiment of this application;

[0027] Figure 6B This is a schematic diagram of the formation of the P-type body region and the JFET region provided in an embodiment of this application;

[0028] Figure 6C This is a schematic diagram of the formation of the N+ source region provided in an embodiment of this application;

[0029] Figure 6D A schematic diagram illustrating the formation of a second patterned mask provided in an embodiment of this application;

[0030] Figure 6E This is a schematic diagram of the formation of a high-resistivity region provided in an embodiment of this application;

[0031] Figure 6F This is a schematic diagram of the formation of the P+ contact area provided in an embodiment of this application;

[0032] Figure 6G This is a schematic diagram of the formation of the gate structure provided in an embodiment of this application;

[0033] Figure 6H This is a schematic diagram of the formation of the N+ drain layer and the back metal layer provided in an embodiment of this application.

[0034] In the attached figures: 10-substrate; 11-buffer layer; 12-silicon carbide epitaxial layer; 13-first patterned mask; 14-ion implantation protective layer; 15-P-type body region; 15a-channel; 16-N-drift region; 21-JFET region; 22-sidewall structure; 23-N+ source region; 24-second patterned mask; 25-high resistivity region; 26-P+ body contact region; 27-planar gate structure; 27a-gate dielectric layer; 27b-gate conductive layer; 28-N+ drain region; 29-back metal layer; 30-trench; 31-trench gate structure; 31a-gate dielectric layer; 31b-gate conductive layer; 32-P+ collector region; 33-back metal layer. Detailed Implementation

[0035] To make the objectives, advantages, and features of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the objectives of the embodiments of this utility model. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may emphasize different aspects and sometimes use different scales.

[0036] It should be understood that when an element or layer is referred to as "on" or "connected to" other elements or layers, it may be directly on or connected to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on" or "directly connected to" other elements or layers, there are no intervening elements or layers. Although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this utility model, the first element, component, area, layer, or part discussed below may be referred to as a second element, component, area, layer, or part. Spatial relation terms such as "below," "under," "below," "above," "on top," "above," etc., may be used herein for convenience of description to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relational terms are intended to also include different orientations of the devices in use and operation. For example, if the devices in the figures are flipped, then elements or features described as “below,” “under,” or “below” will be oriented “on” other elements or features. Devices may be oriented additionally (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly. The terminology used herein is intended only to describe particular embodiments and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “comprising” is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the terms “and / or” include any and all combinations of the associated listed items.

[0037] Figure 1 This is a cross-sectional schematic diagram of a planar MOS device provided in an embodiment of this application.

[0038] like Figure 1As shown, the silicon carbide power device provided in this application embodiment can be a planar MOS device, which is disposed on a substrate 10. The substrate 10 includes a front side and a back side. The planar MOS device provided in this application includes, along the direction away from the back side of the substrate 10, a back metal layer 29, an N+ drain region 28, an N- drift layer 16, a P-type body region 15, a JFET region 21, a high-resistivity region 25, a planar gate structure 27, a front metal layer, and a passivation layer, which are sequentially disposed. Among them, the back metal layer 29 is located on the back side of the substrate 10. The substrate 10 can be made of semiconductor substrate materials such as silicon carbide and silicon. Moreover, the substrate 10 can also be a thinned semiconductor substrate. The N+ drain region 28 is located within the thinned substrate.

[0039] In some examples, please continue to refer to Figure 1 A buffer layer 11 and a silicon carbide epitaxial layer 12 are sequentially disposed on the front side of the substrate 10. The aforementioned N-drift layer 16, P-type body region 15, JFET region 21, and high-resistivity region 25 are all disposed in the silicon carbide epitaxial layer 12. The planar gate structure 27, the front metal layer, and the passivation layer are all located on the surface of the silicon carbide epitaxial layer 12. The doping type and concentration of the silicon carbide epitaxial layer 12 are the same as those of the N-drift layer 16. In other words, the N-drift layer 16 can be the portion of the silicon carbide epitaxial layer 12 closest to the substrate 10, or the N-drift layer 16 can be the portion of the silicon carbide epitaxial layer 12 excluding the P-type body region 15 and the JFET region 21. At least two P-type body regions 15 are spaced apart on the side of the silicon carbide epitaxial layer 12 away from the substrate 10. The silicon carbide epitaxial layer 12 (or N-drift layer 16) between adjacent P-type body regions 15 constitutes the JFET region 21. Each P-type body region 15 has an N+ source region 23 and a P+ body contact region 26. The N+ source region 23 is in contact with the P+ body contact region 26. The N+ source region 23 is located close to the JFET region 21, while the P+ body contact region 26 is located away from the JFET region 21. The portion of the P-type body region 15 between the N+ source region 23 and the JFET region 21 can be a channel 15a. The planar gate structure 27 covers the surface of the silicon carbide epitaxial layer 12 of the JFET region 21 and the channels 15a on both sides, and can extend to cover part of the surface of the silicon carbide epitaxial layer 12 of the N+ source region 23. The planar gate structure 27 may include a gate dielectric layer 27a and a gate conductive layer 27b formed sequentially. The gate dielectric layer 27a covers the surface of the silicon carbide epitaxial layer 12, and the gate conductive layer 27b covers the surface of the gate dielectric layer 27a.

[0040] Please continue to refer to Figure 1 The high-resistivity region 25 is disposed in the JFET region 21 and contacts the bottom of the planar gate structure 27, and is spaced apart from the P-type body regions 15 on both sides of the JFET region 21. In other words, the top of the high-resistivity region 25 contacts the gate dielectric layer 27a. It is understood that in some other embodiments, it is also feasible for the top of the high-resistivity region 25 not to contact the bottom of the gate dielectric layer 27a.

[0041] The high-resistivity region 25 has a first preset spacing distance D1 between its two ends and the two sides of the channel 15a along the channel extension direction. This first preset spacing distance D1 can be determined by the power device's requirements for on-resistance and breakdown voltage. For example, the smaller the required on-resistance, the larger the first preset spacing distance can be; the higher the required breakdown voltage, the smaller the first preset spacing distance can be. In some examples, the first preset spacing distance can be greater than or equal to 10% of the width of the JFET region 21 (i.e., the width of the high-resistivity region 25 is less than or equal to 80% of the width of the JFET region 21), thus balancing on-resistance and breakdown voltage. Furthermore, the high-resistivity region 25 can extend into the N-drift layer 16 beneath the JFET region 21, in addition to being located within the JFET region 21. Therefore, the thickness of the high-resistivity region 25 is between 0.5 and 2 times the thickness of the body region (i.e., the thickness of the JFET region 21). The thickness of the high-resistivity region 25 can be set according to the doping concentration of the high-resistivity region 25, combined with the power device's on-resistance and breakdown voltage. In some examples, the doping concentration of the high-resistivity region 25 can be 10. 16 ~10 20 / cm 3 .

[0042] It is important to note that the aforementioned high-resistivity region is formed by doping with a deep-level dopant that matches silicon carbide. This deep-level dopant can include any one or more of vanadium ions, iron ions, oxygen ions, and magnesium ions. In one aspect, this high-resistivity region, located within the JFET region under the gate structure, has a higher resistance than the JFET region. This can push the electric field from the lower surface (bottom) of the gate structure towards the N-drift region, effectively preventing excessively high electric field strength on the lower surface of the gate structure, thereby improving the reliability of silicon carbide power devices. On the other hand, the high-resistivity region is formed by doping with corresponding deep-level dopants. The deep-level dopants in the high-resistivity region can act as recombination centers (or traps) for non-radiative recombination carriers. Its high-resistivity performance is intrinsic and does not depend on external factors to form a PN structure. Therefore, the high-resistivity region can exert a small influence on the surrounding region (such as the JFET region or the N-drift layer). That is, the high-resistivity region has a small influence on the current path around the high-resistivity region (it does not crowd out the current path of the JFET region and does not affect the current conduction capability). Thus, while improving the reliability of the power device (including improving the withstand voltage), the on-resistance of the power device can be minimized or avoided.

[0043] In a counterexample (i.e., a contrary example) to the embodiments of this application, a P-type doped region is formed in the JFET region under the gate structure. This P-type doped region forms a PN structure (high resistance) with the JFET region to improve the breakdown voltage. However, the breakdown voltage provided by the PN structure is not stable and is affected by various factors such as bias voltage, temperature, and switching frequency, making it prone to failure. Moreover, after implantation, the aforementioned P-type doped region will also form hole diffusion (i.e., the P-type doped region forms a PN structure with the JFET region), which squeezes the current path of the JFET region and seriously affects the on-resistance of the power device. Alternatively, to reduce the impact on on-resistance (ensuring current conduction capability), the width of the JFET region can be increased, which requires increasing the pitch, thus increasing the chip area and correspondingly increasing the cost.

[0044] Figure 2 This is a cross-sectional schematic diagram of a planar gate IGBT device provided in an embodiment of this application.

[0045] like Figure 2 As shown, the silicon carbide power device provided in this application embodiment can be a planar gate IGBT (planar IGBT) device, which is disposed on a substrate 10. The substrate 10 includes a front side and a back side facing each other. The planar gate IGBT device provided in this application includes, along the direction away from the back side of the substrate 10, a back metal layer 33, a P+ collector region 32, an N+ field cutoff layer (not shown), an N- drift region 16, a P-type body region 15, a JFET region 21, a high-resistivity region 25, a planar gate structure 27, a front metal layer, and a passivation layer, which are sequentially disposed. Among them, the back metal layer 33 is located on the back side of the substrate 10. The substrate 10 can be made of semiconductor substrate materials such as silicon carbide and silicon. Moreover, the substrate 10 can also be a thinned semiconductor substrate. The P+ collector region 32 and the N+ field cutoff layer can be located within the thinned substrate.

[0046] In some examples, please continue to refer to Figure 1A silicon carbide epitaxial layer 12 may be provided on the front side of the substrate 10. The aforementioned N+ field cutoff layer, N- drift region 16, P-type body region 15, JFET region 21, and high-resistivity region 25 are all disposed in the silicon carbide epitaxial layer 12. The planar gate structure 27, the front metal layer, and the passivation layer are all located on the surface of the silicon carbide epitaxial layer 12. At least two P-type body regions 15 are spaced apart on the side of the silicon carbide epitaxial layer 12 away from the substrate 10. The silicon carbide epitaxial layer 12 (or N-drift layer 16) between adjacent P-type body regions 15 is the JFET region 21. Each P-type body region 15 has an N+ source region 23 (or emitter region) and a P+ body contact region 26. The N+ source region 23 is in contact with the P+ body contact region 26. The N+ source region 23 is located close to the JFET region 21, while the P+ body contact region 26 is located away from the JFET region 21. The portion of the P-type body region 15 between the N+ source region 23 and the JFET region 21 can be a channel 15a. The planar gate structure 27 covers the surface of the silicon carbide epitaxial layer 12 of the JFET region 21 and the channels 15a on both sides, and can extend to cover part of the surface of the silicon carbide epitaxial layer 12 of the N+ source region 23. The planar gate structure 27 may include a gate dielectric layer 27a and a gate conductive layer 27b formed sequentially. The gate dielectric layer 27a covers the surface of the silicon carbide epitaxial layer 12, and the gate conductive layer 27b covers the surface of the gate dielectric layer 27a.

[0047] Please continue to refer to Figure 2 The high-resistivity region 25 is disposed in the JFET region 21 and contacts the bottom of the planar gate structure 27, and is spaced apart from the P-type body regions 15 on both sides of the JFET region 21. In other words, the top of the high-resistivity region 25 contacts the gate dielectric layer 27a. It is understood that in some other embodiments, it is also feasible for the top of the high-resistivity region 25 not to contact the bottom of the gate dielectric layer 27a.

[0048] The high-resistance region 25 has a first preset spacing distance D1 between its two ends and the two sides of the channel 15a along the channel extension direction. This first preset spacing distance can be determined by the power device's requirements for on-resistance and breakdown voltage. For example, the smaller the required on-resistance, the larger the first preset spacing distance can be; the higher the required breakdown voltage, the smaller the first preset spacing distance can be. In some examples, the first preset spacing distance can be greater than or equal to 10% of the width of the JFET region 21 (i.e., the width of the high-resistance region 25 is less than or equal to 80% of the width of the JFET region 21), thus balancing on-resistance and breakdown voltage. In addition, the high-resistivity region 25 can be located not only within the JFET region 21 but also extend into the N-drift layer 16 beneath the JFET region 21. Therefore, the thickness of the high-resistivity region 25 is between 0.5 and 2 times the thickness of the P-type body region 15 (i.e., the thickness of the JFET region 21). The thickness of the high-resistivity region 25 can be set based on its doping concentration, combined with the on-resistance and breakdown voltage of the power device. In some examples, the doping concentration of the high-resistivity region 25 can be 10⁻⁶. 16~10 20 / cm 3 .

[0049] It is important to note that the aforementioned high-resistivity region is formed by doping with a deep-level dopant that matches silicon carbide. This deep-level dopant can include any one or more of vanadium ions, iron ions, oxygen ions, and magnesium ions. In one aspect, this high-resistivity region, located within the JFET region under the gate structure, has a higher resistance than the JFET region. This can push the electric field from the lower surface (bottom) of the gate structure towards the N-drift region, effectively preventing excessively high electric field strength on the lower surface of the gate structure, thereby improving the reliability of silicon carbide power devices. On the other hand, the high-resistivity region is formed by doping with corresponding deep-level dopants. The deep-level dopants in the high-resistivity region can act as recombination centers (or traps) for non-radiative recombination carriers. Its high-resistivity performance is intrinsic and does not depend on external factors to form a PN structure. Therefore, the high-resistivity region can exert a small influence on the surrounding region (such as the JFET region or the N-drift layer). That is, the high-resistivity region has a small influence on the current path around the high-resistivity region (it does not crowd out the current path of the JFET region and does not affect the current conduction capability). Thus, while improving the reliability of the power device (including improving the withstand voltage), the on-resistance of the power device can be minimized or avoided.

[0050] Figure 3 This is a cross-sectional schematic diagram of a trench MOS device provided in an embodiment of this application.

[0051] like Figure 3 As shown, the silicon carbide power device provided in this application embodiment can be a trench MOS device, which is disposed on a substrate 10. The substrate 10 includes a front side and a back side. The trench 30 gate trench MOS device provided in this application includes, along the direction away from the back side of the substrate 10, a back metal layer 29, an N+ drain region 28, an N- drift layer 16, a P-type body region 15, a JFET region 21, a high-resistivity region 25, a trench gate structure 31, a front metal layer, and a passivation layer, which are sequentially disposed. Among them, the back metal layer 29 is located on the back side of the substrate 10. The substrate 10 can be made of semiconductor substrate materials such as silicon carbide and silicon. Moreover, the substrate 10 can also be a thinned semiconductor substrate. The N+ drain region 28 is located in the thinned substrate.

[0052] In some examples, please continue to refer to Figure 3A buffer layer 11 and a silicon carbide epitaxial layer 12 may be sequentially disposed on the front side of the substrate 10. The aforementioned N-drift layer 16, P-type body region 15, JFET region 21, high-resistivity region 25, and trench gate structure 31 are all disposed in the silicon carbide epitaxial layer 12. The front metal layer and passivation layer are both located on the surface of the silicon carbide epitaxial layer 12. The doping type and doping concentration of the silicon carbide epitaxial layer 12 are the same as those of the N-drift layer 16. In other words, the N-drift layer 16 may be the portion of the silicon carbide epitaxial layer 12 closest to the substrate 10, or the N-drift layer 16 may be the portion of the silicon carbide epitaxial layer 12 excluding the P-type body region 15, the JFET region 21, and the trench gate structure 31. A trench 30 is formed in the silicon carbide epitaxial layer 12 on the side away from the substrate 10. A trench gate structure 31 is disposed in the trench 30. The trench gate structure 31 includes a gate dielectric layer 31a and a gate conductive layer 31b formed sequentially. The gate dielectric layer 31a covers the inner wall of the trench 30, and the gate conductive layer 31b covers the surface of the gate dielectric layer 31a and fills the trench 30. A P-type body region 15 is located in the silicon carbide epitaxial layer 12 and is disposed on both sides of the trench gate structure 31. The P-type body region 15 is in contact with the outer wall of the trench 30, and the thickness of the P-type body region 15 is less than the depth of the trench 30. In other words, the trench gate structure 31 extends vertically through the surface of the silicon carbide epitaxial layer 12 through the P-type body region 15 and into the N-drift layer 16. Each P-type body region 15 has an N+ source region 23 and a P+ body contact region 26. The N+ source region 23 is in contact with the P+ body contact region 26, and the N+ source region 23 is in contact with the outer wall of the trench 30. The P+ body contact region 26 is located away from the trench 30 and extends into the P-type body region 15 and connects with the P-type body region 15. The portion of the P-type body region 15 extending downward from the N+ source region 23 and along the outer wall of the trench 30 can be a channel 15a, and the portion of the N-drift layer 16 surrounding the outer wall of the trench 30 can be a JFET region 21.

[0053] The high-resistivity region 25 is located below the P-type body region 15, within the JFET region 21 at the bottom of the trench 30, and contacts the bottom (bottom wall) or bottom sidewall of the trench 30. The top of the high-resistivity region 25 may have a second predetermined spacing distance D2 with the bottom of the P-type body region 15. In other words, the high-resistivity region 25 covers the portion of the trench 30 extending from the P-type body region 15 (i.e., a portion of the gate dielectric layer 31a). In some examples, please refer to... Figure 3The high-resistivity region 25 is located at the bottom of the trench 30, i.e., the second preset spacing distance is the length of the trench 30 extending beyond the P-type body region 15. The center of the high-resistivity region 25 is aligned or substantially aligned with the center of the trench 30. The width of the high-resistivity region 25 is less than or equal to the width of the trench 30 (i.e., the high-resistivity region 25 does not cover the bottom sidewall of the trench 30). The width of the high-resistivity region 25 can be, for example, 0.5 to 1 times the width of the trench 30. In other examples, the width of the high-resistivity region 25 is greater than the width of the trench 30. The width of the high-resistivity region 25 can be, for example, 1 to 1.2 times the width of the trench 30, and it also extends towards the P-type body region 15 and covers part of the bottom sidewall of the trench 30. The second preset spacing distance can be, for example, 0.5 to 1 times the length of the trench 30 extending beyond the P-type body region 15. The thickness of the high-resistivity region 25 can be set according to its doping concentration, combined with the on-resistance and breakdown voltage of the power device. In some examples, the doping concentration of the high-resistivity region 25 can be 10. 16 ~10 20 / cm 3 Furthermore, in some other embodiments, it is also possible for the top of the high-resistivity region 25 to not contact the outer wall of the gate dielectric layer 31a (i.e., the outside of the trench 30).

[0054] It is important to note that the aforementioned high-resistivity region is formed by doping with a deep-level dopant that matches silicon carbide. This deep-level dopant can include any one or more of vanadium ions, iron ions, oxygen ions, and magnesium ions. In one aspect, this high-resistivity region, located within the JFET region under the gate structure, has a higher resistance than the JFET region. This can push the electric field from the lower surface (bottom) of the gate structure towards the N-drift region, effectively preventing excessively high electric field strength on the lower surface of the gate structure, thereby improving the reliability of silicon carbide power devices. On the other hand, the high-resistivity region is formed by doping with corresponding deep-level dopants. The deep-level dopants in the high-resistivity region can act as recombination centers (or traps) for non-radiative recombination carriers. Its high-resistivity performance is intrinsic and does not depend on external factors to form a PN structure. Therefore, the high-resistivity region can exert a small influence on the surrounding region (such as the JFET region or the N-drift layer). That is, the high-resistivity region has a small influence on the current path around the high-resistivity region (it does not crowd out the current path of the JFET region and does not affect the current conduction capability). Thus, while improving the reliability of the power device (including improving the withstand voltage), the on-resistance of the power device can be minimized or avoided.

[0055] Figure 4 This is a cross-sectional schematic diagram of a trench gate IGBT device provided in an embodiment of this application.

[0056] like Figure 4As shown, the silicon carbide power device provided in this application embodiment can be a trench gate IGBT device, which is disposed on a substrate 10. The substrate 10 includes a front side and a back side. The trench gate IGBT device provided in this application includes, along the direction away from the back side of the substrate 10, a back metal layer 33, a P+ collector region 32, an N+ field cutoff layer (not shown), an N- drift region 16, a P-type body region 15, a JFET region 21, a high-resistivity region 25, a trench gate structure 31, a front metal layer, and a passivation layer, which are sequentially disposed. Among them, the collector metal layer is located on the back side of the substrate 10. The substrate 10 can be made of semiconductor substrate materials such as silicon carbide and silicon. Moreover, the substrate 10 can also be a thinned semiconductor substrate. The P+ collector region 32 and the N+ field cutoff layer can be located within the thinned substrate.

[0057] In some examples, please continue to refer to Figure 4 A buffer layer 11 and a silicon carbide epitaxial layer 12 may be sequentially disposed on the front side of the substrate 10. The aforementioned N-drift layer 16, P-type body region 15, JFET region 21, high-resistivity region 25, and trench gate structure 31 are all disposed in the silicon carbide epitaxial layer 12. The front metal layer and passivation layer are both located on the surface of the silicon carbide epitaxial layer 12. The doping type and doping concentration of the silicon carbide epitaxial layer 12 are the same as those of the N-drift layer 16. In other words, the N-drift layer 16 may be the portion of the silicon carbide epitaxial layer 12 closest to the substrate 10, or the N-drift layer 16 may be the portion of the silicon carbide epitaxial layer 12 excluding the P-type body region 15, the JFET region 21, and the trench gate structure 31. A trench 30 is formed in the silicon carbide epitaxial layer 12 on the side away from the substrate 10. A trench gate structure 31 is disposed in the trench 30. The trench gate structure 31 includes a gate dielectric layer 31a and a gate conductive layer 31b formed sequentially. The gate dielectric layer 31a covers the inner wall of the trench 30, and the gate conductive layer 31b covers the surface of the gate dielectric layer 31a and fills the trench 30. A P-type body region 15 is located on the surface of the silicon carbide epitaxial layer 12 and is disposed on both sides of the trench gate structure 31. The P-type body region 15 is in contact with the outer wall of the trench 30, and the thickness of the P-type body region 15 is less than the depth of the trench 30. In other words, the trench gate structure 31 extends vertically through the surface of the silicon carbide epitaxial layer 12 through the P-type body region 15 and into the N-drift layer 16. Each P-type body region 15 has an N+ source region 23 and a P+ body contact region 26. The N+ source region 23 is in contact with the P+ body contact region 26, and the N+ source region 23 is in contact with the outer wall of the trench 30. The P+ body contact region 26 is located away from the trench 30 and extends into the P-type body region 15 and connects with the P-type body region 15. The portion of the P-type body region 15 extending downward from the N+ source region 23 and along the outer wall of the trench 30 can be a channel 15a, and the portion of the N-drift layer 16 surrounding the outer wall of the trench 30 can be a JFET region 21.

[0058] The high-resistivity region 25 is located below the P-type body region 15, within the JFET region 21 at the bottom of the trench 30, and contacts the bottom (bottom wall) or bottom sidewall of the trench 30. The top of the high-resistivity region 25 may have a second predetermined spacing distance D2 with the bottom of the P-type body region 15. In other words, the high-resistivity region 25 covers the portion of the trench 30 extending from the P-type body region 15 (i.e., a portion of the gate dielectric layer 31a). In some examples, please refer to... Figure 3 The high-resistivity region 25 is located at the bottom of the trench 30, i.e., the second preset spacing distance is the length of the trench 30 extending beyond the P-type body region 15. The center of the high-resistivity region 25 is aligned or substantially aligned with the center of the trench 30. The width of the high-resistivity region 25 is less than or equal to the width of the trench 30 (i.e., the high-resistivity region 25 does not cover the bottom sidewall of the trench 30). The width of the high-resistivity region 25 can be, for example, 0.5 to 1 times the width of the trench 30. In other examples, the width of the high-resistivity region 25 is greater than or less than the width of the trench 30. The width of the high-resistivity region 25 can be, for example, 0.1 to 2 times the width of the trench 30, and it also extends towards the P-type body region 15 and covers part of the bottom sidewall of the trench 30. The second preset spacing distance can be, for example, 0.5 to 1 times the length of the trench 30 extending beyond the P-type body region 15. The thickness of the high-resistivity region 25 can be set according to its doping concentration, combined with the on-resistance and breakdown voltage of the power device. In some examples, the doping concentration of the high-resistivity region 25 can be 10. 16 ~10 20 / cm 3 Furthermore, in some other embodiments, it is also possible for the top of the high-resistivity region 25 to not contact the outer wall of the gate dielectric layer 31a (i.e., the outside of the trench 30).

[0059] It is important to note that the aforementioned high-resistivity region is formed by doping with a deep-level dopant that matches silicon carbide. This deep-level dopant can include any one or more of vanadium ions, iron ions, oxygen ions, and magnesium ions. In one aspect, this high-resistivity region, located within the JFET region under the gate structure, has a higher resistance than the JFET region. This can push the electric field from the lower surface (bottom) of the gate structure towards the N-drift region, effectively preventing excessively high electric field strength on the lower surface of the gate structure, thereby improving the reliability of silicon carbide power devices. On the other hand, the high-resistivity region is formed by doping with corresponding deep-level dopants. The deep-level dopants in the high-resistivity region can act as recombination centers (or traps) for non-radiative recombination carriers. Its high-resistivity performance is intrinsic and does not depend on external factors to form a PN structure. Therefore, the high-resistivity region can exert a small influence on the surrounding region (such as the JFET region or the N-drift layer). That is, the high-resistivity region has a small influence on the current path around the high-resistivity region (it does not crowd out the current path of the JFET region and does not affect the current conduction capability). Thus, while improving the reliability of the power device (including improving the withstand voltage), the on-resistance of the power device can be minimized or avoided.

[0060] This application provides a silicon carbide power device.

[0061] The silicon carbide power device provided in this application includes a substrate (e.g., Figures 1 to 4 The structure comprises a substrate 10), a silicon carbide epitaxial layer, a gate structure, a JFET region, and a high-resistivity region. The silicon carbide epitaxial layer is disposed on the surface of the substrate. The gate structure is disposed on the silicon carbide epitaxial layer (e.g., ...). Figure 1 , Figure 3 The planar gate structure 27 and the silicon carbide epitaxial layer 12 are disposed in or within the silicon carbide epitaxial layer (e.g., Figure 2 , Figure 4 The trench gate structure 31 and silicon carbide epitaxial layer 12 are in the JFET region (e.g., the trench gate structure 31 and the silicon carbide epitaxial layer 12). Figures 1 to 4 The JFET region 21 in the image is located on the silicon carbide epitaxial layer. (For example, ...) Figures 1 to 4 The high-resistivity region 25 is located in the JFET region and below the gate structure. The high-resistivity region is formed by doping with a deep-level dopant that matches silicon carbide.

[0062] In some embodiments, the deep-level dopant includes any one or more of vanadium ions, iron ions, oxygen ions, and magnesium ions.

[0063] In some embodiments, the doping concentration of the high-resistivity region is 10. 16 ~10 20 / cm 3 .

[0064] In some embodiments, the silicon carbide power device is a planar gate power device, and the high-resistivity region is located adjacent to the P-type body region (e.g., including...). Figure 1 , Figure 3 In the JFET region between the P-type body regions 15), the high-resistivity region and the P-type body regions on both sides have a first preset distance.

[0065] In some embodiments, the width of the high-resistivity region is less than or equal to 80% of the width of the JFET region.

[0066] In some embodiments, the thickness of the high-resistivity region is 0.5 to 2 times the thickness of the P-type body region.

[0067] In some embodiments, the planar gate power device is a planar IGBT device or a planar MOS device.

[0068] In some embodiments, the silicon carbide power device is a trench gate power device, the high-resistivity region is located below the P-type body region and has a second predetermined spacing distance from the P-type body region, and the high-resistivity region and the trench gate (e.g.) Figure 2 , Figure 4 The bottom phase of the trench gate structure 31) is in contact.

[0069] In some embodiments, the width of the high-resistivity region is 0.1 to 2 times the width of the trench gate.

[0070] In some embodiments, the trench gate power device is a trench IGBT device or a trench MOS device.

[0071] This application also provides a method for fabricating a silicon carbide power device.

[0072] Figure 5 A flowchart illustrating the fabrication method of the silicon carbide power device provided in the embodiments of this application.

[0073] like Figure 5 As shown, the method for fabricating a silicon carbide power device provided in this application includes:

[0074] S01: Provide a substrate, on which a silicon carbide epitaxial layer is formed;

[0075] S02: A JFET region is formed in the silicon carbide epitaxial layer;

[0076] S03: Forming a high-resistivity region and a gate structure, wherein the gate structure is disposed on the surface of the silicon carbide epitaxial layer or on the silicon carbide epitaxial layer, the high-resistivity region is disposed in the JFET region and located below the gate structure, and the high-resistivity region is formed by doping with a deep-level dopant that matches silicon carbide.

[0077] Figures 6A to 6H The diagram below shows the structural schematics corresponding to the steps of the fabrication method for the silicon carbide power device provided in this embodiment. The following will be combined with... Figures 6A to 6H The fabrication method of the silicon carbide power device is described in detail.

[0078] First, perform step S01, please refer to... Figure 6A A substrate 10 is provided, and a silicon carbide epitaxial layer 12 is formed on the surface of the substrate 10.

[0079] The substrate 10 can be made of any suitable substrate material for epitaxial growth of silicon carbide, such as silicon, sapphire, or silicon carbide. In some examples, a buffer layer 11 can be formed before forming the silicon carbide epitaxial layer 12 on the surface (front) of the substrate 10. This buffer layer 11 can be, for example, a lightly doped or intrinsic silicon carbide layer. In another example, when epitaxially forming the silicon carbide epitaxial layer 12, it can also be simultaneously doped in situ to a first type of conductivity, which can be the same as the doping type of the N-drift layer 16 (i.e., the first type of conductivity is N-type). Moreover, the concentration of in-situ doping during epitaxy can be the same as the doping concentration of the N-drift layer 16. In other words, an N-drift layer 16 is also formed in the silicon carbide epitaxial layer 12.

[0080] Next, step S02 is performed to form a JFET region 21 in the silicon carbide epitaxial layer 12.

[0081] Please refer to Figure 6B A first patterned mask 13 is formed on the silicon carbide epitaxial layer 12, and ion implantation of the second conductivity type is performed to form a P-type body region 15 in the silicon carbide epitaxial layer 12. The N-drift layer 16 (silicon carbide epitaxial layer 12) between adjacent P-type body regions 15 serves as the JFET region 21. In addition, before forming the first patterned mask 13, an ion implantation protection layer 14 may be formed to cover the surface of the silicon carbide epitaxial layer 12 to protect the surface of the silicon carbide epitaxial layer 12 during subsequent ion implantation.

[0082] Among them, the second type of conductivity ion implantation can be P-type conductivity ion implantation, and the material of the ion implantation protective layer 14 can be a composite film layer composed of any one or more of silicon, silicon nitride, silicon oxide, silicon oxynitride or aluminum nitride.

[0083] Please refer to Figure 6C A sidewall structure 22 is formed on the sidewall of the first patterned mask 13, and ion implantation of a first type of conductivity is performed to form an N+ source region 23 in the P-type body region 15. The first type of conductivity ion implantation can be N-type ion implantation, and the thickness of the N+ source region 23 (i.e., the ion implantation depth) can be less than the thickness of the P-type body region 15. The sidewall structure 22 covers the sidewall of the first patterned mask 13, and its width can be determined based on the length of the subsequent channel and the effect of double diffusion.

[0084] Next, step S03 is performed to form a high-resistivity region 25 and a gate structure. The gate structure is disposed on the surface of the silicon carbide epitaxial layer 12 or on the silicon carbide epitaxial layer 12. The high-resistivity region 25 is disposed in the JFET region 21 and is in contact with the gate structure. The high-resistivity region 25 is formed by doping with a deep-level dopant that matches silicon carbide.

[0085] Please refer to Figure 6DThe first patterned mask 13 and sidewall structure 22 are removed, and a second patterned mask 24 is formed on the silicon carbide epitaxial layer 12. The opening of the second patterned mask 24 is located directly above the JFET region 21, and the width of the opening of the second patterned mask 24 is smaller than the width of the JFET region 21. The second patterned mask 24 may be located on the ion implantation protective layer 14. The center of the opening of the second patterned mask 24 may be aligned or substantially aligned with the center of the JFET region 21. The edge of the opening of the second patterned mask 24 is at the same or substantially the same distance from its corresponding P-type body region 15. In other words, the edge of the opening of the second patterned mask 24 is at the same or substantially the same distance from its corresponding P-type body region 15. In some examples, the width of the opening of the second patterned mask 24 may be less than or equal to 80% of the width of the JFET region 21.

[0086] Please refer to Figure 6E Using a second patterned mask 24, ion implantation including deep-level dopants is performed to form a high-resistivity region 25 in the JFET region 21.

[0087] The deep-level dopant may include any one or more of vanadium ions, iron ions, oxygen ions, and magnesium ions. The doping concentration (i.e., doping dose) of the deep-level dopant is set according to the required on-resistance and breakdown voltage of the power device. In some examples, the doping dose of the deep-level dopant may be 10. 11 ~10 15 / cm 2 The doping concentration in the high-resistivity region 25 can be 10. 16 ~10 20 / cm 3 The depth of ion implantation can be set according to the doping concentration of the high-resistivity region 25, combined with the on-resistance and breakdown voltage of the power device. For example, the depth can be 0.5 to 2 times the thickness of the P-type body region 15 (i.e. the thickness of the JFET region 21). In other words, it is also feasible for the high-resistivity region 25 to extend into the N-drift layer 16 below the P-type body region 15.

[0088] In such Figure 6E In one example, the top of the high-resistivity region 25 is located on the surface of the JFET region 21, while in other examples, the top of the high-resistivity region 25 may also be located below the surface of the JFET region 21, meaning that the high-resistivity region 25 is not in contact with the subsequent gate structure.

[0089] Please refer to Figure 6F The second patterned mask 24 and the ion implantation protective layer 14 are removed, and a P+ contact region is formed in the N+ source region 23.

[0090] The steps for forming the P+ contact region may include, for example, forming a third patterned mask on the surface of the silicon carbide epitaxial layer 12, the opening of the third patterned mask exposing a portion of the surface of the P-type body region 15 and the surface of the N+ source region 23 away from the JFET region 21, performing heavy doping of the P-type conductivity type to connect the P-type body region 15 and the N+ source region 23 in the formed P+ contact region. Alternatively, a current spreading layer (not shown), a protective layer, or other junction ion doped regions may be formed on the surface of the silicon carbide epitaxial layer 12, and after removing the mask layer on the surface of the silicon carbide epitaxial layer 12, an annealing protective layer (e.g., a carbon layer) is formed to cover the surface of the silicon carbide epitaxial layer 12, and an annealing process is performed to activate the aforementioned doped ions at high temperature.

[0091] Please refer to Figure 6G A gate structure, a passivation layer, and a front metal layer are formed on the surface of the silicon carbide epitaxial layer 12.

[0092] The gate structure can be, for example, a planar gate structure 27, covering the JFET region 21 (including the high-resistivity layer therein) and the surface of the silicon carbide epitaxial layer 12 of the channels on both sides, and can extend to cover part of the surface of the silicon carbide epitaxial layer 12 of the N+ source region 23. It can include a gate dielectric layer 27a and a gate conductive layer 27b formed sequentially, with the gate dielectric layer 27a covering the surface of the silicon carbide epitaxial layer 12 and the gate conductive layer 27b covering the surface of the gate dielectric layer 27a. Next, a first passivation layer (not shown) is formed to cover the gate structure and the surface of the silicon carbide epitaxial layer 12, and a contact hole is formed in the first passivation layer to expose the area to be led out (the structure to be led out). Then, contact plugs, interconnects and pads are formed, which serve as the front metal layer. Next, a second passivation layer (not shown) can be formed to cover the first passivation layer and the interconnects, and expose the pads. The first passivation layer and the second passivation layer serve as passivation layers, and the material of the first passivation layer and the second passivation layer can include an oxide layer and / or a nitride layer.

[0093] Please refer to Figure 6H A thinning process is performed on the back side of the substrate 10, and an N+ drain region 28 and a back metal layer 33 are formed on the back side of the substrate 10.

[0094] In summary, this utility model provides a silicon carbide power device, which includes a substrate, a silicon carbide epitaxial layer, a gate structure, a JFET region, and a high-resistivity region. The silicon carbide epitaxial layer is disposed on the surface of the substrate. The gate structure is disposed on the surface of the silicon carbide epitaxial layer or within the silicon carbide epitaxial layer. The JFET region is disposed within the silicon carbide epitaxial layer. The high-resistivity region is disposed within the JFET region and located below the gate structure, and is formed by doping with a deep-level dopant that matches silicon carbide. In this application, the high-resistivity region, located within the JFET region below the gate structure, has a higher resistance than the JFET region. This high-resistivity region can push the electric field on the lower surface of the gate structure towards the N-drift region, effectively suppressing excessively high electric field strength on the lower surface of the gate structure, thereby improving the reliability of the silicon carbide power device. More importantly, this high-resistivity region is formed by doping with corresponding deep-level dopants. The deep-level dopants in this high-resistivity region can act as recombination centers (or traps) for non-radiative recombination carriers. Its high-resistivity performance is intrinsic, rather than dependent on external factors to form a PN structure. Therefore, this high-resistivity region can exert a small influence on the surrounding region (such as the JFET region or the N-drift layer). That is, the high-resistivity region has a small impact on the current path around the high-resistivity region (it does not crowd out the current path of the JFET region and does not affect the current conduction capability). Thus, while improving the reliability of power devices (including improving the breakdown voltage), the on-resistance of power devices can be minimized or avoided.

[0095] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A silicon carbide power device, characterized in that, include: Substrate; A silicon carbide epitaxial layer is disposed on the surface of the substrate; A gate structure is disposed on the surface of the silicon carbide epitaxial layer or in the silicon carbide epitaxial layer; The JFET region is located in the silicon carbide epitaxial layer; A high-resistivity region is disposed in the JFET region and located below the gate structure, the high-resistivity region being formed by doping with a deep-level dopant that matches silicon carbide.

2. The silicon carbide power device according to claim 1, characterized in that, The deep-level dopant includes any one or more of vanadium ions, iron ions, oxygen ions, and magnesium ions.

3. The silicon carbide power device according to claim 1, characterized in that, The doping concentration of the high resistance region is 10 16 ~ 10 20 / cm 3 .

4. The silicon carbide power device according to claim 1, characterized in that, The silicon carbide power device is a planar gate power device, which includes a P-type body region, a source region, and a planar gate structure. The P-type body region is disposed in the silicon carbide epitaxial layer, the source region is disposed in the P-type body region, the JFET region is located between two adjacent P-type body regions, the planar gate structure is located on the JFET region, and the high-resistivity region is located in the JFET region below the planar gate structure. The high-resistivity region has a first preset distance from the P-type body regions on both sides.

5. The silicon carbide power device according to claim 4, characterized in that, The width of the high-resistivity region is less than or equal to 80% of the width of the JFET region.

6. The silicon carbide power device according to claim 4, characterized in that, The thickness of the high-resistivity region is 0.5 to 2 times the thickness of the P-type body region.

7. The silicon carbide power device according to any one of claims 4 to 6, characterized in that, The planar gate power device is a planar IGBT device or a planar MOS device.

8. The silicon carbide power device according to claim 1, characterized in that, The silicon carbide power device is a trench gate power device, which includes a P-type body region, a source region, and a trench gate structure. The P-type body region is disposed in the silicon carbide epitaxial layer, and the trench gate structure penetrates the P-type body region. The source region is disposed in the P-type body region and contacts the outer wall of the trench gate structure. The JFET region is the area in the silicon carbide epitaxial layer surrounding the portion of the trench gate structure that extends out of the P-type body region. The high-resistivity region is located in the JFET region at the bottom of the trench gate structure and around it, and the high-resistivity region has a second preset spacing distance from the P-type body region.

9. The silicon carbide power device according to claim 8, characterized in that, The width of the high-resistivity region is 0.1 to 2 times the width of the trench gate.

10. The silicon carbide power device according to claim 8 or 9, characterized in that, The trench gate power device is a trench IGBT device or a trench MOS device.

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