Array p-island and multi-buffer layer SiC MOSFET with improved single particle resistance

Abstract

The application relates to an array P island and a multi-buffer layer SiC MOSFET with improved anti-single particle capability, and belongs to the microelectronic technology field. The application aims to solve the problems of weak anti-single particle burnout capability and high thermal failure risk of a silicon carbide device in a space radiation environment. The technical scheme comprises arranging four buffer layers with a doping gradient between a drain metal and a drift layer, and embedding an array structure composed of multiple left and right P islands and a middle P island in the buffer layers. The structure forms a super-junction-like electric field distribution on a single particle incident path. The technical effect of the application is that, through the synergistic effect of the array P island and the multi-buffer layer, the electric field peak value in the device is effectively flattened and homogenized, the carrier multiplication effect is inhibited, the transient power density and lattice temperature caused by single particle incidence are significantly reduced, and the single particle burnout threshold voltage of the device is greatly improved on the premise of basically maintaining the original electrical characteristics of the device.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology and relates to an array of P-islands and a multi-buffered SiC MOSFET that enhances single-particle rejection capability. Background Technology

[0002] Silicon carbide (SiC), a typical representative of third-generation wide-bandgap semiconductors, has become an ideal material for manufacturing high-voltage, high-frequency, and high-temperature power devices due to its excellent physical properties such as wide bandgap, high breakdown electric field, high thermal conductivity, and high saturated electron drift velocity. Among them, SiC MOSFETs (metal-oxide-semiconductor field-effect transistors) combine the intrinsic advantages of SiC materials with the efficient switching mechanism of MOS structure gate field control, and have demonstrated performance far exceeding that of traditional silicon-based devices in high-end power electronics fields such as new energy vehicles, photovoltaic inverters, and aerospace.

[0003] However, in the special space application environments such as aerospace, SiC MOSFETs must face the severe challenges of space radiation. Single event effects (SEE) generated after high-energy heavy ion incident on the device are one of the key causes of failure in aerospace electronic systems. Among various SEEs, single event burnout (SEB) is extremely destructive, typically occurring within nanoseconds after particle incident.

[0004] When high-energy particles penetrate a device, they generate a large number of electron-hole pairs along their incident path. Under a strong drain bias, these additional charge carriers induce a surge in local current within the drift region through a multiplication effect. Due to the significant electric field concentration effect at the trench structure or interface of traditional SiC MOSFETs, the high electric field and high current density on the incident path converge, generating extremely high transient power density. This causes the local temperature inside the device to rise sharply within a very short time, exceeding the melting point of SiC material (approximately 3000K), ultimately leading to thermal failure, breakdown, or even permanent physical damage to the device.

[0005] Currently, although hardening solutions employing multi-buffer layers to alleviate electric field concentration exist, their ability to control the peak electric field at the buffer layer's edge remains insufficient when dealing with single-particle incident particles of higher energy density. How to further optimize the electric field distribution within the device and limit power density accumulation along the single-particle incident path to improve the burn-out threshold voltage and operational reliability of SiC MOSFETs under extreme radiation environments is a pressing technical challenge in the power semiconductor field. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of existing silicon carbide (SiC) power devices in terms of insufficient resistance to single-event burn-out (SEB) under space radiation conditions, and to provide an arrayed P-island and multi-buffered layer SiC MOSFET with improved SEB resistance. This invention aims to suppress the electric field peak and current density convergence on the single-event incident path through precise control of the space charge region, thereby significantly improving the burn-out threshold voltage of the device and ensuring its operational reliability in extreme environments.

[0007] To achieve the above objectives, the present invention provides the following technical solution: An arrayed P-island and multi-buffered silicon carbide metal-oxide-semiconductor field-effect transistor (SiCMOSFET) with enhanced single-particle rejection capability includes: Drain metal 110; A substrate 109 and a buffer layer structure are stacked on the drain metal 110. The buffer layer structure includes buffer layer four 114, buffer layer three 113, buffer layer two 112 and buffer layer one 111 arranged sequentially from bottom to top. An N-drift layer 108 is disposed on the buffer layer structure; The P-body region 106 and the P+ shielding region 107 located at the bottom of the P-body region 106 are disposed within the N-drift layer 108. The N+ source region 104 and the P+ contact region 105 are disposed within the P-body region 106 and are adjacent to each other; A gate oxide layer 103 disposed above the P+ shielding region 107 and a gate 102 surrounded by the gate oxide layer 103; Source metal 101 covering the N+ source region 104, P+ contact region 105 and part of the gate 102; Multiple P islands, including left and right P islands 115 disposed inside the first buffer layer 111, the second buffer layer 112, and the third buffer layer 113, and a middle P island 116 disposed inside the first buffer layer 111 and located between the left and right P islands 115.

[0008] Furthermore, the thickness of buffer layer 111, buffer layer 2 112, buffer layer 3 113 and buffer layer 4 114 is 0.7 μm.

[0009] Furthermore, the N-type doping concentrations of the buffer layer 111, buffer layer 212, buffer layer 313, and buffer layer 414 are respectively as follows: , , , .

[0010] Furthermore, the buffer layer 114 has a groove with a width of 2.45 μm in the middle, which divides the buffer layer 114 into two separate parts, left and right.

[0011] Furthermore, the P-type doping concentration of the intermediate P-island 116 is... It has a thickness of 0.2 μm, and its lower surface is 0.4 μm away from the upper surface of the substrate 109.

[0012] Furthermore, the P-type doping concentration of the left and right P islands 115 is... The thickness is 0.2μm.

[0013] Furthermore, the distance between the lower surface of the left and right P islands 115 and the upper surface of the substrate 109 is 0.4 μm.

[0014] Furthermore, the distance between the inner sidewalls of the left and right P islands 115 and the sidewall of the middle P island 116 is 0.45 μm.

[0015] Furthermore, the plurality of P islands are arranged in an array in the vertical direction, and in the horizontal direction, they form a superjunction structure with the buffer layer structure, in which N-type pillars and P-type pillars are arranged alternately side by side.

[0016] Furthermore, the left and right P islands 115 have three layers, and the vertical spacing between them is 0.7 μm.

[0017] The beneficial effects of this invention are as follows: (1) The introduced array of P-islands and the N-type buffer layer form a structure similar to a "superjunction". This structure can flatten the strong electric field that was originally concentrated at the interface of the buffer layer and spread it evenly in all directions, so that the voltage is shared by the entire buffer layer region. Experiments show that under single-particle incident conditions, the maximum electric field intensity of the present invention is reduced by approximately The decrease was 16.7%.

[0018] (2) Because the peak electric field is suppressed, the transient power density on the single-particle incident path decreases significantly, which directly leads to a reduction in the highest lattice temperature inside the device. Under the same incident energy, the highest lattice temperature of the present invention is reduced by 20% (approximately 300K) compared to the device with only a buffer layer.

[0019] (3) While maintaining the basic static electrical characteristics of the device, the single-particle burn-off threshold voltage of the present invention is increased from 214V in the traditional structure to 666V, which is more than twice as high; it is also 16% higher than the single multi-layer buffer layer reinforcement structure.

[0020] (4) By arranging array P islands on the vertical path corresponding to the N+ source region, the sensitive area of ​​the device most easily burned out is specifically strengthened.

[0021] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0022] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the cross-sectional structure of the SiC MOSFET (PI-MB-MOSFET) that utilizes a superjunction to control the electric field to resist SEB, as described in this invention. Figure 2 This is a schematic diagram of the cross-sectional structure of a traditional trench-gate SiC MOSFET. Figure 3 A schematic diagram of the cross-sectional structure of a trench gate SiC MOSFET (MB-MOSFET) after the introduction of multiple buffer layers; Figure 4 A comparison of the electrical parameters of a traditional trench gate MOSFET with those of a reinforced MB-MOSFET and a PI-MB-MOSFET; Figure 5 The graph shows the leakage current of a traditional trench gate MOSFET as a function of single-particle incident time. Figure 6 The graph shows the leakage current of the hardened MB-MOSFET as a function of single-particle incident device time. Figure 7 The graph shows the leakage current of the PI-MB-MOSFET after the addition of the P-island as a function of single-particle incident time. Figure 8 The graph shows the variation of lattice temperature along the incident path of MB-MOSFET and PI-MB-MOSFET with device depth. Figure 9 The graph shows the variation of electric field intensity along the incident path of MB-MOSFET and PI-MB-MOSFET with device depth. Figure 10 This is a graph showing the electron density along the incident path of MB-MOSFET and PI-MB-MOSFET as a function of device depth.

[0023] Reference numerals: 101: Source metal, 102: Gate, 103: Gate oxide layer, 104: N+ source region, 105: P+ contact region, 106: P-body region, 107: P+ shielding region, 108: N- drift layer, 109: Substrate, 110: Drain metal, 111: Buffer layer one, 112: Buffer layer two, 113: Buffer layer three, 114: Buffer layer four, 115: Left and right P-islands, 116: Middle P-island. Detailed Implementation

[0024] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0025] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0026] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0027] I. Physical structure and parameter configuration of the device like Figure 1 As shown, this invention provides an arrayed P-island and multi-buffered silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) with enhanced single-particle rejection capability. Based on the traditional trench gate structure, this device strengthens the transition region between the drift layer and the substrate through a reinforced design, as detailed below: 1. Bottom layer and substrate structure: The bottom layer of the device is drain metal 110, and above the drain metal is a highly doped N+ substrate 109.

[0028] 2. Multi-Buffer Layer System: Four buffer layers are stacked on the N+ substrate 109. From bottom to top, they are buffer layer four 114, buffer layer three 113, buffer layer two 112 and buffer layer one 111.

[0029] Size and distribution: The thickness of each buffer layer is precisely set to 0.7μm.

[0030] Doping gradient: The N-type doping concentration of the four buffer layers decreases in a stepwise manner, with specific concentration values ​​as follows: (The text abruptly ends here, so the translation stops as well.) Buffer layer three is Buffer layer two is Buffer layer one is .

[0031] Trench design: A 2.45μm wide trench is provided in the middle of the buffer layer 4 114. This trench divides the buffer layer 4 into two separate parts, left and right, to coordinate the regulation of the bottom current path.

[0032] 3. Hardened area of ​​P-Island Array: Spatial arrangement: Three layers of left and right P-islands 115 are provided on the left and right sides of buffer layer 111 to buffer layer 313. The vertical spacing between them is determined by the thickness of the buffer layer and is 0.7μm. In addition, a central P-island 116 is provided in the center of buffer layer 111.

[0033] Key dimensions: The distance between the inner sidewalls of the left and right P-islands 115 and the sidewall of the middle P-island 116 is 0.45 μm. The thickness of both the left and right P-islands 115 and the middle P-island 116 is 0.2 μm, and the P-type doping concentration is [missing information]. .

[0034] Height positioning: The distance from the lower surface of all P islands to the upper surface of the N+ substrate 109 is consistent and set to 0.4 μm.

[0035] 4. Active region structure: Above the buffer layer 111 is an N-drift layer 108. The drift layer contains a P-body region 106 and a bottom P+ shielding region 107. The P-body region contains adjacent N+ source regions 104 and P+ contact regions 105. The gate structure includes a gate 102 and a gate oxide layer 103, with the topmost layer covered by source metal 101.

[0036] II. Electrical Properties and Single-Effect Burn-Up (SEB) Simulation Analysis This embodiment uses TCAD simulation software to simulate a traditional trench gate MOSFET ( Figure 2 MB-MOSFET with only a buffer layer Figure 3 ) and the PI-MB-MOSFET of the present invention ( Figure 1 A performance comparison was conducted.

[0037] 1. Comparison of static characteristics: such as Figure 4 As shown, in the comparison of transfer characteristics and breakdown voltage, the breakdown voltage of the conventional device is 993V. The MB-MOSFET's breakdown voltage drops to 967V due to the limited depletion region expansion caused by the introduction of a heavily doped buffer layer. However, the PI-MB-MOSFET of this invention utilizes the P-island's ability to modulate the electric field, thus raising the breakdown voltage back to 970V. Experimental results demonstrate that this invention, while introducing a ruggedized structure, essentially maintains the original static electrical performance of the device.

[0038] 2. Single-particle burn-off threshold voltage determination: A single particle was incident perpendicularly from the most sensitive N+ source region (10⁴), with a charge of 0.5 pC / μm. Traditional devices: such as Figure 5 As shown, the single-particle burn-off threshold voltage is only 214V without any reinforcement.

[0039] MB-MOSFET: such as Figure 6 As shown, after adding multiple buffer layers, the threshold voltage is increased to 575V.

[0040] The PI-MB-MOSFET of this invention: as follows Figure 7 As shown, after the N+ source region path is specifically enhanced by arraying P islands, the threshold voltage is increased to 666V, which is about 16% higher than that of MB-MOSFET and more than twice higher than that of traditional structure.

[0041] III. Physical Mechanism The core physical mechanism by which this invention improves SEB resistance reliability is as follows: 1. Thermal inhibition effect ( Figure 8 ): After 1 ns of incident radiation at the same drain voltage (570V), the peak temperature of the incident path of the MB-MOSFET is approximately 1500K, while the highest lattice temperature of the PI-MB-MOSFET of this invention is reduced to 1200K, a decrease of 20% (approximately 300K). This effectively prevents the local temperature from reaching the melting point of SiC.

[0042] 2. Electric field reconstruction effect ( Figure 9 The superjunction-like structure formed by the P-island and the buffer layer uniformly flattens the electric field peak that was originally concentrated at the buffer layer interface. The electric field intensity in the buffer layer region of the PI-MB-MOSFET is reduced by approximately [missing information - likely a percentage] compared to the MB-MOSFET. The decrease was 16.7%.

[0043] 3. Carrier density modulation ( Figure 10 When a single particle is incident for 1 ns, the carrier multiplication effect is weakened due to the lowered electric field. The electron density of this invention is only about 50% of that of MB-MOSFET.

[0044] In summary, this invention achieves a dual reduction of high electric field and high current density in the incident path through the synergistic effect of arrayed P-islands and multiple buffer layers, significantly reducing transient power density and lattice temperature, and solving the thermal failure problem of SiC MOSFETs under space radiation environment.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An arrayed P-island and multi-buffered layer SiC MOSFET with enhanced single-particle rejection capability, characterized in that: include: Drain metal (110); A substrate (109) and a buffer layer structure are stacked on the drain metal (110). The buffer layer structure includes buffer layer four (114), buffer layer three (113), buffer layer two (112) and buffer layer one (111) arranged sequentially from bottom to top. An N-drift layer (108) is disposed on the buffer layer structure. The P-body region (106) disposed within the N-drift layer (108) and the P+ shielding region (107) located at the bottom of the P-body region (106). The N+ source region (104) and the P+ contact region (105) are located within the P-body region (106) and are adjacent to each other. A gate oxide layer (103) disposed above the P+ shielding region (107) and a gate (102) surrounded by the gate oxide layer (103). Source metal (101) covering the N+ source region (104), P+ contact region (105) and part of the gate (102). Multiple P islands, including left and right P islands (115) disposed inside the first buffer layer (111), the second buffer layer (112), and the third buffer layer (113), and a middle P island (116) disposed inside the first buffer layer (111) and located between the left and right P islands (115).

2. The arrayed P-island and multi-buffered layer SiC MOSFET with enhanced single-particle rejection capability according to claim 1, characterized in that: The thickness of the first buffer layer (111), the second buffer layer (112), the third buffer layer (113), and the fourth buffer layer (114) is 0.7 μm.

3. The arrayed P-island and multi-buffered layer SiC MOSFET with enhanced single-particle rejection capability according to claim 2, characterized in that: The N-type doping concentrations of the buffer layer one (111), buffer layer two (112), buffer layer three (113), and buffer layer four (114) are respectively as follows: , , , .

4. The arrayed P-island and multi-buffered layer SiC MOSFET with enhanced single-particle rejection capability according to claim 1, characterized in that: The buffer layer four (114) has a groove with a width of 2.45 μm in the middle, which divides the buffer layer four (114) into two separate parts, left and right.

5. The arrayed P-island and multi-buffered layer SiC MOSFET with enhanced single-particle rejection capability according to claim 1, characterized in that: The P-type doping concentration of the intermediate P-island (116) is The thickness is 0.2 μm, and the distance between its lower surface and the upper surface of the substrate (109) is 0.4 μm.

6. The arrayed P-island and multi-buffered layer SiC MOSFET with enhanced single-particle rejection capability according to claim 1, characterized in that: The P-type doping concentration of the left and right P islands (115) is: The thickness is 0.2μm.

7. The arrayed P-island and multi-buffered layer SiC MOSFET with enhanced single-particle rejection capability according to claim 6, characterized in that: The distance between the lower surface of the left and right P islands (115) and the upper surface of the substrate (109) is 0.4 μm.

8. The arrayed P-island and multi-buffered layer SiC MOSFET with enhanced single-particle rejection capability according to claim 1, characterized in that: The distance between the inner wall of the left and right P islands (115) and the side wall of the middle P island (116) is 0.45 μm.

9. The arrayed P-island and multi-buffered layer SiC MOSFET with enhanced single-particle rejection capability according to claim 1, characterized in that: The multiple P-islands are arranged in an array in the vertical direction, and in the horizontal direction, they form a superjunction structure with the buffer layer structure, in which N-type pillars and P-type pillars alternate side by side.

10. The arrayed P-island and multi-buffered layer SiC MOSFET with enhanced single-particle rejection capability according to claim 1, characterized in that: The left and right P islands (115) have three layers, and the vertical spacing between them is 0.7 μm.

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