Semiconductor device and chip
By integrating a Schottky diode into a silicon carbide device, the switching loss problem caused by parasitic diodes under high temperature conditions is solved, resulting in a smaller chip area and lower switching loss, and improving the reverse blocking capability and operating efficiency of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BYD CO LTD
- Filing Date
- 2025-04-17
- Publication Date
- 2026-06-09
AI Technical Summary
When the parasitic diode of a silicon carbide device is forward-biased under high-temperature conditions, the minority carrier lifetime increases, resulting in a longer time to recover to the reverse blocking state and increasing switching losses.
By integrating a Schottky diode into a silicon carbide device, a Schottky contact is formed by setting a shielding region, first and second gate structures, and a trench structure through the shielding region in the epitaxial region, which suppresses the conduction of parasitic diodes and reduces switching losses.
It effectively reduces the switching losses of silicon carbide devices, reduces the chip area, and improves the reverse blocking capability and operating efficiency of the devices.
Smart Images
Figure CN224343674U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductors, and more particularly to a semiconductor device and chip. Background Technology
[0002] Silicon carbide (SiC), as an emerging semiconductor material, possesses excellent physical and chemical properties, making silicon carbide devices (such as metal oxide field effect transistors (MOSFETs) made of silicon carbide) widely applicable in electric vehicles and their related infrastructure.
[0003] At room temperature, the parasitic diode (body diode) of a silicon carbide (SiC) device exhibits freewheeling properties during reverse conduction. However, at high temperatures, the lifetime of minority carriers (holes) entering the drift region increases during forward conduction, resulting in a longer recovery time to the reverse blocking state and consequently, increased switching losses in the SiC device.
[0004] Therefore, reducing the switching losses of devices is a crucial issue. Utility Model Content
[0005] This application provides semiconductor devices and chips to reduce switching losses of the devices.
[0006] In a first aspect, embodiments of this application provide a semiconductor device, including:
[0007] Substrate;
[0008] An epitaxial region is disposed on the substrate;
[0009] A shielding area, wherein the shielding area is disposed within the extensional area;
[0010] A first gate structure is disposed on the epitaxial region and connected to the shielding region;
[0011] The second gate structure is disposed on the epitaxial region and connected to the shielding region, and is spaced apart from the first gate structure;
[0012] A trench structure is located between the first gate structure and the second gate structure and extends through the shielding region. The portion of the trench structure extending through the shielding region is filled with source metal, and the source metal and the epitaxial region form a Schottky contact.
[0013] In one possible implementation, the trench structure includes:
[0014] A first groove is disposed on a side opposite to the extensional region;
[0015] The second trench is disposed on the side facing the extension region, connected to the first trench, and penetrates the shielding region.
[0016] In one possible implementation, the epitaxial region includes:
[0017] The drift region is connected to the substrate.
[0018] In one possible implementation, the epitaxial region further includes:
[0019] A diffusion region located between the substrate and the drift region.
[0020] In one possible implementation, it also includes:
[0021] A well region is located on the epitaxial region and is connected to one side of the first gate structure and one side of the second gate structure.
[0022] In one possible implementation, it also includes:
[0023] Drain metal region, which is located on the substrate and on the side opposite to the epitaxial region.
[0024] In one possible implementation, it also includes:
[0025] The first ohmic contact region is located on the well region and is opposite to the epitaxial region on one side, and is connected to one side of the first gate structure and one side of the second gate structure.
[0026] In one possible implementation, it also includes:
[0027] The second ohmic contact region is located on the well region, away from the side of the epitaxial region, and connected to one side of the first ohmic contact region.
[0028] In one possible implementation, it also includes:
[0029] The source metal region is located on the first ohmic contact region, the second ohmic contact region, the first gate structure, the second gate structure, and the trench structure.
[0030] In one possible implementation, the substrate, the epitaxial region, and the first ohmic contact region are of a first conductivity type, and the shielding region, the well region, and the second ohmic contact region are of a second conductivity type.
[0031] In one possible implementation, the doping concentration range of the substrate, the shielding region, the first ohmic contact region, and the second ohmic contact region is 1 × 10⁻⁶. 18 ㎝ -3 -1×10 20 ㎝ -3 .
[0032] In one possible implementation, the doping concentration of the first ohmic contact region is in the range of 1 × 10⁻⁶. 19 ㎝ -3 -1×10 20 ㎝ -3 ;
[0033] In one possible implementation, the doping concentration of the second ohmic contact region is in the range of 1 × 10⁻⁶. 19 ㎝ -3 -1×10 20 ㎝ -3 .
[0034] In one possible implementation, the doping concentration range of the substrate, the epitaxial region, and the well region is 1 × 10⁻⁶. 14 ㎝ -3 -1×10 18 ㎝ -3 .
[0035] In one possible implementation, the doping concentration of the well region ranges from 1 × 10⁻⁶. 16 ㎝ -3 -1×10 18 ㎝ -3 .
[0036] In one possible implementation, the depth of the first trench is less than 1.5 μm.
[0037] In one possible implementation, the depth of the second trench is greater than the depth of the shielding area.
[0038] In one possible implementation, the depth of the second trench ranges from 0.3 μm to 1 μm.
[0039] In one possible implementation, the second groove includes at least one of the following: a square groove, a trapezoidal groove, a conical groove, and an irregular groove.
[0040] In one possible implementation, the first gate structure and the second gate structure include a gate metal and a gate dielectric surrounding the gate metal.
[0041] Secondly, this application provides a chip, including the semiconductor device of the first aspect.
[0042] The semiconductor device and chip provided in this application include a substrate, an epitaxial region on the substrate, a shielding region disposed within the epitaxial region, a first gate structure disposed on the epitaxial region and connected to the shielding region, a first gate structure disposed on the epitaxial region and connected to the shielding region and spaced apart from the first gate structure, and a trench structure located between the first gate structure and the second gate structure and penetrating the shielding region. The portion of the trench structure penetrating the shielding region is filled with source metal, and the source metal and the epitaxial region form a Schottky contact, thereby integrating a Schottky diode within the semiconductor device and reducing the switching losses of the semiconductor device. Attached Figure Description
[0043] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0044] Figure 1 Schematic diagram of the structure of the semiconductor device provided in this application Figure 1 ;
[0045] Figure 2 Schematic diagram of the structure of the semiconductor device provided in this application Figure 2 ;
[0046] Figure 3 Schematic diagram of the structure of the semiconductor device provided in this application Figure 3 ;
[0047] Figure 4 Schematic diagram of the structure of the semiconductor device provided in this application Figure 4 ;
[0048] Figure 5 Schematic diagram of the structure of the semiconductor device provided in this application Figure 5 ;
[0049] Figure 6 Schematic diagram of the structure of the semiconductor device provided in this application Figure 6 ;
[0050] Figure 7 Schematic diagram of the structure of the semiconductor device provided in this application Figure 7 ;
[0051] Figure 8 Schematic diagram of the structure of the semiconductor device provided in this application Figure 8 .
[0052] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0053] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0054] As described in the background section, in silicon carbide (SiC) devices at high temperatures, the minority carrier (hole) lifetime in the drift region increases during the forward conduction of the parasitic diode, resulting in a longer recovery time to the reverse blocking state. This leads to increased switching losses in SiC devices, and the switching losses caused by the recovery to the reverse blocking state become non-negligible as the operating frequency of the SiC device increases. Furthermore, the forward conduction of the parasitic diode introduces a bipolar (electron and hole) degradation effect. Therefore, suppressing the turn-on of the parasitic diode can effectively reduce the switching losses of SiC devices.
[0055] For example, a Schottky barrier diode (SBD) can be connected in parallel with a silicon carbide device to use the Schottky diode as a freewheeling diode for the silicon carbide device, thereby reducing the switching losses of the silicon carbide device.
[0056] The applicant discovered that by integrating (intracellularly integrating) Schottky diodes within silicon carbide devices, it is possible to reduce chip area.
[0057] To this end, this application proposes a semiconductor device including an epitaxial region, a shielding region disposed within the epitaxial region, a first gate structure disposed on the epitaxial region and connected to the shielding region, a first gate structure disposed on the epitaxial region and connected to the shielding region and spaced apart from the first gate structure, and a trench structure located between the first gate structure and the second gate structure and penetrating the shielding region. The portion of the trench structure penetrating the shielding region is filled with source metal, and the source metal and the epitaxial region form a Schottky contact, thereby integrating a Schottky diode within the semiconductor device and reducing the switching losses of the semiconductor device. Furthermore, compared to forming a Schottky diode outside the semiconductor device, the chip area can be reduced. In addition, by using a split-gate method for the first and second gate structures, the chip area can be further reduced, and the gate-drain capacitance can also be reduced, achieving a shorter switching time and reducing switching losses.
[0058] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.
[0059] Figure 1 A schematic diagram of the structure of the semiconductor device provided in this application is shown below. Figure 1 As shown, the semiconductor device includes:
[0060] Substrate 211; epitaxial region 210 disposed on substrate 211; shielding region 221 disposed within epitaxial region 210; first gate structure 240 disposed on epitaxial region 210 and connected to shielding region 221; second gate structure 242 disposed on epitaxial region 210, connected to shielding region 221, and spaced apart from first gate structure 240; trench structure located between first gate structure 240 and second gate structure 242, penetrating shielding region 221; the portion of the trench structure penetrating shielding region 221 is filled with source metal, and the source metal and epitaxial region 210 form a Schottky contact (e.g., Figure 1 (The position of the dotted line in the middle).
[0061] For example, semiconductor devices can be used in chips for new energy vehicles, smart home appliances, rail transportation, and aerospace, as well as in chips for other fields. This application does not impose any special limitations on this.
[0062] For example, semiconductor devices may include silicon carbide metal oxide semiconductor field-effect transistors, or devices made of silicon (Si), germanium (Ge), silicon germanide (SiGe), etc.
[0063] In this embodiment of the application, an epitaxial region 210 is provided on the substrate 211. The substrate 211 provides the basis for mechanical support, enabling the entire semiconductor device to be stably constructed and operated. The substrate 211 is usually a semiconductor material (such as silicon, silicon carbide, gallium arsenide, etc.), and its electrical characteristics can affect the overall performance of the device. It can be an intrinsic semiconductor, a doped semiconductor, or an insulator.
[0064] The epitaxial region 210 is typically the active region of the device, where the main electron and hole transport and reaction occur. It can be doped to achieve the desired electrical characteristics, such as switching speed, power handling capability, and frequency response.
[0065] In this embodiment, a shielding region 221 is provided in the epitaxial region 210. When the semiconductor device is in a reverse blocking state, the shielding layer can effectively shield the high electric field generated in the device body region, thereby reducing the electric field strength of the gate structure and Schottky contact region, which helps to improve the reverse blocking capability of the device and solve problems such as gate dielectric breakdown or Schottky contact degradation caused by high electric field.
[0066] It should be noted that the shielding region 221 is located within the epitaxial region 210, and the surface of the epitaxial region 210 away from the substrate 211 is flush with the surface of the shielding region 221 away from the substrate 211.
[0067] In this embodiment, the gate structure of the semiconductor device is a split-gate structure, including a first gate structure 240 and a second gate structure 242. The first gate structure 240 is disposed on the epitaxial region 210 and connected to the shielding region 221, and the second gate structure 242 is disposed on the epitaxial region 210 and connected to the shielding region 221. Accordingly, the shielding region 221 can effectively reduce the electric field strength of the gate structure.
[0068] The connection between the first gate structure 240 and the shielding region 221 can be such that the surface of the first gate structure 240 near the epitaxial region 210 contacts a portion of the epitaxial region 210 and a portion of the isolation region 221. The connection between the second gate structure 242 and the shielding region 221 can be such that the surface of the second gate structure 242 near the epitaxial region 210 (e.g., Figure 1 The lower surface of the second gate structure 242, and a portion of the epitaxial region 210 (e.g., the lower surface of the second gate structure 242), and a portion of the epitaxial region 210 (e.g., the lower surface of the second gate structure 242). Figure 1 (part of the upper surface of the middle extension zone 210) and part of the isolation zone 221 (e.g.) Figure 1 (Part of the upper surface of the isolation zone 221) in contact.
[0069] Furthermore, the first gate structure 240 and the second gate structure 242 are spaced apart, and the first gate structure 240 and the second gate structure 242 form a trench structure that penetrates the shielding region 221. The portion of the trench structure penetrating the shielding region 221 is filled with source metal. Since the trench structure penetrates the shielding region 221, and the portion of the trench structure penetrating the shielding region 221 is filled with source metal, the source metal can contact the epitaxial region 210 to form a Schottky contact. The Schottky contact can act as a freewheeling diode, suppressing the conduction of parasitic diodes, preventing bipolar degradation of the device, and reducing the switching losses of the device. In addition, with the same chip area, using the same raw materials, the Schottky contact formed by the trench structure of this application can reduce the occupied chip area, thereby increasing the Schottky contact area without excessively increasing the chip area. Furthermore, since the metal-semiconductor junction of the Schottky diode has a lower barrier height than that of a conventional PN junction diode, its forward voltage drop is typically lower, reducing the power consumption of the device and improving the operating efficiency of the device.
[0070] In one specific embodiment, the first gate structure 240 and the second gate structure 242 include a gate metal and a gate dielectric 241 surrounding the gate metal. The gate dielectric 241 prevents direct current conduction between the gate metal and the semiconductor substrate 211, thereby ensuring the normal operation of the device.
[0071] For example, the gate metal can be polysilicon, doped polysilicon, tungsten, copper, aluminum, gold, silver, etc. The gate dielectric 241 can be an oxide or other insulating dielectric.
[0072] In some alternative embodiments, the trench structure includes a first trench 243 and a second trench 244. The first trench 243 is disposed on the side away from the epitaxial region 210, and the second trench 244 is disposed on the side facing the epitaxial region 210, connected to the first trench 243, and penetrating the shielding region 221. Accordingly, the second trench 244 may be filled with source metal, and the source metal in the second trench 244 forms a Schottky contact with the epitaxial region 210. Source metal may also be formed in the first trench 243 to form a source region and provide a current path.
[0073] For example, such as Figure 1 As shown, the first trench 243 is disposed between the first gate structure 240 and the second gate structure 242, and the second trench 244 is disposed below the first trench 243 and penetrates the isolation region 221.
[0074] For example, the portion of the trench structure that penetrates the shielding area 221 can be a second trench 244.
[0075] For example, the source metal filled in the second trench 244 can be a conductive metal, such as aluminum, copper, titanium, nickel, gold, etc.
[0076] In one specific embodiment, the depth of the first trench 243 may be less than the depth of the well region 222. For example, the depth of the first trench 243 may be less than 1.5 μm to prevent damage to the gate dielectric 241 during the etching of the second trench 244.
[0077] In one specific implementation, the depth of the second trench 244 can be greater than the depth of the shielding region 221, that is, the second trench 244 penetrates the shielding region 221 and extends into the epitaxial region 210, thereby increasing the area of the Schottky contact and enabling the Schottky diode to withstand and conduct a larger current.
[0078] For example, the depth of the second trench 244 ranges from 0.3 μm to 1 μm. For instance, it can be 0.3 μm, 0.6 μm, 0.8 μm, 1 μm, etc.
[0079] For example, the second groove may include regular and / or irregular grooves, and the regular groove may include at least one of square, trapezoidal, and conical grooves. For example, as Figure 1 As shown, the second trench 244 is a square trench, and the shape of the source metal filled in the second trench 244 is adapted to the shape of the second trench 244.
[0080] In one alternative embodiment, the epitaxial region 210 includes a drift region 212 connected to the substrate 211. Accordingly, an isolation region 221 is disposed within the drift region 212, and the source metal partially filled within the trench penetrating the shielding region 221 forms a Schottky contact with the drift region 212. Furthermore, the surface of the drift region 212 away from the substrate 211 is flush with the surface of the shielding region 221 away from the substrate 211. When the device is in the off state, a wider depletion region can be formed in the drift region 212, thereby enabling it to withstand high voltages without breakdown. For example, by adjusting the thickness and doping concentration of the drift region 212, the thermal conductivity and thermal stability of the device can be improved.
[0081] In some alternative embodiments, the epitaxial region 210 includes a drift region 212 and a diffusion region 213, with the diffusion region 213 located between the substrate 211 and the drift region 212. Correspondingly, an isolation region 221 is disposed within the diffusion region 213, and the source metal partially filling the trench through the shielding region 221 forms a Schottky contact with the diffusion region 213. Furthermore, the surface of the diffusion region 213 away from the substrate 211 is flush with the surface of the shielding region 221 away from the substrate 211. The diffusion region 213 helps reduce the on-resistance of the device, improves its conduction performance, and allows the device to withstand higher current densities, thereby improving its current handling capability.
[0082] In some alternative embodiments, the semiconductor device further includes a well region 222 located on the epitaxial region 210 and connected to one side of the first gate structure 240 and one side of the second gate structure 242. The well region 222 is typically a region formed by doping, with the doping type opposite to that of the substrate 211. For example, a p-type well region 222 formed on an n-type substrate 211. When an appropriate gate voltage is applied to the gate structure, charge carriers (such as electrons or holes) in the well region 222 form a conductive channel under the control of the gate voltage, thereby allowing current to flow between the source and drain. The well region 222 is also used to achieve device isolation in integrated circuits; by forming multiple well regions 222 on the same substrate 211, multiple independent devices can be implemented on the same chip. The doping concentration and depth of the well region 222 can tune the electrical characteristics of the device, including threshold voltage, breakdown voltage, and on-resistance, thereby enabling optimization of device performance according to specific application requirements.
[0083] For example, such as Figure 1 As shown, the well region 222 and the side of the first gate structure 240 away from the second gate structure 242 (e.g.) Figure 1 The well region 222 is in contact with the left side of the first gate structure 240, and the well region 222 is also in contact with the side of the second gate structure 242 away from the first gate structure 240 (e.g., the left side of the first gate structure 240). Figure 1 (The right side of the second gate structure 242) is contacted.
[0084] In some alternative embodiments, the semiconductor device further includes a drain metal region 231 located on the substrate 211 and on the side opposite to the epitaxial region 210. The drain metal region 231 is used to receive and transmit charge carriers flowing from the source through the conductive channel, and transmit them to the external circuit, thereby realizing functions such as power supply or signal transmission to the external load.
[0085] For example, the drain metal region 231 may include a drain metal, which may include aluminum, copper, titanium, nickel, gold, etc.
[0086] In some alternative embodiments, the semiconductor device further includes a first ohmic contact region 214 located on the well region 222, facing away from the epitaxial region 210, and connected to one side of the first gate structure 240 and one side of the second gate structure 242. The first ohmic contact region 214 forms an ohmic contact, which improves the breakdown voltage of the device and reduces the resistance when the device is turned on. Furthermore, the first ohmic contact region 214 provides a primary channel for electrons, allowing current to flow between the source and drain.
[0087] In some alternative embodiments, the semiconductor device includes a first ohmic contact region 214 and a second ohmic contact region 223, both located on the well region 222 and facing away from the epitaxial region 210. The first ohmic contact region 214 is connected to one side of the first gate structure 240 and one side of the second gate structure 242, and the second ohmic contact region 223 is connected to one side of the first ohmic contact region 214. The first ohmic contact region 214 provides the primary electron path, allowing current to flow between the source and drain. By adjusting the doping concentration and size of the first ohmic contact region 214, the on-resistance can be reduced, improving the switching speed and efficiency of the device. The second ohmic contact region 223 is used to stabilize the potential of the well region 222, suppress parasitic effects, and prevent well drift, thereby improving the stability of the device.
[0088] For example, the first gate structure 240 is located on the side away from the second gate structure 242 (e.g. Figure 1 The left side of the first gate structure 240 and one side of the well region 222 (e.g., the left side of the first gate structure 240) and one side of the well region 222 Figure 1 The right side of the left-side well region 222) and one side of the first ohmic contact region 214 (e.g. Figure 1 The right side of the first ohmic contact region 214 on the left side of the middle gate structure 240 is contacted, and the second gate structure 242 is located on the side away from the first gate structure 240 (e.g., the side away from the first gate structure 240). Figure 1 The right side of the second gate structure 242 and one side of the well region 222 (e.g., the right side of the second gate structure 242) and one side of the well region 222. Figure 1 The left side of the right-side well region 222) and one side of the first ohmic contact region 214 (e.g. Figure 1 The left side of the first ohmic contact area 214 on the right side of the middle is in contact.
[0089] In some alternative implementations, the semiconductor device includes a source metal region 230 located on a first ohmic contact region 214, a second ohmic contact region 223, a first gate structure 240, a second gate structure 242, and a trench structure, thereby providing current input and providing an interface for the semiconductor device to connect to external circuitry.
[0090] In some specific embodiments, the substrate 211, the epitaxial region 210 and the first ohmic contact region 214 are of the first conductivity type, and the shielding region 221, the well region 222 and the second ohmic contact region 223 are of the second conductivity type.
[0091] For example, the first conductivity type is n-type and the second conductivity type is p-type, or the first conductivity type is p-type and the second conductivity type is n-type.
[0092] In some specific embodiments, the shielding region 221, the substrate 211, the first ohmic contact region 214, and the second ohmic contact region 223 are heavily doped regions with a doping concentration ranging from 1×10⁻⁶. 18 ㎝ -3 -1×10 20 ㎝ -3 For example, 1×10 18 ㎝ -3 5×10 18 ㎝ -3 8×10 18 ㎝ -3 1×10 19 ㎝ -3 4×10 19 ㎝ -3 7×10 19 ㎝ -3 1×10 20 ㎝ -3 wait.
[0093] For example, the doping concentration of the shielding region 221 ranges from 1 × 10⁻⁶. 18 ㎝ -3 -1×10 20 ㎝ -3 For example, the doping concentration of shielding region 221 is 1×10 18 ㎝ -3 5×10 18 ㎝ -3 8×10 18 ㎝ -3 1×10 19 ㎝ -3 4×10 19 ㎝ -37×10 19 ㎝ -3 1×10 20 ㎝ -3 wait.
[0094] The doping concentration range of the first ohmic contact region 214 is 1×10⁻⁶. 19 ㎝ -3 -1×10 20 ㎝ -3 For example, the doping concentration of the first ohmic contact region 214 is 1×10⁻⁶. 19 ㎝ -3 4×10 19 ㎝ -3 7×10 19 ㎝ -3 1×10 20 ㎝ -3 wait.
[0095] The doping concentration range of the second ohmic contact region 223 is 1×10⁻⁶. 19 ㎝ -3 -1×10 20 ㎝ -3 For example, the doping concentration of the second ohmic contact region 223 is 1×10⁻⁶. 19 ㎝ -3 4×10 19 ㎝ -3 7×10 19 ㎝ -3 1×10 20 ㎝ -3 wait.
[0096] In some specific embodiments, the epitaxial region 210 and the well region 222 are lightly doped regions with a doping concentration ranging from 1×10⁻⁶. 14 ㎝ -3 -1×10 18 ㎝ -3 For example, 1×10 14 ㎝ -3 1×10 15 ㎝ -3 1×10 16 ㎝ -3 1×10 17 ㎝ -3 1×10 18 ㎝ -3 wait.
[0097] For example, the doping concentration of well region 222 ranges from 1 × 10⁻⁶. 16 ㎝ -3 -1×10 18 ㎝ -3 For example, 1×10 16 ㎝-3 5×10 16 ㎝ -3 1×10 17 ㎝ -3 5×10 17 ㎝ -3 1×10 18 ㎝ -3 wait.
[0098] The semiconductor device provided in this application has been described above. The semiconductor device includes an epitaxial region 210, a shielding region 221 disposed within the epitaxial region 210, a first gate structure 240 disposed on the epitaxial region 210 and connected to the shielding region 221, a first gate structure 240 disposed on the epitaxial region 210 and connected to the shielding region 221 and spaced apart from the first gate structure 240, and a trench structure located between the first gate structure 240 and the second gate structure 242 and penetrating the shielding region 221. The portion of the trench structure penetrating the shielding region 221 is filled with source metal, and the source metal and the epitaxial region 210 form a Schottky contact, thereby integrating a Schottky diode within the semiconductor device and reducing the switching losses of the semiconductor device.
[0099] This application also provides a method for fabricating a semiconductor device, which may include:
[0100] (1) Provide a substrate.
[0101] For example, the substrate 211 is a first conductivity type substrate 211, and the first conductivity type is, for example, n-type.
[0102] (2) An epitaxial region is formed on the substrate.
[0103] For example, a drift region 212 and a diffusion region 213 can be epitaxially grown sequentially from bottom to top on a substrate 211, such as... Figure 2 As shown.
[0104] In some specific embodiments, a buffer zone can also be epitaxially grown between the substrate 211 and the drift region 212. For example, the buffer zone is an n-type heavily doped region, and the drift region 212 and the diffusion region 213 are n-type lightly doped regions.
[0105] (3) A shielding zone is formed within the extensional region.
[0106] A well region 222 is formed on the extensional region 210, such as Figure 3 As shown, trenches are then formed in the well region 222 by depositing an implantation mask on the well region 222, photolithographically patterning the area, and etching trenches. Figure 4As shown, the trenches in the well region 222 expose a portion of the surface of the epitaxial region 210. Ion implantation is then used to dope the epitaxial region 210 to form an isolation region 221, and a first ohmic contact region 214 and a second ohmic contact region 223 are formed in the well region 222. Figure 5 As shown.
[0107] (4) A first gate structure and a second gate structure are formed on the epitaxial region. The first gate structure is connected to the shielding region, and the second gate structure is connected to the shielding region and is spaced apart from the first gate structure.
[0108] An implantation mask is deposited within the trenches in the well region 222, and multiple trenches are formed through photolithography patterning, etching, and other processes. Figure 6 As shown. For example, using a photolithographic transfer pattern, an implantation mask layer is formed, and using doping methods such as ion implantation, a first ohmic contact region 214 is formed above a portion of the well region 222; using a photolithographic transfer pattern, an implantation mask layer is formed, and using doping methods such as ion implantation, a second ohmic contact region 223 is formed above a portion of the well region 222; using a photolithographic transfer pattern, a deposition mask is formed to deposit a gate dielectric insulator; using a photolithographic transfer pattern, an etching mask layer is formed to etch out, as shown... Figure 6 The trench area shown.
[0109] Subsequently, gate metal is filled into a portion of the trench to form a first gate structure 240 and a second gate structure 242, such as Figure 7 As shown. For example, a deposition mask layer is formed using photolithography to transfer patterns, and a highly conductive material is deposited to serve as the gate, which can be heavily doped polysilicon; when filling the highly doped polysilicon, the highly doped polysilicon should completely cover the bottom insulating layer and have a planarized surface; after depositing the highly doped polysilicon conductive material, a gate oxide layer is formed on its surface, which can be obtained by oxidation or deposition, to isolate it from the subsequent source metal.
[0110] Then, etching continues within the trench between the first gate structure 240 and the second gate structure 242, so that the trench between the first gate structure 240 and the second gate structure 242 penetrates the isolation region 221, as shown. Figure 8 As shown, an etching mask layer is formed by using photolithography to transfer the pattern, and a trench penetrating the isolation region 221 is etched in the middle trench region.
[0111] (5) The source metal is filled in the trench between the first gate structure and the second gate structure so that the source metal filled in the part of the trench that penetrates the shielding area and the epitaxial region form a Schottky contact.
[0112] For example, source metal is deposited on the inner wall of the groove so that the source metal contacts the inner surface of the groove to form a Schottky contact. The anode metal is deposited by vapor deposition and then annealed at high temperature under nitrogen protection to form a Schottky barrier electrode with the epitaxial region 210.
[0113] Drain metal regions can also be deposited on the lower surface of substrate 211. For example, drain metal can be deposited on the lower surface of substrate 211 by vapor deposition.
[0114] Thus, a semiconductor device integrating a Schottky diode is formed. When the source to drain of the device is forward-biased, the Schottky diode conducts, thereby effectively reducing the bipolar degradation effect caused by the conduction of the parasitic diode, reducing the turn-on voltage and the turn-off loss of the diode. Compared with traditional devices with intracellular integrated Schottky diodes, it occupies a smaller area and has a smaller gate-drain capacitance, making it more suitable for high-frequency applications.
[0115] This application also provides a chip that includes the semiconductor device described above.
[0116] In practical applications, this chip is used in new energy vehicles, smart home appliances, rail transportation, and aerospace.
[0117] Finally, it should be noted that other embodiments of this utility model will readily conceive of by those skilled in the art upon consideration of the specification and practice of the utility model disclosed herein. This utility model is intended to cover any variations, uses, or adaptations of this utility model that follow the general principles of this utility model and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this utility model is limited only by the appended claims.
Claims
1. A semiconductor device, characterized in that, include: Substrate (211); An epitaxial region (210) is disposed on the substrate (211); A shielding area (221) is disposed within the extensional area (210); A first gate structure (240) is disposed on the epitaxial region (210) and connected to the shielding region (221); The second gate structure (242) is disposed on the epitaxial region (210) and connected to the shielding region (221), and is spaced apart from the first gate structure (240); A trench structure is located between the first gate structure (240) and the second gate structure (242) and extends through the shielding region (221). The portion of the trench structure extending through the shielding region (221) is filled with source metal, and the source metal and the epitaxial region (210) form a Schottky contact.
2. The semiconductor device according to claim 1, characterized in that, The trench structure includes: The first groove (243) is disposed on the side opposite to the extensional region (210); The second trench (244) is disposed on the side facing the extension region (210), connected to the first trench (243), and penetrates the shielding region (221).
3. The semiconductor device according to claim 1 or 2, characterized in that, The extensional region (210) includes: A drift region (212) is connected to the substrate (211).
4. The semiconductor device according to claim 3, characterized in that, The extension region (210) also includes: A diffusion region (213) is located between the substrate (211) and the drift region (212).
5. The semiconductor device according to claim 1 or 2, characterized in that, Also includes: The well region (222) is located on the epitaxial region (210) and is connected to one side of the first gate structure (240) and one side of the second gate structure (242).
6. The semiconductor device according to claim 1 or 2, characterized in that, Also includes: Drain metal region (231) is located on the substrate (211) and on the side opposite to the epitaxial region (210).
7. The semiconductor device according to claim 5, characterized in that, Also includes: The first ohmic contact region (214) is located on the well region (222) and is away from the epitaxial region (210) on one side, and is connected to one side of the first gate structure (240) and one side of the second gate structure (242).
8. The semiconductor device according to claim 7, characterized in that, Also includes: The second ohmic contact region (223) is located on the well region (222) and is opposite to the side of the extension region (210), and is connected to one side of the first ohmic contact region (214).
9. The semiconductor device according to claim 8, characterized in that, Also includes: The source metal region (230) is located on the first ohmic contact region (214), the second ohmic contact region (223), the first gate structure (240), the second gate structure (242) and the trench structure.
10. The semiconductor device according to claim 8, characterized in that, The substrate (211), the epitaxial region (210), and the first ohmic contact region (214) are of the first conductivity type, and the shielding region (221), the well region (222), and the second ohmic contact region (223) are of the second conductivity type.
11. The semiconductor device according to claim 8, characterized in that, The doping concentration range of the substrate (211), the shielding region (221), the first ohmic contact region (214), and the second ohmic contact region (223) is 1×10⁻⁶. 18 ㎝ -3 -1×10 20 ㎝ -3 .
12. The semiconductor device according to claim 11, characterized in that, The doping concentration range of the first ohmic contact region (214) is 1×10⁻⁶. 19 ㎝ -3 -1×10 20 ㎝ -3 .
13. The semiconductor device according to claim 11, characterized in that, The doping concentration range of the second ohmic contact region (223) is 1×10⁻⁶. 19 ㎝ -3 -1×10 20 ㎝ -3 .
14. The semiconductor device according to claim 5, characterized in that, The doping concentration range of the epitaxial region (210) and the well region (222) is 1×10⁻⁶. 14 ㎝ -3 -1×10 18 ㎝ -3 .
15. The semiconductor device according to claim 14, characterized in that, The doping concentration range of the well region (222) is 1×10⁻⁶. 16 ㎝ -3 -1×10 18 ㎝ -3 .
16. The semiconductor device according to claim 2, characterized in that, The depth of the first trench (243) is less than 1.5 μm.
17. The semiconductor device according to claim 2, characterized in that, The depth of the second trench (244) is greater than the depth of the shielding area (221).
18. The semiconductor device according to claim 2, characterized in that, The depth of the second trench (244) ranges from 0.3 μm to 1 μm.
19. The semiconductor device according to claim 2, characterized in that, The second groove (244) includes at least one of the following: square groove, trapezoidal groove, conical groove, and irregular groove.
20. The semiconductor device according to claim 1, characterized in that, The first gate structure (240) and the second gate structure (242) include a gate metal and a gate dielectric (241) surrounding the gate metal.
21. A chip, characterized in that, Includes the semiconductor device according to any one of claims 1-20.