High-voltage solid-state relay
By optimizing the structural layout and chip selection of high-voltage solid-state relays, the problem of insufficient creepage distance of existing solid-state relays in high-voltage scenarios has been solved, achieving normal operation and improved insulation isolation under high-voltage conditions.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- XIAMEN SILICON TOP OPTO ELECTRONICS CO LTD
- Filing Date
- 2025-05-26
- Publication Date
- 2026-06-12
AI Technical Summary
Due to their structural layout, existing solid-state relays have insufficient minimum creepage distance between input and output pins, making them unsuitable for high-voltage applications above 800 volts.
The high-voltage solid-state relay with a specific structural layout includes a lead frame, a power chip, a photosensitive chip, and a light-emitting chip. By optimizing the design of the lead frame, the creepage distance between adjacent input pins and output pins reaches more than 10 mm. It uses a 1500-volt SiC MOSFET chip and a light guide to cover the photosensitive chip and the light-emitting chip.
It enables high-voltage solid-state relays to operate normally in high-voltage scenarios, improves insulation isolation and withstand voltage, and is suitable for high-voltage environments above 800 volts.
Smart Images
Figure CN224356096U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of solid-state relays, and in particular to a high-voltage solid-state relay. Background Technology
[0002] Solid-state relays are a new type of contactless switching device composed entirely of solid-state electronic components. They utilize the switching characteristics of electronic components (such as transistors, triacs, MOSFETs, and other semiconductor devices) to achieve contactless and sparkless connection and disconnection of circuits.
[0003] However, due to their structural layout, existing solid-state relays have insufficient minimum creepage distance between their input and output pins, making them unsuitable for high-voltage applications above 800 volts.
[0004] In view of the above problems, it is necessary to study a high-voltage solid-state relay that can be applied to high-voltage scenarios. Utility Model Content
[0005] The purpose of this invention is to provide a high-voltage solid-state relay that is suitable for high-voltage scenarios.
[0006] To achieve the above objectives, the solution of this utility model is:
[0007] A high-voltage solid-state relay, characterized in that it comprises a solid-state relay body and a plastic encapsulation covering the solid-state relay body;
[0008] The solid-state relay body includes a lead frame, a first power chip, a second power chip, a photosensitive chip, and a light-emitting chip;
[0009] The lead frame includes a first wafer carrier, a second wafer carrier, a third wafer carrier, a first input pin, a second input pin, a first output pin, and a second output pin. The first and second wafer carriers, the first and second output pins are located on the left side of the lead frame, while the third wafer carrier, the first input pin, and the second input pin are located on the right side of the lead frame. A notch is formed on the lower right side of the first wafer carrier to accommodate the second wafer carrier. The third wafer carrier is positioned above the first and second output pins. The first, second, first, and second output pins are arranged side-by-side and partially protrude from the plastic package. The first output pin is connected to the first wafer carrier, the second output pin is connected to the second wafer carrier, and the second input pin is connected to the second input pin. The output pins are arranged adjacent to each other, and the creepage distance between the second input pin and the second output pin is greater than 10 mm; the first power chip, the second power chip, and the photosensitive chip are respectively mounted on the first wafer stage, the second wafer stage, and the third wafer stage. The first end of the photosensitive chip is electrically connected to the gate of the first power chip and the gate of the second power chip, and the second end of the photosensitive chip is electrically connected to the source of the first power chip and the source of the second power chip. The drain of the first power chip is electrically connected to the first wafer stage, and the drain of the second power chip is electrically connected to the second wafer stage; the light-emitting chip is opposite to the photosensitive chip, the light-emitting chip is fixed on the first input pin, and the first end of the light-emitting chip is electrically connected to the first input pin, and the second end of the light-emitting chip is electrically connected to the second output pin.
[0010] The first end of the photosensitive chip is connected to the gate of the first power chip and the gate of the second power chip via a metal wire, respectively. The second end of the photosensitive chip is connected to the source of the first power chip and the source of the second power chip via a metal wire, respectively.
[0011] The drain of the first power chip is soldered to the first wafer stage, the drain of the second power chip is soldered to the second wafer stage, and the first end of the light-emitting chip is soldered to the first input pin.
[0012] The second output pin is located below the light-emitting chip, and the distance between the first output pin and the third wafer stage is greater than 1.5 mm. The minimum distance between the first wafer stage and the first input pin, the minimum distance between the first wafer stage and the second input pin, the minimum distance between the second wafer stage and the first input pin, and the minimum distance between the second wafer stage and the second input pin are all greater than the distance between the first output pin and the third wafer stage.
[0013] The first and second power chips use SiC MOSFETs.
[0014] The first and second power chips have a withstand voltage of at least 1500 volts.
[0015] The creepage distance between the first output pin and the second output pin is greater than 4.3 mm.
[0016] The areas of the first, second, and third film loading stages decrease sequentially.
[0017] The area of the second film stage is at least 22 square millimeters.
[0018] The plastic encapsulation contains a light guide that encapsulates the photosensitive chip and the light-emitting chip.
[0019] By adopting the above solution, the present invention, through the structural layout of the lead frame, makes the creepage distance between adjacent second input pins and second output pins greater than 10 mm, thereby enabling the high-voltage solid-state relay of the present invention to be applicable to high-voltage scenarios. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the structure of this utility model.
[0021] Figure 2 This is a partial structural schematic diagram of the present invention.
[0022] Figure 3 This is a schematic diagram of the lead frame of this utility model.
[0023] Figure 4 This is the circuit schematic diagram of this utility model.
[0024] Label Explanation:
[0025] Solid-state relay body A,
[0026] Lead frame 1, first wafer stage 11, notch 110, through hole 111, second wafer stage 12, third wafer stage 13, first input pin 14, second input pin 15, first output pin 16, second output pin 17.
[0027] First power chip 2,
[0028] Second power chip 3,
[0029] Photosensitive chip 4,
[0030] LED chip 5
[0031] Metal wire 6,
[0032] Encapsulated body B. Detailed Implementation
[0033] To further explain the technical solution of this utility model, the following detailed description is provided through specific embodiments.
[0034] like Figures 1 to 4As shown, this utility model discloses a high-voltage solid-state relay, which includes a solid-state relay body A and a plastic encapsulation body B covering the solid-state relay body A; wherein, the solid-state relay body A includes a lead frame 1, a first power chip 2, a second power chip 3, a photosensitive chip 4, and a light-emitting chip 5; the lead frame 1 is provided with a first substrate 11, a second substrate 12, a third substrate 13, a first input pin 14, a second input pin 15, a first output pin 16, and a second output pin 17; the first substrate 11 and the second substrate 12, the first output pin 16, and the second output pin 17 are located on the left side of the lead frame 1, and the third substrate 13, the first input pin 14, and the second input pin 15 are located on the right side of the lead frame 1. A notch is formed at the lower right of the first substrate 11 for accommodating the second substrate 12. The third substrate 13 is located above the first output pin 16 and the second output pin 17. The first output pin 16, the second output pin 17, the first input pin 14, and the second output pin 17 are arranged side by side. Partially protruding from the plastic encapsulation body B, the first output pin 16 is connected to the first wafer stage 11, the second output pin 17 is connected to the second wafer stage 12, the second input pin 15 and the second output pin 17 are arranged adjacent to each other and the creepage distance L1 between the second input pin 15 and the second output pin 17 is greater than 10 mm; the first power chip 2, the second power chip 3 and the photosensitive chip 4 are respectively fitted onto the first wafer stage 11, the second wafer stage 12 and the third wafer stage 13, the first end of the photosensitive chip 4 is electrically connected to the gate of the first power chip 2 and the gate of the second power chip 3, the second end of the photosensitive chip 4 is electrically connected to the source of the first power chip 2 and the source of the second power chip 3, the drain of the first power chip 2 is electrically connected to the first wafer stage 11, and the drain of the second power chip 3 is electrically connected to the second wafer stage 12; the light-emitting chip 5 is opposite to the photosensitive chip 4, the light-emitting chip 5 is fixed on the first input pin 14 and the first end of the light-emitting chip 5 is electrically connected to the first input pin 14, and the second end of the light-emitting chip 5 is electrically connected to the second output pin.
[0035] Through the structural layout of the lead frame 1 of this utility model, the creepage distance L1 between adjacent second input pins 15 and second output pins 17 is greater than 10 mm, thereby enabling the high-voltage solid-state relay of this utility model to be applicable to high-voltage scenarios.
[0036] In an embodiment of this utility model, the first end of the photosensitive chip 4 can be connected to the gate of the first power chip 2 and the gate of the second power chip 3 respectively via the metal wire 6. The second end of the photosensitive chip 4 can be connected to the source of the first power chip 2 and the source of the second power chip 3 respectively via the metal wire 6. The drain of the first power chip 2 can be soldered to the first substrate 11. The drain of the second power chip 3 can be soldered to the second substrate 12. The first end of the light-emitting chip 5 can be soldered to the first input pin 14.
[0037] In an embodiment of this invention, the second output pin 17 is located below the light-emitting chip 5, and the distance L2 between the first output pin 16 and the third substrate 13 is greater than 1.5 mm. The minimum distance between the first substrate 11 and the first input pin 14, the minimum distance between the first substrate 11 and the second input pin 15, the minimum distance between the second substrate 12 and the first input pin 14, and the minimum distance between the second substrate 12 and the second input pin 15 are all greater than the distance between the first output pin 16 and the third substrate 13. This arrangement ensures good insulation between the input and output circuits of the solid-state relay of this invention, which helps to improve the withstand voltage of the high-voltage solid-state relay of this invention.
[0038] In an embodiment of this utility model, the creepage distance L3 between the first output pin 16 and the second output pin 17 can be greater than 4.3 mm.
[0039] In embodiments of this invention, the areas of the first wafer carrier 11, the second wafer carrier 12, and the third wafer carrier 13 can be reduced sequentially, with the area of the second wafer carrier 12 being at least 22 square millimeters. This allows the first wafer carrier 11 and the second wafer carrier 12 to be compatible with most existing power chips. The first wafer carrier 11 may be provided with through-holes 111 to improve the bonding stability between the first wafer carrier 11 and the molding compound B.
[0040] In the embodiments of this utility model, the first power chip 2 and the second power chip 3 are high-voltage devices. Specifically, the first power chip 2 and the second power chip 3 are SiC MOSFETs, and the withstand voltage of the first power chip 2 and the second power chip 3 can be at least 1500 volts.
[0041] In an embodiment of this utility model, the encapsulation body B may contain a light guide (not shown) that covers the photosensitive chip 4 and the light-emitting chip 5, to ensure that the light emitted by the light-emitting chip 5 can be accurately transmitted to the photosensitive chip 4.
[0042] The above embodiments and figures are not intended to limit the product form and style of this utility model. Any appropriate changes or modifications made by those skilled in the art should be considered as not departing from the patent scope of this utility model.
Claims
1. A high-voltage solid-state relay, characterized in that: Includes the solid-state relay body and the plastic encapsulation covering the solid-state relay body; The solid-state relay body includes a lead frame, a first power chip, a second power chip, a photosensitive chip, and a light-emitting chip; The lead frame includes a first die carrier, a second die carrier, a third die carrier, a first input pin, a second input pin, a first output pin, and a second output pin. The first and second die carriers, the first and second output pins are located on the left side of the lead frame, while the third die carrier, the first input pin, and the second input pin are located on the right side of the lead frame. A notch is formed on the lower right side of the first die carrier for accommodating the second die carrier. The third die carrier is located above the first and second output pins. The first, second, first, and second output pins are arranged side by side and partially protrude from the plastic package. The first output pin is connected to the first die carrier, and the second output pin is connected to the second die carrier. The second input pin and the second output pin are arranged adjacent to each other, and the creepage distance between the second input pin and the second output pin is greater than 10 mm. A first power chip, a second power chip, and a photosensitive chip are respectively mounted on a first wafer carrier, a second wafer carrier, and a third wafer carrier. The first end of the photosensitive chip is electrically connected to the gate of the first power chip and the gate of the second power chip. The second end of the photosensitive chip is electrically connected to the source of the first power chip and the source of the second power chip. The drain of the first power chip is electrically connected to the first wafer carrier, and the drain of the second power chip is electrically connected to the second wafer carrier. A light-emitting chip is opposite to the photosensitive chip. The light-emitting chip is fixed on a first input pin, and the first end of the light-emitting chip is electrically connected to the first input pin. The second end of the light-emitting chip is electrically connected to the second output pin.
2. The high-voltage solid-state relay as described in claim 1, characterized in that: The first end of the photosensitive chip is connected to the gate of the first power chip and the gate of the second power chip via a metal wire, respectively. The second end of the photosensitive chip is connected to the source of the first power chip and the source of the second power chip via a metal wire, respectively.
3. The high-voltage solid-state relay as described in claim 1 or 2, characterized in that: The drain of the first power chip is soldered to the first wafer stage, the drain of the second power chip is soldered to the second wafer stage, and the first end of the light-emitting chip is soldered to the first input pin.
4. The high-voltage solid-state relay as described in claim 1, characterized in that: The second output pin is located below the light-emitting chip, and the distance between the first output pin and the third wafer stage is greater than 1.5 mm. The minimum distance between the first wafer stage and the first input pin, the minimum distance between the first wafer stage and the second input pin, the minimum distance between the second wafer stage and the first input pin, and the minimum distance between the second wafer stage and the second input pin are all greater than the distance between the first output pin and the third wafer stage.
5. The high-voltage solid-state relay as described in claim 1, characterized in that: The first and second power chips use SiC MOSFETs.
6. The high-voltage solid-state relay as described in claim 1 or 5, characterized in that: The first and second power chips have a withstand voltage of at least 1500 volts.
7. The high-voltage solid-state relay as described in claim 1, characterized in that: The creepage distance between the first output pin and the second output pin is greater than 4.3 mm.
8. The high-voltage solid-state relay as described in claim 1, characterized in that: The areas of the first, second, and third film loading stages decrease sequentially.
9. The high-voltage solid-state relay as described in claim 8, characterized in that: The area of the second film stage is at least 22 square millimeters.
10. The high-voltage solid-state relay as described in claim 1, characterized in that: The plastic encapsulation contains a light guide that encapsulates the photosensitive chip and the light-emitting chip.