Integrated circuit device

Abstract

An integrated circuit device is provided. The integrated circuit device includes a plurality of columns of semiconductor devices and a metal layer. The plurality of columns extends along a first axis and side-by-side along a second axis transverse to the first axis. The metal layer includes a plurality of conductors extending along a plurality of tracks, the plurality of tracks extending along the first axis. Each column of the plurality of columns includes a first active region of a first conductivity type and a second active region of a second conductivity type different from the first conductivity type, the second active region spaced apart from the first active region along the second axis. The plurality of columns includes a first column and a second column having a same first height along the second axis. The plurality of tracks includes a first track in the first column and a second track in the second column. A first number of the first tracks is different from a second number of the second tracks.

Description

Technical Field

[0001] This disclosure relates to integrated circuit devices. Background Technology

[0002] An integrated circuit (IC) device comprises one or more semiconductor devices presented in an IC layout (also known as an "IC design layout," "layout," "IC layout," or "layout"). A layout is hierarchical and includes modules that perform higher-order functions according to the design specifications of the semiconductor device. Modules are typically formed by combining cells, each cell representing one or more semiconductor structures for performing a specific function. Cells with pre-designed layouts (sometimes called standard cells) are stored in a standard cell library (hereinafter referred to as the "library" or "cell library") and are accessible by various tools (such as electronic design automation (EDA) tools) to generate, optimize, and verify IC designs. Power, performance, and area (PPA) are design considerations for IC devices. Utility Model Content

[0003] In one embodiment of this disclosure, the integrated circuit device includes a plurality of columns of semiconductor devices and a metal layer. The plurality of columns extend along a first axis and are arranged side-by-side along a second axis perpendicular to the first axis. The metal layer includes a plurality of conductors arranged along a plurality of tracks. The plurality of tracks extend along the first axis. Each of the plurality of columns includes a first active region of a first conductivity type and a second active region of a second conductivity type. The second conductivity type is different from the first conductivity type, and the second active region is spaced apart from the first active region along the second axis. The plurality of columns includes a first column and a second column having the same first height along the second axis. The plurality of tracks includes a plurality of first tracks in the first column and a plurality of second tracks in the second column. A first number of the plurality of first tracks is different from a second number of the plurality of second tracks. Attached Figure Description

[0004] The best understanding of the various forms disclosed herein can be obtained from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various feature components are not drawn to scale. In fact, for clarity, the dimensions of the various feature components may be arbitrarily increased or decreased.

[0005] Figure 1A This is a block diagram of an IC device according to some embodiments.

[0006] Figure 1B , Figure 1CThis is a schematic diagram of different levels of unit layout according to some embodiments.

[0007] Figure 2 This is a schematic cross-sectional view of the circuit area of ​​an IC device according to some embodiments.

[0008] Figures 3A to 3G This is a schematic diagram of the circuit layout of one or more IC devices according to some embodiments.

[0009] Figures 4A to 4D , Figures 5A to 5B , Figures 6A to 6B , Figures 7A to 7B This is a schematic diagram of an IC layout according to some embodiments.

[0010] Figures 8A to 8C This is a flowchart of various methods according to some embodiments.

[0011] Figure 9A picture, Figure 9C , Figure 9E For the circuit diagrams of various units according to some embodiments, and Figure 9B , Figure 9D , Figure 9F The figure shows some embodiments. Figure 9A , Figure 9C , Figure 9E The corresponding layout of the middle unit.

[0012] Figure 10 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0013] Figure 11 This is a block diagram of an IC device manufacturing system according to some embodiments, and the associated IC manufacturing process. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, materials, values, steps, configurations, etc., are also considered. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Source / drain may refer to a source or a drain, and may be referred to individually or jointly depending on the context.

[0015] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the integrated circuit device in use or operation, in addition to those shown in the figures. The integrated circuit device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein will be interpreted accordingly.

[0016] To generate an integrated circuit layout for an integrated circuit device, cells are read from one or more cell libraries and placed in multiple columns (sometimes referred to as "cell columns") of the integrated circuit layout, for example, using an Automated Placement and Routing (APR) tool or system. In some embodiments, these columns have the same height (sometimes referred to as "column height"); however, at least one column has a different metal pattern configuration (sometimes referred to as "metal scheme") than at least another column. This arrangement is sometimes referred to as a "hybrid column configuration." For example, in at least one embodiment, one column has more metal layer conductor tracks, while another column has the same height but fewer identical metal layer conductor tracks. In at least one embodiment, columns with more tracks are suitable for complex cells, such as those with a greater than predetermined number of interconnects, because when more tracks are available, the internal winding of the complex cells becomes simpler and / or more efficient. In at least one embodiment, columns with fewer tracks are suitable for non-complex cells, such as cells with no more than a predetermined number of interconnects, because fewer tracks allow for increased conductor width and / or spacing between conductors, correspondingly reducing resistance and / or capacitance (hereinafter “RC”), correspondingly improving performance (or speed), and correspondingly reducing IR drop (voltage drop).

[0017] In contrast, other methods use the same number of tracks for the metal layers in all columns of the same height. Therefore, in other methods, when the number of tracks is high, the performance of non-complex cells may be hampered due to reduced conductor width and / or spacing; while when the number of tracks is low, internal winding of complex cells may become difficult and / or inefficient. Hybrid column configurations according to some embodiments provide an improvement over other methods by simultaneously achieving efficient internal winding of complex cells and performance improvements for non-complex cells. In some embodiments, the hybrid column configuration includes columns with two or more different metal pattern configurations, each corresponding to two or more levels of cell complexity, to enhance the balance between internal winding efficiency and performance across various cell complexity levels. Further features and their corresponding advantages according to various embodiments are also described herein.

[0018] Figure 1A This is a block diagram of an integrated circuit device 100A according to some embodiments.

[0019] exist Figure 1AIn this embodiment, integrated circuit device 100A includes components such as macro 101. In some embodiments, macro 101 includes one or more of memory, power grids, one or more cells, inverters, latches, buffers, and / or any other type of circuit configuration that can be digitally represented in a cell library. In some embodiments, macro 101 is understood in the context of an architectural hierarchy simulating modular programming, where a subroutine / program is called by a main program (or other subroutines) to perform a given computational function. In this context, integrated circuit device 100A uses macro 101 to perform one or more given functions. Therefore, in this context and in terms of architectural hierarchy, integrated circuit device 100A is analogous to a main program, and macro 101 is analogous to a subroutine / program. In some embodiments, macro 101 is a software macro. In some embodiments, macro 101 is a hardware macro. In some embodiments, macro 101 is a software macro described digitally in register-transferlevel (RTL) code. In some embodiments, macro 101 has not been composited, placed, and routed, allowing the software macro to be composited, placed, and routed for various process nodes. In some embodiments, macro 101 is a hardware macro described digitally in a binary file format (e.g., Graphic Database System II (GDSII) stream format), wherein the binary file format represents the planar geometry, text labels, other information, and similar information of one or more layout diagrams of macro 101 in a hierarchical manner. In some embodiments, macro 101 has been composited, placed, and routed, making the hardware macro dedicated to a specific process node.

[0020] Macro 101 includes a circuit region 103, which includes columns of semiconductor devices arranged in a hybrid column configuration as described herein. In some embodiments, the circuit region 103 includes a substrate on which circuitry is formed in a front-end-of-line (FEOL) fabrication process. Furthermore, above and / or below the substrate, the circuit region 103 includes various metal layers stacked above and / or below an insulating layer in a back-end-of-line (BEOL) fabrication process. The back-end process provides wiring for the circuitry of the integrated circuit device 100A, including macro 101 and circuit region 103.

[0021] Figure 1B , Figure 1C This is a schematic diagram showing the arrangement of unit 100B at different levels according to some embodiments. Figure 1B This is a schematic diagram of the semiconductor device in the cell 100B layout. Figure 1CThis is a schematic diagram of the metal layer above the semiconductor device in the layout of cell 100B. In some embodiments, cell 100B corresponds to... Figure 1A The circuitry in circuit area 103. In at least one embodiment, the layout of cell 100B is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium.

[0022] exist Figure 1B , Figure 1C In the example configuration, unit 100B is an inverter, and its circuit diagram is as follows: Figure 9A This is merely an example; other units are also within the scope of various embodiments. Examples of units include, but are not limited to, logic gate units, memory cells, or the like. Examples of logic gate units include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI), OR-AND-Invert (OAI), multiplexers (MUX), flip-flops, buffers, latches, delay units, frequencies, or the like. Examples of memory cells include, but are not limited to, static random access memory (SRAM), dynamic random access memory (DRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), read-only memory (ROM) units, or other unit types capable of having multiple states representing logical values. Figure 1B , Figure 1C In the example configuration, unit 100B is an inverter with a drive strength of 1. Other drive strengths, such as 2, 4, 6, or the like, are within the scope of various embodiments. For example, Figure 9B An inverter with a drive strength of 4 is described.

[0023] Reference Figure 1B Unit 100B includes a first active region and a second active region, at least one gate region extending across the active regions, and a boundary within which the active regions and at least one gate region are arranged. For example, unit 100B includes active regions 101 and 102, gate region 110, and boundary 120.

[0024] Active regions 101 and 102 extend along a first axis (i.e., the X-axis). Active regions are sometimes referred to as oxide-definition (OD) regions and are schematically shown in the figures marked "OD". In an integrated circuit device including cell 100B according to at least one embodiment, active regions 101 and 102 are located above a first or front side of the substrate, as described herein. Active regions 101 and 102 include P-type dopants and / or N-type dopants to form one or more circuit components or semiconductor devices. Examples of circuit components include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field effect transistors (PFETs / NFETs), fin field-effect transistors (FinFETs), planar metal oxide semiconductor transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, or the like. The active region used to form one or more PMOS devices therein is referred to herein as a "PMOS active region." The active region used to form one or more NMOS devices therein is referred to herein as an "NMOS active region." In the embodiments described herein, a PMOS active region may be replaced by an NMOS active region, and vice versa.

[0025] Gate region 110 extends across active regions 101, 102 along a second axis (i.e., the Y-axis), which is transverse to the X-axis. In at least one embodiment, the Y-axis is perpendicular to the X-axis. Gate region 110 comprises a conductive material, such as polysilicon, and is schematically shown in the figures with the label “PO”. Other conductive materials for the gate region, such as metals, are available in various embodiments.

[0026] exist Figure 1BIn the illustrated configuration, active region 101 is a PMOS active region, used to form transistor P0 of an inverter together with gate region 110. Active region 102 is an NMOS active region, used to form transistor N0 of an inverter together with gate region 110. Specifically, active region 101 includes source / drain regions 103 and 105 on the opposite side of the first portion of gate region 110, the first portion of gate region 110 extending beyond active region 101. Active region 102 includes source / drain regions 104 and 106 on the opposite side of the second portion of gate region 110.

[0027] Boundary 120 includes boundaries 121, 122, 123, and 124 connected together to form a closed boundary. In the placement and routing operation described herein (also known as "automated placement and routing" (APR)), cells are placed in an integrated circuit layout so that they are adjacent to each other on their respective boundaries. For example, cell 100B is placed adjacent to one or more other cells along the X-axis at one or more boundaries 121, 123. Additionally or alternatively, cell 100B is placed adjacent to one or more other cells along the Y-axis at one or more boundaries 122, 124. Boundary 120 is sometimes referred to as a "placement and routing boundary" and is schematically illustrated in the diagram with the numeral "prBoundary". Boundaries 121, 122, 123, and 124 of boundary 120 are sometimes referred to as boundary lines. Figure 1B In the exemplary configuration, boundary 120 has a rectangular shape, with boundaries 121 and 123 parallel to the Y-axis and boundaries 122 and 124 parallel to the X-axis. Other configurations are within the scope of various embodiments. For example, in one or more embodiments, boundary 120 has a shape other than a rectangle, and / or one or more boundaries of boundary 120 are not perpendicular to the X-axis and Y-axis.

[0028] Unit 100B further includes dummy gate regions 118, 119 along corresponding boundaries 121, 123 of boundary 120. In at least one embodiment, the centerline of the dummy gate regions 118, 119 coincides with the corresponding boundaries 121, 123 of boundary 120. Gate region 110 is an example of a "functional gate region," which, together with its underlying active region, configures a transistor and / or electrically couples it to one or more other circuit components. Unlike functional gate regions, dummy gate regions or non-functional gate regions are not configured to form a transistor together with their underlying active regions, and / or the one or more transistors formed by the dummy gate region and its underlying active region are not electrically coupled to other circuit components. In at least one embodiment, the dummy gate region includes dielectric material in the manufactured integrated circuit device. The dummy gate regions and functional gate regions are arranged along the X-axis at the same spacing CPP (i.e., center-to-center distance). During placement and wiring operations, when cell 100B is placed adjacent to other cells, the dummy gate regions 118, 119 along boundaries 121, 123 of boundary 120 are merged with the corresponding dummy gate regions of other cells. Other configurations are within the scope of various embodiments. For example, in one or more embodiments, one or more boundaries 121, 123 of boundary 120 are not arranged along dummy gate regions 118, 119.

[0029] The configuration of unit 100B, comprising two active regions 101 and 102 directly adjacent along the Y-axis, is one example. Other units in various embodiments include other numbers of active regions arranged along the Y-axis. When there are no other active regions between two active regions, the two active regions are directly adjacent along the Y-axis. Figure 1B In the exemplary configuration, each of the active regions 101, 102 has opposite boundaries (unlabeled) along the X-axis, which are spaced inward from the corresponding boundaries 121, 123 of boundary 120. Other configurations are within the scope of various embodiments. For example, in one or more embodiments, the active regions 101, 102 have opposite boundaries along the X-axis, which coincide with the corresponding boundaries 121, 123 of boundary 120. Cell 100B includes a functional gate region 110. This is an example; other cells in various embodiments include multiple functional gate regions.

[0030] Cell 100B has a height (or cell height) H, which is the distance along the Y-axis between boundaries 122 and 124 of boundary 120. Each of active regions 101 and 102 has a width W_OD along the Y-axis, sometimes referred to as the "active region width". In some embodiments, the active region width W_OD is predetermined by and depends on the corresponding cell height H and one or more design rules. One design rule example is a predetermined minimum spacing S_OD along the Y-axis between directly adjacent active regions. Another design rule example is a predetermined minimum spacing Sx along the Y-axis between an active region and the nearest boundary (or boundary line) of boundary 120. For example, as... Figure 1B As shown, the spacing S_OD is located between the relative boundaries of directly adjacent active regions 101 and 102, and the spacing Sx is located between the relative boundary of boundary line 122 and active region 101 (i.e., Figure 1B Between the upper boundary of the boundary line 124 and the active region 102, the spacing Sx is also located at the relative boundary of the boundary line 124 and the active region 102 (i.e., the upper boundary of the boundary line 124 and the active region 102). Figure 1B Between the lower boundary of the active regions (H and S). In some embodiments, S_OD = 2Sx. Other design rules are within the scope of various embodiments. In some embodiments, given a cell height H, W_OD is the maximum active region width of active regions 101 and 102 when all design rules are satisfied.

[0031] Unit 100B further includes a contact structure above and electrically in contact with the corresponding source / drain regions in the active regions 101 and 102. This contact structure is sometimes referred to as a metal-to-device structure and is schematically illustrated in the diagram under the numeral "MD". The MD contact structure includes conductive material formed above the corresponding source / drain regions in the respective active regions to define electrical connections from one or more devices formed in the active regions to other circuitry. Figure 1BIn the exemplary configuration, MD contact structures 135 and 136 are above and electrically contacting the respective source / drain regions 103 and 104, and MD contact structure 137 extends continuously along the Y-axis to be above and electrically contacting the respective source / drain regions 105 and 106. MD contact structure 137 is electrically coupled to the source / drain regions 105 and 106. MD contact structure 137 is an example of an extended contact structure extending above multiple active regions. In some embodiments, the extended contact structure is electrically contacting all the active regions below it. In one or more embodiments, the extended contact structure is electrically contacting at least one of the underlying active regions, while traversing the other underlying active regions without making electrical contact with them. MD contact structures and gate regions (including functional gate regions and dummy gate regions) are arranged alternately along the X-axis. The spacing between directly adjacent MD contact structures (i.e., the center-to-center distance along the X-axis) is the same as the spacing CPP between directly adjacent gate regions. When there are no other gate regions (including functional gate regions and / or dummy gate regions) between two gate regions (including functional gate regions and / or dummy gate regions), the two gate regions are considered to be directly adjacent along the X-axis. When there are no other MD contact structures between two MD contact structures, the two MD contact structures are considered to be directly adjacent. Example conductive materials for MD contact structures include metals. Other configurations are within the scope of various embodiments.

[0032] Unit 100B further includes a via electrically contacting the corresponding gate region or MD contact structure above and to the corresponding gate region or MD contact structure. The via electrically contacting the MD contact structure above and to the MD contact structure is sometimes referred to as a via-to-device (VD). The via electrically contacting the gate region above and to the gate region is sometimes referred to as a via-to-gate (VG). VD and VG vias are schematically illustrated in the figures using the reference numerals "VD / VG". Figure 1B and Figure 1C In the exemplary configuration, VG via 131 is above and electrically contacts the gate region 110, and VD vias 132, 133, and 134 are above and electrically contacts the MD contact structures 135, 136, and 137, respectively. The exemplary materials for the VD and VG vias include metals. Other configurations are within the scope of various embodiments.

[0033] Unit 100B further includes one or more metal layers and via layers arranged sequentially and alternately on the VD and VG vias. The lowest metal layer directly above and electrically connected to the VD and VG vias is the metal-zero (M0) layer. In other words, the M0 layer is the lowest metal layer above the active regions 101 and 102 on the front side of the substrate, or the metal layer closest to the active regions 101 and 102 on the front side of the substrate. The next metal layer directly above the M0 layer is the metal-one (M1) layer or similar. The conductor in the M0 layer is referred to herein as the M0 conductor, and the conductor in the M1 layer is referred to herein as the M1 conductor, or similar. The via layer Vn is disposed between the Mn layer and the Mn+1 layer and electrically coupled to the Mn layer and the Mn+1 layer, where n is an integer of zero or higher. For example, the via-zero (V0) layer is the bottommost via layer disposed between and electrically coupled to layers M0 and M1. Other via layers are V1, V2, or similar. The metal layers (such as M0, M1, or similar) and via layers (such as V0, V1, or similar) on the front side of the substrate are referred to herein as the front metal layer and the front via layer.

[0034] Reference Figure 1C Unit 100B includes M0 conductors 141, 142, 143, and 144 along tracks M0_1, M0_2, M0_3, and M0_4 in the M0 layer. The M0 conductors 141, 142, 143, and 144 are configured to transmit signals, such as data, control, frequency, or similar signals, between various circuit components of the integrated circuit device, and are sometimes referred to as signal conductors. The tracks M0_1, M0_2, M0_3, and M0_4 along which the M0 conductors 141, 142, 143, and 144 are arranged are sometimes referred to as signal tracks.

[0035] Unit 100B further includes M0 conductors 140 and 145 along tracks M0_VSS and M0_VDD in the M0 layer. M0 conductors 140 and 145 are configured to supply power to various circuit components of the integrated circuit device and are sometimes referred to as power rails. For example, power rail 140 is configured to supply a reference voltage, i.e., ground voltage VSS, and is sometimes referred to as the VSS power rail. Power rail 145 is configured to supply a positive power supply voltage, such as VDD, and is sometimes referred to as the VDD power rail. The tracks M0_VSS and M0_VDD along which power rails 140 and 145 are arranged are sometimes referred to as power rails. Signal rails and power rails in the M0 layer are sometimes collectively referred to as M0 rails.

[0036] In some embodiments, power rails 140, 145 extend continuously along the X-axis across multiple cells in a circuit region (e.g., circuit region 103) to supply VDD and VSS to these multiple cells. In some embodiments, multiple power rails extend along the X-axis and are arranged side-by-side along the Y-axis across a circuit region of an integrated circuit device to configure a power grid to power circuit components in said circuit region. In at least one embodiment, the VDD power rail and VSS power rail in the power grid are arranged alternately along the Y-axis. In some embodiments, as described herein, a pair of adjacent power rails define a row of semiconductor devices between them. When there are no other power rails (or power rails) between two power rails (or power rails), they are adjacent along the Y-axis. Power rails 140, 145 are examples of adjacent power rails, and power rails M0_VSS, M0_VDD are examples of adjacent power rails. Similarly, when there are no other signal rails between two signal rails, they are adjacent along the Y-axis. Furthermore, when there are no other M0 rails between two M0 rails along the Y-axis, they are adjacent.

[0037] Tracks M0_VSS, M0_1, M0_2, M0_3, M0_4, M0_VDD and their corresponding M0 conductors 140-145 extend along the X-axis and are spaced apart from each other along the Y-axis. Figure 1C In the exemplary configuration, tracks M0_VSS, M0_1, M0_2, M0_3, M0_4, and M0_VDD coincide with the center lines of the corresponding M0 conductors 140-145. Furthermore, tracks M0_VSS and M0_VDD coincide with boundary lines 124 and 122, respectively. This described coincidence is an example; other configurations are also within the scope of various embodiments.

[0038] In at least one embodiment, all M0 conductors extend or lengthen in the same direction, for example, along the X-axis but not along the Y-axis. In some embodiments, the M0 conductors in the M0 layer belong to the same photomask. In at least one embodiment, the M0 conductors in the M0 layer are separated into several photomasks to meet one or more design and / or manufacturing requirements. For example, M0 conductors 140, 142, and 144 belong to one photomask, schematically indicated in the figure by the label "M0_A," while M0 conductors 141, 143, and 145 belong to another photomask, schematically indicated in the figure by the label "M0_B." The number of four signal tracks M0_1, M0_2, M0_3, and M0_4 between a pair of adjacent power rails M0_VSS and M0_VDD is one example. As described herein, other configurations are also within the scope of various embodiments.

[0039] exist Figure 1CIn the exemplary configuration, each of the M0 conductors 141, 142, 143, and 144 extends toward boundaries 121 and 123 of boundary 120, but still maintains an inward spacing. In other words, the M0 conductors 141, 142, 143, and 144 are completely disposed within boundary 120. For example, the right boundaries (unlabeled) of the M0 conductors 141, 142, 143, and 144 are adjacent to but inwardly spaced from boundary 121 of boundary 120, while the left boundaries (unlabeled) of the M0 conductors 141, 142, 143, and 144 are adjacent to but inwardly spaced from boundary 123 of boundary 120. This configuration is an example, and other configurations are also within the scope of various embodiments. Power rails 140 and 145 extend to boundaries 121 and 123 of boundary 120. This configuration corresponds to the described configuration where power rails 140 and 145 continuously span multiple units.

[0040] M0 conductor 140 overlaps and is electrically coupled to VD via 133, and is therefore electrically coupled to the source / drain region 136 through VD via 133. M0 conductor 141 overlaps and is electrically coupled to VD via 134, and is therefore electrically coupled to the source / drain region 137 through VD via 134. M0 conductor 142 overlaps and is electrically coupled to VG via 131, and is therefore electrically coupled to the gate region 110 through VG via 131. M0 conductor 145 overlaps and is electrically coupled to VD via 132, and is therefore electrically coupled to the source / drain region 135 through VD via 132. M0 conductors 141 and 142 correspond to the output and input of the inverter corresponding to cell 100B. M0 conductors 143 and 144 are floating M0 conductors. In some embodiments, at least one of the M0 conductors 143 and 144 is omitted.

[0041] M0 conductors 141 and 142 are examples of internal wiring within a cell. In at least one embodiment, the internal wiring of a cell includes conductors in one or more metal layers and / or vias in one or more via layers, all included in the cell layout and configured to electrically couple various circuit components or semiconductor devices within the cell to the cell's internal circuitry, and / or form one or more inputs and / or outputs of the cell to electrically couple the cell's internal circuitry to circuitry outside the cell, such as to other cells including integrated circuit devices. For simple cells, such as cell 100B corresponding to an inverter, two M0 conductors are sufficient for internal wiring. For more complex cells, such as flip-flops, a greater number of M0 conductors and / or M0 tracks are used. In some embodiments, for the internal wiring of complex cells, the M0 conductors are divided into several M0 conductors (not shown in the original text). Figure 1C As shown in the diagram, these Mo conductors are spaced apart from each other along the X-axis and electrically isolated. In other words, in one or more embodiments, several Mo conductors are arranged along the same Mo orbit. An example of several Mo conductors arranged along the same Mo orbit is shown in... Figure 9D As described in the document. In some embodiments, the internal wiring of the cell is accomplished solely by the M0 conductor, without the need for one or more conductors in higher metal layers (such as M1, M2, etc.). In some embodiments, the internal wiring of the cell includes not only the M0 conductor, but also one or more conductors in one or more higher metal layers, and one or more vias in one or more corresponding via layers.

[0042] Each M0 conductor 140, 141, 142, 143, 144, 145 has a width (sometimes referred to as "metallic linewidth") along the Y-axis. Figure 1C In the illustrated configuration, the M0 conductors 141, 142, 143, and 144, which serve as signal conductors, have a metal linewidth W, while the M0 conductors 140 and 145, which serve as power rails, have a metal linewidth W_PG. The metal linewidth of the power rail is sometimes referred to as the power rail width. The metal linewidth W of the signal conductors is smaller than the metal linewidth W_PG of the power rails. In some embodiments, as described herein, one or more signal conductors in a unit may have a larger metal linewidth than one or more other signal conductors in the same unit.

[0043] Adjacent M0 conductors, i.e., M0 conductors along a pair of adjacent M0 tracks, are spaced apart by a metal pitch S in the Y-axis direction. The metal pitch S is equal to or greater than a minimum metal pitch, a predetermined design rule that must be met to ensure the manufacturability of the integrated circuit device including the unit. In at least one embodiment, the metal pitch S is equal to the minimum metal pitch. The sum of the metal linewidths of the M0 conductors in the unit and the sum of the metal pitches between the M0 conductors equals the unit height H. Figure 1C In the example configuration shown, H = W_PG + 4W + 5S. Other configurations are also within the scope of various embodiments. For example, in some embodiments, as described herein, the metallic spacing S between adjacent M0 conductors is greater than the minimum spacing.

[0044] In some embodiments, the metal patterning configuration of the metal layer above the cell includes the number of tracks above the cell, one or more metal linewidths of conductors along the tracks, one or more metal spacings between conductors, and one or more sizes of vias coupled to the conductors. In at least one embodiment, the number of tracks above the cell corresponds to the number of signal tracks above the cell. For example, the metal patterning configuration of the M0 layer above the cell includes the number of M0 tracks above the cell, one or more metal linewidths of M0 conductors along the tracks, and one or more metal spacings between M0 conductors. In one or more embodiments, by changing one or more aspects of the metal patterning configuration of the metal layer, such as the number of tracks, metal linewidths, and metal spacing, a desired balance between wiring efficiency and performance can be achieved in cells of varying complexity, as described herein. Several M0 layer metal patterning configurations according to one or more embodiments are described herein. The one or more metal patterning configurations described herein are applicable to other metal layers, such as metal layers on the front side above the M0 layer, and / or the back metal layers described herein.

[0045] Figure 2 This is a schematic cross-sectional view of a circuit region of an integrated circuit device 200 according to some embodiments. In some embodiments, Figure 2 The circuit area in the document corresponds to circuit area 103, and / or includes one or more circuit areas of units placed and wired as described herein. In at least one embodiment, Figure 2 The units placed and wired within the middle circuit area correspond to unit 100B and / or one or more units described herein.

[0046] like Figure 2 As shown, the integrated circuit device 200 includes a substrate 260 on which circuit components and structures corresponding to one or more units described herein are formed. The substrate 260 has a first side 261 and a second side 262 that are opposite to each other along the thickness direction of the substrate 260 (i.e., along the Z-axis). In at least one embodiment, the first side 261 is referred to as the “upper side” or “front side” or “device side,” while the second side 262 is referred to as the “lower side” or “back side.” In at least one embodiment, the substrate 260 includes silicon, silicon germanium (SiGe), gallium arsenide, or other suitable semiconductor or dielectric materials.

[0047] The integrated circuit device 200 further includes N-type and P-type doping, which are added to the substrate 260 to correspondingly form NMOS active regions and PMOS active regions. The NMOS and PMOS active regions form corresponding active regions and are arranged and schematically clustered in... Figure 2 The term "OD" is designated in this context. In some embodiments, the isolation structure is formed between adjacent active regions. For simplicity, the isolation structure is... Figure 2 The term is omitted. In at least one embodiment, Figure 2 The active area in the middle corresponds to Figure 1B One or more active regions 101, 102 as described in the document.

[0048] The integrated circuit device 200 further includes various gate structures over active regions on a front side 261 and a back side 262. For example, a gate structure includes a gate portion 211 on the front side 261 and a gate portion 212 integral with the gate portion 211 and on the back side 262. Another gate structure includes a gate portion 213 on the front side 261 and a gate portion 214 integral with the gate portion 213 and on the back side 262. Yet another gate structure includes a gate portion 215 on the front side 261 and a gate portion 216 integral with the gate portion 215 and on the back side 262. This described configuration is referred to as a “gate-all-around”. Other configurations are also within the scope of various embodiments. For example, in at least one embodiment, the gate structure is formed over the active region on the front side 261 but not on the back side 262. One or more gate dielectric layers (not shown) are located between the active region and the corresponding gate structure. Examples of materials for the gate dielectric layers include hafnium dioxide (HfO2), zirconium dioxide (ZrO2), or the like. Examples of materials for the gate structure include polysilicon, metal, or the like. In some embodiments, at least one of the gate structures 211-216 corresponds to the functional gate region 110, and / or at least another of the gate structures 211-216 corresponds to, for example, a functional gate region 110. Figure 1B The dummy gate region 118 or 119 is described. In at least one embodiment, the gate structure corresponding to the dummy gate region includes a dielectric material.

[0049] The integrated circuit device 200 further includes MD contact structures for electrically coupling the source / drain regions of various transistors in the active region to other circuit components. For example, MD contact structures 231-234 are illustrated in... Figure 2 In some embodiments, at least one of the MD contact structures 231-234 corresponds to, as shown in the figure. Figure 1B One of the MD contact structures 135 to 137.

[0050] The integrated circuit device 200 further includes a VD via and a VG via, which are respectively located above and electrically contacted with the MD contact structure and the gate structure. For example, as Figure 2 As shown, the VG via 241 is located above and electrically contacts the gate portion 211 of the corresponding gate structure, while the VD via 242 is located above and electrically contacts the MD contact structure 233. In some embodiments, such as Figure 1BThe VG via 241 corresponds to the VG via 131, and / or the VD via 242 corresponds to one of the VD vias 132, 133, and 134.

[0051] The integrated circuit device 200 further includes an interconnect structure 268 on the front side 261. The interconnect structure 268, above the VD and VG vias, includes multiple metal layers M0, M1… and multiple via layers V0, V1…, alternately arranged in the thickness direction of the substrate 260 (i.e., along the Z-axis). The interconnect structure 268 further includes various interlayer dielectric (ILD) layers (not shown or labeled), with the metal layers and via layers embedded within the interlayer dielectric layers. The metal layers and via layers of the interconnect structure 268 are used to electrically couple various components or circuits of the integrated circuit device 200 to each other and to external circuits. For simplicity, the metal layers and via layers above the M1 layer… Figure 2 The middle part is omitted.

[0052] For example, the M0 layer includes M0 conductors 243 and 244, which are respectively located above and electrically contacted with the VG via 241 and VD via 242. In some embodiments, such as Figure 1B As described, at least one of the M0 conductors 243 and 244 corresponds to at least one of the M0 conductors 140 to 145. The V0 layer includes V0 vias 245 and 246, which are correspondingly located above and electrically contacted by the M0 conductors 243 and 244. The M1 layer includes M1 conductors 247 and 248, which are correspondingly located above and electrically contacted by the V0 vias 245 and 246. In at least one embodiment, the M0 conductors provide internal wiring for the cell, while the V0 vias, M1 conductors, and / or one or more higher via layers and metal layers provide electrical connections from other cells of the integrated circuit device 200 to said cell. Other configurations are also within the scope of various embodiments.

[0053] The integrated circuit device 200 further includes a back-side interconnect structure 269 on a back-side surface 262. The back-side interconnect structure 269 includes at least one back-side metal layer, such as a back-side-metal-zero (BMO) layer below the back-side surface 262 of the substrate 260. On the back-side surface 262 of the substrate 260, the BMO layer is the uppermost metal layer below the active region of the integrated circuit device 200 or the source / drain of a transistor, or the metal layer closest to the active region of the integrated circuit device 200 or the source / drain of a transistor. In at least one embodiment, the integrated circuit device 200 includes one or more distal via layers, dielectric layers, and metal layers (not shown) below the BMO layer to form interconnects among circuit components of the integrated circuit device 200 and / or to form electrical connections to external circuitry. The via layers and metal layers from and below the BMO layer are sometimes referred to as back-side via layers and back-side metal layers. Exemplary materials for back-side via layers and back-side metal layers include metals. Other configurations are within the scope of various embodiments. For simplicity, the dielectric layer below BM0, the back via layer, and the back metal layer are... Figure 2 The middle part is omitted.

[0054] exist Figure 2 In the illustrated configuration, the BMO layer includes a BMO conductor 251 located below and electrically contacting a back-side VD (BVD) via 253, which in turn is located below and electrically contacting an active region on the back side 262. The BMO layer further includes a BMO conductor 252 located below and electrically contacting a back-side VG (BVG) via 254, which in turn is located below and electrically contacting a gate portion 216 of a corresponding gate structure. In some embodiments, as described herein, at least one of the BMO conductors 251 and 252 is configured as a signal conductor or power rail of the unit. For example, in one or more embodiments, the integrated circuit device 200 includes a power rail configured by a BMO conductor on the back side, which frees up the MO rails and MO conductors on the front side for signaling. In other words, as... Figure 1C The power rails 140, 145, etc., are moved to the back side. In at least one embodiment, the BMO conductor includes a signal conductor and a power rail. In some embodiments where the gate structure is not formed below the active region, gate portions 212, 214, 216 and the corresponding BVG vias are omitted. In some embodiments, the BVD via is omitted.

[0055] In some embodiments, the example procedure for designing an integrated circuit device uses one or more electronic design automation (EDA) tools to generate, optimize, and / or verify the integrated circuit device design before and / or after manufacturing the integrated circuit device. In the integrated circuit device design generation operation, the integrated circuit device design is provided by a circuit designer. In some embodiments, the integrated circuit device design includes an integrated circuit device schematic, i.e., a circuit diagram of the integrated circuit device. In subsequent cell placement and routing operations, an integrated circuit device layout is generated based on the integrated circuit device schematic. In at least one embodiment, the cell placement and routing operation is referred to as Automatic Placement and Routing (APR). In at least one embodiment, the integrated circuit device layout is generated by an EDA tool, such as an APR tool. Example operations of the APR tool include, but are not limited to, cell placement and routing operations. In the cell placement operation, the APR tool performs cell placement. Cells used to provide predefined functionality and having a pre-designed layout are stored in one or more cell libraries. The APR tool retrieves various cells from one or more cell libraries and places the cells in an adjacency or proximity manner to generate an integrated circuit device layout corresponding to the integrated circuit device schematic. In the routing operation, the APR tool performs routing to route various networks that interconnect the placed circuit components. Routing is performed to ensure that the routed interconnects or networks meet a set of constraints. After the routing operation, the APR tool outputs an integrated circuit device layout diagram including the placed circuit components and the routing network. In some embodiments, one or more verifications are performed after cell placement and routing operations. If one or more verifications fail, the integrated circuit device diagram and / or integrated circuit device layout diagram is revised and / or redesigned. If the verification passes, an integrated circuit device layout diagram is output for manufacturing integrated circuit devices based on the integrated circuit device layout diagram.

[0056] Some embodiments described herein pertain to an automated placement and routing (APR) operation in which cells and cell columns having different metal pattern configurations within the same metal layer are used in the placement operation. This document describes several metal pattern configurations for a metal 0 (M0) layer according to one or more embodiments. However, other metal layers with different metal pattern configurations are also within the scope of various embodiments. For example, one or more metal pattern configurations described herein are applicable to other metal layers, such as metal layers on the front side above the metal 0 (M0) layer, and / or back metal layers, such as a backside metal 0 (BM0) layer or a lower back metal layer.

[0057] Figures 3A-3GThis is a schematic diagram of circuit regions of one or more integrated circuit devices according to some embodiments, corresponding to integrated circuit layouts 300A-300G. In some embodiments, at least one circuit region represented by integrated circuit layouts 300A-300G corresponds to circuit region 103, and / or includes one or more units placed and routed as described herein. In at least one embodiment, at least one integrated circuit device including such circuit regions corresponds to integrated circuit device 200. In some embodiments, integrated circuit layouts 300A-300G and other integrated circuit layouts described herein with respect to various embodiments are generated by an electronic design automation (EDA) system, such as an automatic place and route (APR) system, and / or stored in a non-transitory computer-readable storage medium. The description herein of integrated circuit layouts 300A-300G and other integrated circuit layouts conforming to various embodiments is applicable to integrated circuit devices including circuit regions corresponding to the described integrated circuit layouts. For simplicity, Figures 3A-3G The corresponding components are identified by the same reference numerals, and several features, such as active regions and placed cells, are omitted in figures 3B–3G. The integrated circuit layouts 300A–300G feature various hybrid column configurations, as described herein.

[0058] exist Figure 3A In the diagram, integrated circuit layout 300A includes multiple rows of semiconductor devices. For simplicity, Figure 3A Only columns 311 and 312 are shown, while other columns are omitted. Columns 311 and 312 extend along the X-axis and are arranged side-by-side along the Y-axis. The X-axis is an example of a first axis, and the Y-axis is an example of a second axis perpendicular to the first axis. In at least one embodiment, the semiconductor devices in columns 311 and 312 correspond to... Figure 1B , Figure 2 The semiconductor device or transistor described herein. For example, the semiconductor device in column 311 is a semiconductor device included in units C1, C2, or similar units placed in column 311, while the semiconductor device in column 312 is a semiconductor device included in units C3, C4, or similar units placed in column 312. In at least one embodiment, each of units C1 to C4 corresponds to unit 100B and / or one or more further units described herein. Various features of units C1 to C4, such as active regions, gate regions, metal diffusion (MD) contact structures, gate vias (VG), drain vias (VD), metal O (MO) conductors, or similar structures, become corresponding features in columns 311 and 312 of integrated circuit layout 300A.

[0059] Each column in columns 311 and 312 has a pair of boundary lines that are spaced apart along the Y-axis by a distance corresponding to the column height. For example, column 311 has a pair of boundary lines 301 and 302 with a corresponding height H between them, while column 312 has a pair of boundary lines 302 and 303 with the same corresponding height H between them. Therefore, columns 311 and 312 have the same height (or column height) H, which corresponds to the cell height H of the cells placed in columns 311 and 312. Column 311 is an example of a first column, and column 312 is an example of a second column, and vice versa. In some embodiments, at least one of the boundary lines 301 to 303 corresponds to the centerline of the power rail, as per [reference to...]. Figure 1C As described.

[0060] exist Figure 3A In the exemplary configuration, columns 311 and 312 are in contact with each other and share a common boundary line 302. Other configurations are also within the scope of various embodiments. For example, in at least one embodiment (not shown), two adjacent columns do not share a common boundary line and are separated along the Y-axis by a blank space without semiconductor devices. Such two columns are sometimes referred to as adjacent but not in contact columns. In some embodiments, when two columns share a common boundary line (such as... Figure 3A (As shown) or when two columns are adjacent but not touching columns, the two columns are considered adjacent.

[0061] In one exemplary placement operation, performed, for example, by an automated placement and routing (APR) system, cells are placed in an integrated circuit layout, abutting each other at their respective cell boundaries. For example, along the X-axis, cell C1 is placed abutting cell C2 along a common cell boundary. Along the Y-axis, cell C1 is placed abutting cell C3, and cell C2 is placed abutting cells C3 and C4, along a common cell boundary defined by boundary line 302, which in one or more embodiments is defined by the power rails described herein. Cells are not always placed (or can be placed) in an abutting state. For example, cells C3 and C4 are placed as if separated by a blank space without semiconductor devices along the X-axis. The described placement operation is an example. Other placement operations are also within the scope of various embodiments.

[0062] Each column in columns 311 and 312 includes a first active region of a first conductivity type and a second active region of a second conductivity type different from the first active region, wherein the second active region is separated from the first active region by a distance. For example, as Figure 3AAs illustrated, column 311 includes a first active region 313 of a first conductivity type (e.g., P-type) and a second active region 314 of a second conductivity type (e.g., N-type), while column 312 includes a first active region 315 of a first conductivity type (e.g., P-type) and a second active region 316 of a second conductivity type (e.g., N-type). In some embodiments, active regions 313 and 315 correspond to active region 101, while active regions 314 and 316 correspond to active region 102.

[0063] Each of the active regions 313 to 316 is arranged in a region of a corresponding conductivity type, such as a substrate region, a doped region, or a well region. For example, each of the active regions 313 and 315 is a P-type active region and is arranged in an N-type well region (not shown). In some embodiments, the N-type well region including active region 313 continuously spans boundary line 301 (in Figure 3A Extending upwards from the center into another row of semiconductor devices (not shown), and / or including the N-type well region of the active region 315 continuously across the boundary line 303 (in... Figure 3A The active regions 314 and 316 are N-type active regions and are arranged in a common P-type substrate region (not shown), which extends continuously across the boundary line 302 from column 311 to column 312.

[0064] The integrated circuit layout 300A also includes gate regions (not shown) extending along the Y-axis across active regions 313-316. These gate regions include one or more functional gate regions and / or one or more dummy gate regions. The functional gate regions, together with one or more active regions 313-316, are configured with various semiconductor devices or transistors, as described above. Figure 1B As stated above.

[0065] The integrated circuit layout 300A also includes a metal layer comprising a plurality of conductors arranged on a plurality of tracks extending along a first axis (i.e., the X-axis). Figure 3A In the example configuration, the metal layer is an M0 layer. According to various embodiments, the description herein also applies to other metal layers. Figure 3A In the diagram, the first group of conductors 320-326 are configured according to the first metal pattern arrangement of column 311, and the second group of conductors 326-330 are configured according to a different second metal pattern arrangement of column 312. For illustrative purposes, conductors 320-330 are shown on one side of the corresponding columns 311 and 312. In the actual layout, the conductors extend along the X-axis across columns and cells, as shown in the diagram. Figure 1C For simplicity, conductors and tracks are designated with the same reference numerals. For example, reference numeral "321" is used here to refer to a track and one or more conductors arranged along said track.

[0066] According to the first metal pattern configuration of column 311, there are five tracks 321-325 between two further tracks 320, 326 between the boundary lines 301, 302 of column 311. Tracks 321-325 are signal tracks, along which signal conductors are arranged. The signal conductors are schematically represented in the figure by the label "MO Signal". Tracks 320, 326 are power rails, along which conductors are arranged as power rails. The power rails are schematically represented in the figure by the label "MO PG". In some embodiments, at least one of tracks 320, 326 coincides with a corresponding one of the boundary lines 301, 302 of column 311. The signal conductors 321-325 along the signal tracks have the same metal linewidth W1. The power rails 320, 326 along the power rails have the same power rail width W_PG1. The signal conductors 321-325 are spaced apart from each other and / or from one of the adjacent power rails 320, 326 by a metal pitch S1. In some embodiments, one or more of the metal line width W1, power rail width W_PG1, and metal spacing S1 correspond to the information about Figure 1C The metal linewidth W, the power rail width W_PG, and the metal spacing S are one or more of these. In at least one embodiment, the metal spacing S1 is equal to the minimum metal spacing.

[0067] According to the second metal pattern configuration of column 312, there are three tracks 327-329 between the two further tracks 326 and 330 between the boundary lines 302 and 303 of column 312. Tracks 327-329 are signal tracks along which signal conductors are arranged. Tracks 326 and 330 are power rails along which conductors are arranged as power rails. In some embodiments, at least one of tracks 326 and 330 coincides with a corresponding one of the boundary lines 302 and 303 of column 312. The signal conductors 327-329 along the signal tracks have the same metal linewidth W2. The power rails 326 and 330 along the power rails have the same power rail width W_PG1. The signal conductors 327-329 are spaced apart from each other and / or from one of the adjacent power rails 326 and 330 by a metal pitch S2. In some embodiments, one or more of the metal linewidth W2, the power rail width W_PG1, and the metal pitch S2 correspond to the following about Figure 1C The metal linewidth W, the power rail width W_PG, and the metal spacing S are one or more of these. Figure 3A In the example configuration, W2>W1, and S2>S1.

[0068] As described, the metal pattern configuration of column 312 differs from that of column 311 at least in the number of tracks in the column, the metal linewidth, and the metal spacing. The hybrid column configuration of the described integrated circuit layout 300A, comprising five tracks in column 311 and three tracks in column 312, is merely one example. Other numbers of tracks in columns are also within the scope of various embodiments.

[0069] In a hybrid column configuration of integrated circuit layout 300A, according to some embodiments, complex cells are configured or designed based on a metal pattern configuration of column 311 and placed in column 311 for efficient internal wiring, while non-complex cells are configured or designed based on a metal pattern configuration of column 312 and placed in column 312 for improved performance. In some embodiments, complex cells have a higher number of interconnects, while non-complex cells have a lower number of interconnects. For example, complex cells have more than a predetermined number of interconnects, while non-complex cells have no more than a predetermined number of interconnects. In at least one embodiment, the interconnects of a cell include interconnects for internal connections and interconnects for external connections. Interconnects for internal connections (or internal interconnects of a cell) include interconnects between various semiconductor devices or transistors of the cell. Interconnects for external connections include at least one input and at least one output of the cell. In at least one embodiment, to determine cell complexity, interconnects in a metal layer (such as an MO layer) are considered, while interconnects through metal contact structures or through adjacent transistors sharing a source / drain region are ignored. In at least one embodiment, a cell with more than five interconnects is considered a complex cell, while a cell with five or fewer interconnects is considered a non-complex cell. Other thresholds or interconnection numbers used to distinguish between complex and non-complex units are also within the scope of various embodiments. In some embodiments, more than two levels of unit complexity are employed, such as complex units, intermediate units, and simple units. Examples of complex units include, but are not limited to, inverters, latches, multiplexers, full adders, etc. Examples of non-complex units, such as simple units and / or intermediate units, include, but are not limited to, inverters, buffers, NAND gates, NOR gates, AND gates, OR gates, AOIs, etc. Several non-limiting examples are provided below. Figure 9A , 9C 9E and / or Figure 9B , 9D It is described in 9F.

[0070] As described herein, in some embodiments, complex cells configured based on the metal patterning of column 311 are placed in column 311. The number of tracks in column 311 is high enough to accommodate a large number of interconnects of complex cells and enables simplified or efficient internal routing of complex cells. In some embodiments, the sufficiently high number of tracks in column 311 allows the internal routing of complex cells to be completed within a single metal layer (e.g., M0 layer) without requiring the additional resources of one or more other layers (e.g., higher metal layers and / or via layers).

[0071] On the other hand, uncomplex cells with fewer interconnects can achieve internal wiring using fewer tracks. Therefore, in some embodiments, uncomplex cells configured based on a metal patterning configuration of column 312 are placed in column 312, which has fewer tracks than column 311. The fewer tracks in column 312 allow for relaxed metal linewidth and / or metal spacing requirements, resulting in a metal linewidth W2 and metal spacing S2 of the signal conductor being greater than the corresponding values ​​in column 311. In one or more embodiments, the larger metal linewidth and metal spacing of the signal conductor reduces the RC and voltage drop (IR drop) associated with the signal conductor, thereby improving the speed or performance of the cells placed in column 312.

[0072] Other methods use the same number of tracks for the metal layers in all columns of the same height. Therefore, in other methods, when the number of tracks is high, the performance of non-complex cells may be hampered due to unnecessarily reduced conductor width and / or spacing; while when the number of tracks is low, internal routing of complex cells may become difficult and / or inefficient. Hybrid column configurations according to some embodiments offer improvements over other methods by placing complex cells in columns with more tracks for efficient internal routing and placing non-complex cells in columns with fewer tracks to improve performance.

[0073] In some embodiments, integrated circuit layout 300A includes at least one high-performance cell configured based on a metal patterning configuration of column 312 and placed in one or more columns similar to column 312, which have fewer tracks but larger metal linewidths and metal spacing. A high-performance cell is a cell configured to achieve high speed or high performance, for which other considerations such as area and / or power consumption play a minor or negligible role. In one or more embodiments, the larger metal linewidths and metal spacing in columns similar to column 312 can reduce RC and / or IR drops, improving performance suitable for high-performance cells. In some embodiments, if the high-performance cell is a complex cell requiring more tracks than in a single column 312 to achieve efficient internal routing, such a complex high-performance cell can be placed across multiple columns 312. Therefore, in one or more embodiments, efficient internal routing can be achieved simultaneously while ensuring the expected high performance of the high-performance cell. In one example, one or more high-performance cells are arranged along a critical path in the integrated circuit device layout. A critical path is a timing-sensitive path through which signals propagate during operation. In one example, a critical path is a path whose time delay does not meet (i.e., is greater than) timing requirements. In another example, the critical path is a path with a long delay (in some cases, the longest delay) within a circuit region of an integrated circuit device or the entire integrated circuit device. A long delay is a delay that may meet timing requirements but is still greater than a predetermined threshold. The time delays of various paths in the integrated circuit design of an integrated circuit device are estimated at design time through one or more simulations performed, for example, before or after Automatic Placement and Routing (APR) operations. Based on the results of these simulations, one or more critical paths can be identified. In some embodiments, reducing the time delay of the critical path is either necessary to meet timing requirements or desired to improve the performance of the integrated circuit device. In one or more embodiments, such an objective can be achieved by arranging high-performance cells along the critical path.

[0074] While some embodiments describe placing complex cells in columns with more tracks and non-complex cells in columns with fewer tracks, in one or more embodiments, it is also possible to place one or more non-complex cells in columns with more tracks. For example, an inverter is a non-complex cell and is typically placed in a column with fewer tracks; however, in some embodiments, one or more inverters are also placed in columns with more tracks. The purpose of doing so is to achieve a desired density, and in some cases, this is a design rule.

[0075] exist Figure 3BIn this configuration, integrated circuit layout 300B includes semiconductor devices arranged in a mixed column configuration, including columns 311 and 332. Column 332 has a pair of boundary lines 302, 306, and a height H between the boundary lines 302, 306. Unlike column 312, which has three signal tracks between a pair of power rails, column 332 has four signal tracks between a pair of power rails. The signal conductors along the signal tracks of column 332 are typically designated as 336 and have the same metal linewidth W1 as the signal conductors in column 311. The power rails 326, 337 along the power rails have the same power rail width W_PG1 as the power rails in column 311. In column 332, the metal spacing S4 between the signal conductors 336 and each other and / or with adjacent power rails 326, 337 is greater than the metal spacing S1 in column 311.

[0076] As described, the metal pattern configuration of column 332 differs from that of column 311, at least in the number of tracks in the column and the metal spacing. In one or more embodiments, the looser metal spacing S4 in column 332 reduces the coupling capacitance of signal conductor 336, thus improving the performance of cells based on the metal pattern configuration of column 332 and placed in column 332. In some embodiments, as described herein, complex cells are placed in column 311 with more tracks, while non-complex cells are placed in column 332 with fewer tracks. In some embodiments, one or more advantages described herein may be achieved by including integrated circuit layout 300B and / or integrated circuit devices manufactured according to said integrated circuit layout.

[0077] exist Figure 3C In some embodiments, integrated circuit layout 300C is a modified layout similar to integrated circuit layout 300B. Integrated circuit layout 300C includes semiconductor devices arranged in a mixed column configuration, including columns 311 and 332'. Column 332' includes a modified metal pattern configuration of column 332, still including four tracks, but with different metal linewidths and metal spacings. For example, in column 332', signal conductors 336' have metal linewidths W3>W1, and metal spacings between each other and / or with adjacent power rails 326, 337 S3>S1. In at least one embodiment, W2>W3>W1, S2>S3>S1, and S4>S3. In some embodiments, one or more advantages described herein can be achieved by including integrated circuit layout 300C and / or integrated circuit devices manufactured according to said integrated circuit layout.

[0078] exist Figure 3DIn this configuration, integrated circuit layout 300D includes semiconductor devices arranged in a hybrid column configuration, including columns 311 and 342. Column 342 has a pair of boundary lines 302, 307, and a height H between the boundary lines 302, 307. Similar to column 332, column 342 has four signal tracks between a pair of power rails. The signal conductors along the signal tracks of column 342 are typically designated as 346 and have a metal linewidth W4 > W1. The power rails 326, 347 along the power rails have the same power rail width W_PG1 as the power rails in column 311. In column 342, the metal spacing between signal conductors 346 and each other and / or with adjacent power rails 326, 347 is the same as that of the signal conductors in column 311, which is S1.

[0079] As described, the metal pattern configuration of column 342 differs from that of column 311, at least in the number of tracks and the metal linewidth in the column. In one or more embodiments, the looser metal linewidth W4 in column 342 reduces the resistance of the signal conductor 346, thus improving the performance of cells based on the metal pattern configuration of column 342 and placed in column 342. In some embodiments, as described herein, complex cells are placed in column 311 with more tracks, while non-complex cells are placed in column 342 with fewer tracks. In some embodiments, one or more advantages described herein may be achieved by including an integrated circuit layout 300D and / or an integrated circuit device manufactured according to said integrated circuit layout.

[0080] exist Figure 3E In this configuration, integrated circuit layout 300E includes semiconductor devices arranged in a mixed column configuration, including columns 311 and 352. Column 352 has a pair of boundary lines 302 and 308, and a height H between the boundary lines 302 and 308. Similar to column 332, column 352 has four signal tracks between a pair of power rails. Power rails 326 and 357 along the power rails have the same power rail width W_PG1 as the power rails in column 311. Signal conductors 353 to 356 along the signal tracks of column 352 have different metal linewidths and metal spacings. Specifically, signal conductors 353 and 356 each have a metal linewidth W5 > W1, and the metal spacing between them and adjacent signal conductors and adjacent power rails is the same as that of the signal conductors in column 311, which is S1. Signal conductors 354 and 355 have the same metal linewidth W1 as the signal conductors in column 311, and the metal spacing between them is S5 > S1.

[0081] As described, the metal pattern configuration of column 352 differs from that of column 311 at least in the number of tracks in the column, the metal linewidth, the metal spacing, and the non-uniform arrangement of the signal conductors. The looser metal linewidth W5 of signal conductors 353 and 356 reduces the resistance of signal conductors 353 and 356, while the looser metal spacing S5 between signal conductors 354 and 355 reduces the coupling capacitance of signal conductors 354 and 355. Therefore, in one or more embodiments, the performance of cells based on the metal pattern configuration of column 352 and placed in column 352 can be improved.

[0082] In some embodiments, performance can be further improved by configuring the cells to be placed in column 352 to internally route a resistive critical network using at least one signal conductor 353, 356 with a wider metal linewidth and lower resistance, and / or to internally route a capacitive critical network using at least one signal conductor 354, 355 with a wider metal spacing and lower capacitance. A resistive critical network is an interconnect structure configured to handle a larger current than other interconnect structures in the cell during operation. Therefore, according to some embodiments, low resistance of the resistive critical network is desirable to reduce voltage drop. An example of a resistive critical network for a cell includes, but is not limited to, the cell's output. A capacitive critical network is an interconnect structure configured to handle time-sensitive signals, such as input signals or frequency signals, during operation, and is configured or desired to have a lower time delay than other interconnect structures in the cell. Therefore, according to some embodiments, low capacitance of the capacitive critical network is desirable to reduce time delay. An example of a capacitive critical network for a cell includes, but is not limited to, the cell's input. An example of a cell with an input wired through a signal conductor with a wider metal spacing and lower capacitance, and an output wired through another signal conductor with a wider metal linewidth and lower resistance, will be... Figure 9B The description is in the middle.

[0083] In some embodiments, as described herein, complex cells are placed in column 311 with more tracks, while non-complex cells are placed in column 352 with fewer tracks. In some embodiments, integrated circuit layout 300E and / or integrated circuit devices manufactured according to such integrated circuit layout can achieve one or more of the advantages described herein.

[0084] exist Figure 3F In the diagram, integrated circuit layout 300F includes semiconductor devices arranged in a mixed column configuration, including columns 311 and 362. The metal pattern configuration of column 311 is shown separately as C31, the metal pattern configuration of column 362 is shown separately as C62, and the metal pattern configuration of the mixed column configuration including columns 311 and 362 is shown as C3162.

[0085] As shown in metal pattern configuration C62, column 362 has a pair of boundary lines 302, 309, and a height H between boundary lines 302, 309. Similar to column 332, column 362 has four signal tracks between a pair of power rails. The signal conductors along the signal tracks of column 362 are typically designated 366 and have the same metal linewidth W1 and metal spacing S1 as the signal conductors in column 311. Power rails 365, 367 along the power rails have power rail widths W_PG2 > W_PG1. As shown in metal pattern configuration C62, when columns 311 and 362 are arranged adjacent to each other along boundary line 302, power rail 365 completely overlaps with power rail 326. This is just one example, and other configurations are within the scope of various embodiments. For example, in one or more embodiments, power rail 365 partially overlaps with power rail 326, resulting in a power rail width greater than W_PG1 at the boundary between columns 311 and 362.

[0086] As described, the metal pattern configuration of column 362 differs from that of column 311, at least in the number of rails in the column and the power rail width. In one or more embodiments, the increased power rail width W_PG2 in column 362 reduces the power rail resistance and IR voltage drop, thus improving the performance of cells configured and placed in column 362 based on the metal pattern configuration of column 362. In some embodiments, as described herein, complex cells are placed in column 311 with more rails, while non-complex cells are placed in column 362 with fewer rails. In some embodiments, an integrated circuit layout 300F and / or an integrated circuit device manufactured according to such an integrated circuit layout can achieve one or more of the advantages described herein.

[0087] exist Figure 3G In the integrated circuit layout 300G, semiconductor devices are arranged in a mixed column configuration, including columns 311 and 392. Except for the via size, the metal pattern configuration of column 392 is the same as that of column 342 described with respect to integrated circuit layout 300D. In integrated circuit layout 300D of at least one embodiment, vias connected to signal conductors with a metal linewidth W1 in column 311 have the same size as vias connected to signal conductors with a larger metal linewidth W4 (W4>W1) in column 342. In integrated circuit layout 300G, as shown in exemplary section 380 of integrated circuit layout 300G, vias connected to signal conductors with a larger metal linewidth W4 in column 342 have a larger size than vias connected to signal conductors with a metal linewidth W1 in column 311.

[0088] Section 380 in column 311 includes: signal conductors 371 to 375 corresponding to signal conductors 321 to 325, gate region 376 connected to signal conductor 373 through VG via VG1, metal-to-source / drain (MD) contact structure 377 connected to signal conductor 371 through VD via VD1, and first metal layer (M1) conductor 378 connected to signal conductors 371 and 375 respectively through V0 vias V01 and V02. Section 380 in column 392 further includes: signal conductors 381 to 384 corresponding to signal conductor 346, gate region 386 connected to signal conductor 382 through VG via VG2, metal-to-source / drain (MD) contact structure 387 connected to signal conductor 381 through VD via VD2, and first metal layer (M1) conductor 388 connected to signal conductors 381 and 384 respectively through V0 vias V03 and V04.

[0089] At least one VG via, VD via, and V0 via in column 392 is larger than at least one corresponding VG via, VD via, and V0 via in column 311. In the example configuration of Figure 3G, vias VG2, VD2, V03, and V04 in column 392 are larger than vias VG1, VD1, V01, and V02 in column 311, respectively.

[0090] As described above, the metal pattern configuration of column 392 differs from that of column 311 at least in the number of tracks in the column, the metal linewidth, and the via size. In one or more embodiments, the relaxed metal linewidth W4 and larger via size in column 392 reduce the interconnect RC of signal conductors in column 392, thus improving the performance of cells based on the metal pattern configuration of column 392 and placed in column 392. In some embodiments, as described herein, complex cells are placed in column 311 with more tracks, while non-complex cells are placed in column 392 with fewer tracks. In some embodiments, an integrated circuit layout 300G and / or an integrated circuit device manufactured according to said integrated circuit layout can achieve one or more of the advantages described herein.

[0091] about Figures 3A-3G The various hybrid column configurations and / or metallic pattern configurations described are merely examples. Other hybrid column configurations and / or metallic pattern configurations are also within the scope of various embodiments. In at least one embodiment, regarding Figures 3A-3G One or more of the described features can be related to... Figures 3A-3G Combined with one or more of the other features described herein. For example, in at least one embodiment, regarding Figure 3G The different via sizes described can be related to... Figure 3EThe described combination of signal conductors with different metal linewidths. In some embodiments, one or more features and / or metal pattern configurations described for a column with five tracks are applicable to columns with fewer than five tracks. In at least one embodiment, one or more features and / or metal pattern configurations described for a column with four tracks are applicable to columns with fewer than four tracks, such as columns with three tracks or columns with two tracks.

[0092] In some embodiments, hybrid column configurations include columns of the same height but with different metal patterning configurations on the metal zero (MO) layer, enabling improved performance and reduced IR drop without increasing area. In one or more embodiments, columns with more MO tracks allow internal wiring of complex cells to be efficiently completed within the MO layer and within optimal chip area without the need for additional wiring resources in one or more higher metal layers and / or via layers. In some embodiments, columns with fewer MO tracks allow wider metal linewidths and / or metal spacing for MO conductors, which reduces RC and improves the performance of non-complex cells requiring less wiring resources without increasing area. In at least one embodiment, reducing the power rail width of the MO power rails helps reduce IR drop in the cell. In some embodiments, the same logic (or the same cell) is implemented (or placed) in multiple columns with different MO layer metal patterning configurations to meet density requirements.

[0093] Figures 4A-4D 5A, 5B, 6A, 6B, 7A, and 7B are schematic diagrams of corresponding integrated circuit layouts 400A–400D, 500A, 500B, 600A, 600B, 700A, and 700B with various mixed column configurations, according to some embodiments. In at least one embodiment, an integrated circuit device manufactured based on one or more integrated circuit layouts 400A–400D, 500A, 500B, 600A, 600B, 700A, and 700B corresponds to integrated circuit device 200. In some embodiments, one or more integrated circuit layouts 400A–400D, 500A, 500B, 600A, 600B, 700A, and 700B are generated by an electronic design automation (EDA) system, such as an automatic place and route (APR) system, and / or stored in a non-transitory computer-readable storage medium. The description herein regarding one or more integrated circuit layouts 400A-400D, 500A-500B, 600A-600B, 700A-700B applies to integrated circuit devices manufactured based on said one or more integrated circuit layouts. For simplicity, Figures 4A-4DThe corresponding components in 5A, 5B, 6A, 6B, 7A, and 7B are specified by the same reference number. Layouts 400A–400D, 500A, 500B, 600A, 600B, 700A, and 700B have various mixed column configurations as described herein.

[0094] exist Figure 4A In this embodiment, integrated circuit layout 400A includes a repeating pattern of column set 410 along the Y-axis. Column set 410 includes a first column MP1 and a second column MP2, both having the same height H. The metal pattern configuration of the first column MP1 differs from that of the second column MP2. Therefore, the first column MP1 and the second column MP2 are arranged in a mixed column configuration. In some embodiments, the metal pattern configuration of the first column MP1 and the second column MP2 corresponds to any pair of different metal pattern configurations described herein, for example, with respect to one or more Figures 3A-3G The configuration is as follows. For example, the first column MP1 includes N tracks, while the second column MP2 includes fewer tracks, such as (N-1) tracks, (N-2) tracks, or a similar number. N is a natural number greater than 2. In some embodiments, N = 5.

[0095] In some embodiments, as described herein, complex cells are placed in a first column MP1 with more tracks to achieve efficient internal routing and / or optimized area for these complex cells. Conversely, non-complex cells are placed in a second column MP2 to improve performance and / or reduce power consumption. In a non-limiting example, compared to a layout with five tracks in all columns, a layout with a mixed column configuration (five tracks in the first column and four tracks in the second column) achieves approximately a 4.5% speed improvement and approximately a 0.9% power reduction for non-complex cells in the second column. Furthermore, compared to a layout with four tracks in all columns, a layout with a mixed column configuration (five tracks in the first column and four tracks in the second column) achieves approximately a 9.3% speed improvement and approximately a 15.8% reduction in chip area for complex cells in the first column.

[0096] exist Figure 4B In this layout 400B, a repeating pattern of column set 420 is included along the Y-axis. Column set 420 includes a first subset 421 comprising a plurality of first columns MP1, and a second subset 422 comprising a plurality of second columns MP2, all columns having the same height H. In some embodiments, a configuration in which the plurality of second columns MP2 are arranged adjacently allows for the accommodation of one or more complex, high-performance units by placing these complex, high-performance units across the plurality of adjacent second columns MP2, as described herein.

[0097] Figure 4A and 4BThe integrated circuit layouts 400A and 400B are examples of hybrid column configurations, where the number of MP1 in the first column is equal to the number of MP2 in the second column. Figure 4C and 4D The integrated circuit layouts 400C and 400D are examples of mixed column configurations, where the number of MP1 in the first column is different from the number of MP2 in the second column.

[0098] exist Figure 4C In the layout 400C, a repeating pattern of column set 430 is included along the Y-axis. Column set 430 includes a first column MP1 and two second columns MP2. The two second columns MP2 are adjacent along the Y-axis. The ratio of the number of first column MP1 to the number of second column MP2 is 1:2.

[0099] exist Figure 4D In this layout 400D, a repeating pattern of column set 440 is included along the Y-axis. Column set 440 includes three first columns MP1 and five second columns MP2. The ratio of the number of first columns MP1 to the number of second columns MP2 is 3:5. Unlike in integrated circuit layout 400C, where the second columns MP2 are grouped together in column set 430, the second columns MP2 are arranged at several positions along the Y-axis in column set 440. The first columns MP1 are also arranged at several positions along the Y-axis in column set 440. The specific number of first columns MP1 and / or second columns MP2, their ratio, and / or the physical arrangement of first columns MP1 and / or second columns MP2 in one or more column sets 410-440 are examples. Other configurations are also within the scope of various embodiments.

[0100] In some embodiments, the number of first columns MP1 and second columns MP2 in the integrated circuit layout is determined by an electronic design automation (EDA) tool. For example, upon receiving an integrated circuit schematic (e.g., a circuit) for which an integrated circuit layout is to be generated, the EDA tool is configured to count or determine the number of complex cells and the number of non-complex cells from the integrated circuit schematic. Based on the ratio between the counted or determined number of complex cells and the counted or determined number of non-complex cells, the EDA tool is configured to select or generate column sets to repeat along the Y-axis in the integrated circuit layout. For example, column set 410 or column set 420 is selected to generate the integrated circuit layout when the ratio of the number of complex cells to the number of non-complex cells in the integrated circuit schematic is within a predetermined range of approximately 1:1. In at least one embodiment, a human designer and / or the EDA tool performs the decision to select between column set 410 and column set 420 based on one or more other considerations. As another example, column set 430 is selected when the ratio of the number of complex cells to the number of non-complex cells in the integrated circuit schematic is within a predetermined range of approximately 1:2. In some embodiments, one or more advantages described herein may be achieved by one or more integrated circuit layouts 400A to 400D and / or integrated circuit devices manufactured according to these integrated circuit layouts.

[0101] Figures 4A-4D The integrated circuit layouts 400A to 400D in the text are examples of hybrid column configurations, including columns of the same height and two different metal pattern configurations. Figure 5A , 5B The integrated circuit layouts 500A and 500B in the examples are hybrid column configurations, including columns of the same height and three different metal pattern configurations. Other hybrid column configurations with four or more metal pattern configurations are also within the scope of various embodiments.

[0102] exist Figure 5A In this embodiment, integrated circuit layout 500A includes a repeating pattern of column set 510 along the Y-axis. Column set 510 includes a first column MP1, a second column MP2, and a third column MP3, all having the same height H. The first column MP1, second column MP2, and third column MP3 have different metal pattern configurations. Therefore, the first column MP1, second column MP2, and third column MP3 are arranged in a mixed column configuration. In some embodiments, the metal pattern configuration of the first column MP1, second column MP2, and third column MP3 corresponds to any of the three different metal pattern configurations described herein, for example, regarding... Figures 3A-3GOne or more of the following. For example, the first column MP1 includes N tracks, the second column MP2 includes (N-1) tracks, and the third column MP3 includes (N-2) tracks, where N is a natural number greater than 2. In some embodiments, N = 5.

[0103] In some embodiments, complex units are placed in the first column MP1, which has more tracks, while non-complex units are placed in the second column MP2 and / or the third column MP3. In at least one embodiment, non-complex units include medium units and simple units. Medium units have more interconnects than simple units (but still fewer interconnects than complex units). In one example, complex units have more than five interconnects, medium units have three to five interconnects, and simple units have two or fewer interconnects. Non-limiting specific examples of simple units, medium units, and complex units are respectively provided in... Figure 9A , 9B , Figure 9C , 9D and Figure 9E , 9F The relevant description is provided in the text.

[0104] In at least one embodiment, complex cells are placed in the first column MP1, medium cells are placed in the second column MP2, and simple cells are placed in the third column MP3 to achieve a balance between various effects, including but not limited to efficient internal wiring, optimized area, improved performance, and reduced power consumption. In some embodiments, as described herein, one or more simple cells are also placed in one or more second columns MP2, and / or one or more medium cells are also placed in one or more third columns MP3 to achieve the desired density.

[0105] Figure 5A The integrated circuit layout 500A in the example is a hybrid column configuration, where the number of MP1 in the first column is equal to the number of MP2 in the second column and the number of MP3 in the third column. Figure 5B The integrated circuit layout 500B in the example is a hybrid column configuration with a different number of columns and different metal pattern configurations.

[0106] exist Figure 5BIn this layout 500B, a repeating pattern of column set 530 is included along the Y-axis. Column set 530 includes a first subset 520 and a second subset 525. Each of the first subset 520 and the second subset 525 includes two first columns MP1, one second column MP2, and one third column MP3. The first subset 520 and the second subset 525 are symmetrical on the X-axis. The ratio of the number of first columns MP1 to the number of second columns MP2 to the number of third columns MP3 is 2:1:1. This ratio and the specific arrangement of the first columns MP1, second columns MP2, and third columns MP3 in column set 530 are merely examples. Other configurations are also within the scope of various embodiments. In some embodiments, such as relative to... Figure 4C As described, the number of the first column MP1, the second column MP2, and the third column MP3 in the integrated circuit layout is determined from the corresponding integrated circuit schematic using electronic design automation (EDA) tools. In some embodiments, one or more advantages described herein can be achieved by one or more integrated circuit layouts 500A, 500B and / or integrated circuit devices manufactured according to these integrated circuit layouts.

[0107] Figures 4A-4D The integrated circuit layouts 400A-400D, 500A, and 500B in 5A and 5B are examples of mixed column configurations that include columns of the same height. Figure 6A , 6B The integrated circuit layouts in 7A and 7B, 600A, 600B, 700A, and 700B are examples of mixed column configurations that include columns of different heights.

[0108] exist Figure 6A In the integrated circuit layout 600A, a repeating pattern of column set 610 is included along the Y-axis. Column set 610 includes a first column MP1, a second column MP2, and a third column MP33. The first column MP1 and the second column MP2 have the same height H and have a pattern relative to one or more... Figures 4A-4D The different metal pattern configurations described in 5A and 5B. The third column MP33 has a height H3 that is different from the height H of the first column MP1 and the second column MP2. In some embodiments, the ratio between H and H3 is approximately 1.1 to 1.5.

[0109] exist Figure 6AIn an example configuration, H3 < H. In some embodiments, the third column MP33 with H3 < H (sometimes referred to as a "short column") includes cells with an active region width smaller than that of the cells in the first column MP1 and the second column MP2. Thus, the cells in the third column MP33 (sometimes referred to as "short cells") have lower speed / performance than the cells in the first column MP1 and the second column MP2, but occupy less area and consume less power. The short cells and the short column are configured to provide non-critical circuits optimized for area and power rather than speed / performance. To meet the same set of design rules at a smaller height H3 and a smaller active region width, the third column MP33 has a different metal pattern configuration from the first column MP1 and the second column MP2 in one or more aspects described herein.

[0110] In at least one embodiment (not shown), H3 > H. In some embodiments, the third column MP33 with H3 > H (sometimes referred to as a "tall column") includes cells with an active region width larger than that of the cells in the first column MP1 and the second column MP2. Thus, the cells in the third column MP33 (sometimes referred to as "tall cells") have higher speed / performance than the cells in the first column MP1 and the second column MP2, but occupy more area and consume more power. The tall cells and the tall column are configured to provide critical circuits optimized for speed / performance at the expense of area and power. To meet the same set of design rules at a larger height H3 and a larger active region width, the third column MP33 has a different metal pattern configuration from the first column MP1 and the second column MP2 in one or more aspects described herein. In some embodiments (not shown), both short columns and tall columns are included in the integrated circuit layout.

[0111] Figure 6A The integrated circuit layout 600A in [description] is an example of a hybrid column configuration where the number of the first column MP1 is equal to the number of the second column MP2 and the number of the third column MP33. Figure 6B The integrated circuit layout 600B in [description] is an example of a hybrid column configuration with columns having different numbers and different metal pattern configurations.

[0112] In Figure 6BIn this layout 600B, a repeating pattern of column set 630 is included along the Y-axis. Column set 630 includes a first subset 620 and a second subset 625. Each of the first subset 620 and the second subset 625 includes two first columns MP1, one second column MP2, and one third column MP33. The first subset 620 and the second subset 625 are symmetrical on the X-axis. The ratio of the number of first columns MP1 to the number of second columns MP2 to the number of third columns MP33 is 2:1:1. This ratio and the specific arrangement of the first columns MP1, second columns MP2, and third columns MP33 in column set 630 are merely examples. Other configurations are also within the scope of various embodiments. In some embodiments, such as relative to Figure 4C As described, the number of the first column MP1 and the second column MP2 in the integrated circuit layout is determined by electronic design automation (EDA) tools from the corresponding integrated circuit schematic. In at least one embodiment, the number of the third column MP33 is also determined by EDA tools from the corresponding integrated circuit schematic, for example, by counting or determining the number of non-critical cells to be placed in the third column MP33 as a short column, and / or by counting or determining the number of critical cells to be placed in the third column MP33 as a tall column. In some embodiments, one or more advantages described herein may be achieved by one or more integrated circuit layouts 600A, 600B and / or integrated circuit devices manufactured according to these integrated circuit layouts.

[0113] Figure 7A , 7B The integrated circuit layouts 700A and 700B also include... Figure 6A , 6B The third column, MP33, has the same height H3 as the column, but with a different metallic pattern configuration.

[0114] exist Figure 7A In the integrated circuit layout 700A, a repeating pattern of column set 710 is included along the Y-axis. Column set 710 includes a first column MP1, a second column MP2, a third column MP33, and a fourth column MP34. The first column MP1 and the second column MP2 have the same height H, but different metal pattern configurations as described herein. The third column MP33 and the fourth column MP34 have the same height H3, but different metal pattern configurations. The metal pattern configurations of the third column MP33 and the fourth column MP34 differ in one or more aspects described herein. In one example, the third column MP33 has M tracks, while the fourth column MP34 has (M-1) tracks. Figure 7AIn the example configuration shown, where H3 < H, non-critical complex units are placed in the third column MP33, and non-critical non-complex units are placed in the fourth column MP34. In some embodiments (not shown), where H3 > H, critical complex units are placed in the third column MP33, and critical non-complex units are placed in the fourth column MP34.

[0115] Figure 7A The integrated circuit layout 700A in FIG. 4 is an example of a hybrid column configuration, where the number of the first column MP1 is equal to the number of the second column MP2, the number of the third column MP33, and the number of the fourth column MP34. Figure 7B The integrated circuit layout 700B in FIG. 5 is an example of a hybrid column configuration having different numbers of columns and different metal pattern configurations.

[0116] In Figure 7B FIG. 6, the integrated circuit layout 700B includes a repeating pattern of column sets 730 along the Y-axis. The column set 730 includes four first columns MP1, two second columns MP2, two third columns MP33, and one fourth column MP34. The number and specific arrangement of the first column MP1, the second column MP2, the third column MP33, and the fourth column MP34 in the column set 730 are examples. Other configurations are also within the scope of various embodiments. In some embodiments, the number of the first column MP1, the second column MP2, the third column MP33, and the fourth column MP34 in the integrated circuit layout is determined by an electronic design automation (EDA) tool according to the corresponding integrated circuit schematic, as described with respect to one or more of Figure 4C 、 6B FIGS. 7A-7C. In some embodiments, one or more of the advantages described herein can be achieved by one or more integrated circuit layouts 700A, 700B, and / or integrated circuit devices manufactured according to these integrated circuit layouts.

[0117] Figure 8A FIG. 8 is a flowchart of a method 800A according to some embodiments. In at least one embodiment, the method 800A is performed at least in part by a processor to establish a cell library including cells that can be used to generate an integrated circuit layout having a hybrid column configuration, as described herein.

[0118] In operation 802, a cell design of a cell is received. In some embodiments, the cell design includes the circuit of the cell. Example circuits of various cells are described in Figure 9A 、 9C 、9E. In at least one embodiment, the cell design includes a standard (or pre-developed) cell layout of the cell. An example standard cell layout is similar to Figure 1B 、 1Cor Figures 3A-3G The metal pattern configuration (e.g., quantity, metal line width, metal spacing, etc.) of the M0 tracks used for internal wiring in the cell, as described in column 311, is predetermined. Other standard cell layout configurations are also within the scope of various embodiments. In at least one embodiment, operation 802 is omitted.

[0119] In operation 804, it is determined whether complex internal wiring is required. In other words, it is determined whether the cell is a complex cell. In at least one embodiment, as described herein, the determination of whether a cell is a complex cell is based on the number of interconnects in the cell. If the number of interconnects in the cell is greater than a predetermined number (or a threshold), then the cell is a complex cell. Otherwise, the cell is a non-complex cell. In at least one embodiment, the predetermined threshold is five. Other thresholds are also within the range of various embodiments.

[0120] In operation 806, if it is determined in operation 804 that complex internal wiring is required or that the cell is a complex cell, the process proceeds to operation 806. Otherwise, the process proceeds to operations 808 and 810.

[0121] In operation 806, when the cell is a complex cell, a first cell layout is obtained. The first cell layout has a first number of M0 tracks. The obtained first cell layout is stored in a cell library on a non-transitory computer-readable storage medium. In some embodiments, when the cell is designed as a standard cell layout, the standard cell layout is used as the first cell layout. In at least one embodiment, when the cell is designed as a circuit of the cell, the first cell layout is generated based on a predetermined metal pattern configuration, as described herein.

[0122] In operation 808, when the cell is a non-complex cell, a second cell layout is obtained. The second cell layout has the same height as the first cell layout and has a second number of M0 tracks. The second number of M0 tracks in the second cell layout is less than the first number of M0 tracks in the first cell layout. In at least one embodiment, the second cell layout is generated for the cell based on a metal pattern configuration having a second number of M0 tracks.

[0123] In operation 810, when the cell is also a non-complex cell, a third cell layout is obtained. The third cell layout has the same height as the first cell layout and has a third number of M0 tracks. The third number of M0 tracks in the third cell layout is less than the second number of M0 tracks in the second cell layout. In at least one embodiment, the third cell layout is generated for the cell based on a metal pattern configuration having a third number of M0 tracks. In one example, the first cell layout has five M0 tracks, the second cell layout has four M0 tracks, and the third cell layout has three M0 tracks. Other configurations are also within the scope of various embodiments.

[0124] In operation 812, a power-performance analysis (PPA) is performed on the second cell layout and the third cell layout. In at least one embodiment, the PPA analysis includes simulating a circuit built using the second cell layout and the same circuit built using the third cell layout. In at least one embodiment, the results of the PPA analysis include a quantitative assessment of how the second cell layout and the third cell layout each affect or contribute to one or more of power consumption, performance, and area. In at least one embodiment, operation 812 is omitted.

[0125] In operation 814, at least one of the second cell layout or the third cell layout is stored in the cell library. In some embodiments, when a PPA analysis is performed in operation 812, the results of the PPA analysis indicate which of the second or third cell layouts is better in terms of PPA. The better cell layout is then stored in the cell library.

[0126] In at least one embodiment, both the second and third cell layouts are stored in a cell library along with information related to their respective PPA analysis results. This information can then be used to determine which of the second or third cell layouts should be used to construct the integrated circuit layout. For example, when constructing an integrated circuit layout or a region thereof, if a cell is required to improve power consumption and / or area, and the information stored with the second and third cell layouts indicates that the second cell layout is superior to the third cell layout in terms of power consumption and / or area, then the second cell layout is selected and placed in the integrated circuit layout or its region.

[0127] In at least one embodiment, when PPA analysis is omitted in operation 812, both the second and third cell layouts are stored in a cell library. As needed, one of the stored second and third cell layouts is selected and placed in a specific area of ​​the integrated circuit layout being constructed. For example, when a cell is needed in a column with three M0 tracks, the third cell layout with three M0 tracks is selected. Similarly, when a cell is needed in a column with four M0 tracks, the second cell layout with four M0 tracks is selected.

[0128] In some embodiments, for non-complex cells, a standard cell layout (e.g., with five M0 tracks) is obtained and stored in a cell library along with second and third cell layouts of the same cell design. For example, in one or more embodiments, the cell library includes multiple cell layouts corresponding to five, four, and three M0 tracks for the same non-complex cell, such as an inverter. As described herein, this is done to allow non-complex cells to be placed in columns with a higher number (e.g., five) of M0 tracks to meet density requirements.

[0129] In some embodiments, multiple second cell layouts and / or multiple third cell layouts are generated, PPA analysis is performed, and / or stored. For example, multiple second cell layouts are generated, all having the same height and four M0 tracks; however, as Figures 3B-3G As described in columns 332, 342, 352, 362, and 392, there are one or more differences in one or more aspects of metal linewidth, metal spacing, power rail width, via size, or similar characteristics. In some embodiments, one or more advantages described herein can be achieved by using one or more integrated circuit layouts constructed using cells stored in a cell library and / or integrated circuit devices manufactured according to these integrated circuit layouts.

[0130] Figure 8B The diagram illustrates a method 800B according to some embodiments. In at least one embodiment, method 800B is executed at least in part by a processor or electronic design automation (EDA) system to generate an integrated circuit layout with a hybrid column configuration, such as using... Figure 8A The units stored in the unit library.

[0131] In operation 832, the relationship between cells of a first cell type and cells of different second cell types in the integrated circuit device is determined based on the integrated circuit schematic diagram of the integrated circuit device. For example, the first cell type corresponds to a complex cell, while the second cell type corresponds to a non-complex cell. In some embodiments, as described herein, the relationship between cells of the first cell type and cells of the second cell type in the integrated circuit device is the ratio of the number of complex cells to the number of non-complex cells.

[0132] In operation 834, based on a defined relationship, a set of repeating patterns of columns with the same height is generated. The set of columns includes at least one first column having a first metal pattern configuration corresponding to a first cell type, and at least one second column having a different second metal pattern configuration corresponding to a second cell type. For example, when the ratio of the number of complex cells to the number of non-complex cells in a defined integrated circuit device is within a predetermined range of approximately 1:1, a selection is made as follows... Figure 4A , 4B One of the hybrid column configurations described in 5A, 6A, and 7A is used as a column group to be repeatedly generated in the integrated circuit layout. When the determined ratio is within a predetermined range near another ratio, a corresponding hybrid column configuration with a non-uniform column distribution is selected, for example, as... Figure 4C , 4D As described in 5B, 6B, and 7B, these are column groups that are to be repeatedly generated in the layout of an integrated circuit.

[0133] In operation 836, a place-and-route or automatic placement and routing (APR) operation is performed. An APR operation includes placing a first cell of a first cell type into a first column and placing a second cell of a second cell type into a second column. For example, as described herein, complex cells are placed in columns with more tracks, while non-complex cells are placed in columns with fewer tracks. In some embodiments, a routing operation is performed to connect the placed cells and obtain an integrated circuit layout. The obtained integrated circuit layout is stored in a non-transitory computer-readable storage medium and / or used to manufacture integrated circuit devices. In some embodiments, the integrated circuit layouts generated by method 800B and / or integrated circuit devices manufactured according to these integrated circuit layouts can achieve one or more of the advantages described herein.

[0134] Figure 8C This is a flowchart of method 800C according to some embodiments. In some embodiments, method 800C is a manufacturing process performed using a manufacturing system discussed below, and in the process, at least one of the following operations is performed: (A) performing one or more photolithography exposures, (B) fabricating one or more semiconductor photomasks, or (C) fabricating one or more components in a layer of an integrated circuit device. In some embodiments, the integrated circuit device is fabricated by method 800C based on the integrated circuit layout generated by method 800B and / or using a cell library established according to method 800A.

[0135] In operation 852, multiple semiconductor devices are formed on the substrate, such as... Figure 2 As stated above.

[0136] In operation 854, a metal layer is deposited on a substrate and patterned to obtain a plurality of power rails and a plurality of conductors arranged between the plurality of power rails. The plurality of conductors includes a first conductor located between a first pair of adjacent power rails to configure a first metal pattern configuration, and a second conductor located between a second pair of adjacent power rails to configure a second metal pattern configuration. The first metal pattern configuration and the second metal pattern configuration differ in at least one of the following aspects: the number of rails of the first conductor and the second conductor are different; the widths of the first conductor and the second conductor are different; the spacing between the first conductor and the second conductor is different; or the widths of the power rails corresponding to the first conductor and the second conductor are different. Figure 2 In one example, an MO layer is deposited and patterned on a substrate on which a semiconductor device is formed. For example... Figures 3A-3G The MO layer comprises a mixed column configuration of columns with different metal pattern configurations. In some embodiments, an integrated circuit device manufactured according to method 800C can achieve one or more of the advantages described herein.

[0137] The described methods include exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, substituted, interchanged, and / or eliminated according to the spirit and scope of the embodiments disclosed herein. Embodiments combining different features and / or different embodiments are within the scope of the embodiments disclosed herein and will be apparent to those skilled in the art upon review of the embodiments disclosed herein.

[0138] Figure 9A This is the circuit diagram for a 900A inverter. Figure 9B This is the cell layout corresponding to cell 900B of inverter 900A, according to some embodiments. In one or more embodiments, cell 900B is an example of a simple cell, which is a non-complex cell.

[0139] exist Figure 9A In this embodiment, inverter 900A includes a PMOS transistor P1 and an NMOS transistor N1 connected in series between VDD and VSS. The gates of transistors P1 and N1 are coupled to the input IN1. The source / drain region of transistor P1 is coupled to the source / drain region of transistor N1 and the output ZN1. Inverter 900A has two interconnect structures corresponding to the input IN1 and the output ZN1. In some embodiments, as described herein, the number of these two interconnect structures is used to classify inverter cells (such as cell 900B) as uncomplex or simple cells.

[0140] exist Figure 9B In this context, cell 900B includes a boundary, an active region, a gate region, an MD contact structure, a VD via, a VG via, and an M0 conductor, similar to... Figure 1B , 1CThe structure described herein. Specifically, cell 900B includes active regions OD_P and OD_N, and four gate regions commonly designated 920, arranged between dummy gate regions 921 and 922. The four gate regions 920 are electrically coupled together to configure an inverter with a drive strength of 4. Gate region 920 is configured with transistor P1 in active region OD_P and transistor N1 in active region OD_N. Cell 900B also includes M0 conductors 910–914 in the M0 layer. M0 conductor 910 is the VDD power rail, M0 conductor 914 is the VSS power rail, and M0 conductors 911–913 are signal conductors on the three signal rails. For simplicity, Figure 9B The MD contact structure and VD via coupled to power rails 910 and 914 are omitted. Unit 900B also includes four VG vias (one of which is located in…). Figure 9B The four gate regions 920 are correspondingly coupled to the M0 conductor 912 configured for input IN1. Cell 900B also includes VD vias VD_1 and VD_2, which couple the corresponding MD contact structures (not shown) to the M0 conductor 913 configured for output ZN1. Cell 900B also includes a V0 via V0_1 located above the M0 conductor 913 for coupling the M0 conductor 913 to the M1 conductor (not shown) during routing operations. In some embodiments, via V0_1 is omitted from cell 900B and generated during routing operations by an Automatic Placement and Routing (APR) tool. The boundaries of cell 900B are configured by the center lines of dummy gate regions 921, 922 and power rails 910, 914.

[0141] The M0 conductors 910-914 of unit 900B are configured according to the metal pattern arrangement of the column with three tracks to be placed in unit 900B. The metal line width W91 of M0 conductors 911 and 913 is greater than the metal line width W92 of M0 conductor 912. The metal spacing S92 between M0 conductor 912 and adjacent M0 conductors 911 and 913 is greater than the metal spacing S91 between M0 conductors 911 and 913 and power rails 910 and 914, respectively. The configuration of the described M0 conductors 910-914 is similar to Figure 3E The metal pattern configuration of column 352. For example, similar to the metal pattern configuration described with respect to column 352, the input IN1 of cell 900B is configured by M0 conductor 912, which has a large metal spacing with adjacent M0 conductors, while the output ZN1 of cell 900B is configured by M0 conductor 913, which has a larger metal linewidth than adjacent M0 conductors 912. In some embodiments, one or more advantages described herein may be achieved by including one or more integrated circuit layouts of cell 900B and / or integrated circuit devices manufactured according to these integrated circuit layouts.

[0142] Figure 9C This is the circuit diagram of the AND-OR-INVENTER (AOI) 900C. Figure 9D This is a cell layout corresponding to cell 900D of inverter 900C, according to some embodiments. In one or more embodiments, cell 900D is an example of an intermediate cell, which is a non-complex cell.

[0143] exist Figure 9C In this embodiment, the AND / OR inverter 900C includes PMOS transistors P2-P4 and NMOS transistors N2-N4. Transistors P2 and P3 are connected in parallel between VDD and node No1. Transistor P4 is connected between node No1 and output ZN2. Transistors N2 and N3 are connected in series between VSS and output ZN2. Transistor N4 is connected between VSS and output ZN2. The gates of transistors P2 and N2 are connected to input A1, the gates of transistors P3 and N3 are connected to input A2, and the gates of transistors P4 and N4 are connected to input B. The AND / OR inverter 900C has five interconnects, corresponding to the three inputs A1, A2, and B, output ZN2, and node No1. In some embodiments, this number of five interconnects is used to classify the AND / OR inverter unit (such as unit 900D) as a non-complex unit or an intermediate unit, as described herein.

[0144] exist Figure 9D In this cell, 900D includes a boundary, an active region, a gate region, an MD contact structure, a VD via, a VG via, and an M0 conductor, which are similar to... Figure 1B , 1C The structure described in 9B. Specifically, cell 900D includes active regions OD_P and OD_N, and three gate regions commonly designated 940, arranged between dummy gate regions 941 and 942. Gate region 940 is configured with active region OD_P as transistors P2 to P4, and with active region OD_N as transistors N2 to N4. Cell 900D also includes M0 conductors 930 to 936 in the M0 layer. M0 conductor 930 is the VDD power rail, M0 conductor 936 is the VSS power rail, and M0 conductors 931 to 935 are signal conductors located on the four signal rails. M0 conductors 933 and 934 are located on the same rail and are physically and electrically separated from each other by a cut M0 mask schematically designated 939. For simplicity, Figure 9DThe MD contact structures and VD vias connecting to power rails 930 and 936 are omitted. Unit 900D also includes VG vias VG_2, VG_3, and VG_4, connecting the corresponding gate regions 940 to M0 conductors 932, 933, and 934, which correspondingly configure inputs A1, A2, and B. Unit 900D also includes VD vias VD_3 and VD_4, connecting the corresponding MD contact structures (not shown) to the M0 conductor 931 configuring node No.1. Unit 900D also includes VD vias VD_5 and VD_6, connecting the corresponding MD contact structures (not shown) to the M0 conductor 935 configuring output ZN2. Unit 900D also includes a V0 via V0_2 located above the M0 conductor 933 for connecting the M0 conductor 933 to the M1 conductor (not shown) during wiring operations. In some embodiments, the V0 via V0_2 is omitted from cell 900D and is generated during routing operations by an automatic place and route (APR) tool. The boundaries of cell 900D are configured by the center lines of dummy gate regions 941, 942 and power rails 930, 936.

[0145] The M0 conductors 930-936 of unit 900D are configured according to the metal pattern arrangement of the four track columns to which unit 900D will be placed. The configuration of M0 conductors 930-936 is similar to Figure 3E The metal pattern configuration of column 352 and Figure 9B The configuration of M0 conductors 910-914. Specifically, the inputs A1, A2, and B of unit 900D are configured with M0 conductors 932-934, which have a large metal spacing between each other and with adjacent M0 conductors 931 and 935 in the Y-axis direction, while the output ZN2 of unit 900D is configured with M0 conductor 935, which has a larger metal linewidth than the adjacent M0 conductor 933. In some embodiments, one or more advantages described herein can be achieved by one or more integrated circuit layouts including unit 900D and / or integrated circuit devices manufactured according to these integrated circuit layouts.

[0146] Figure 9E This is the circuit diagram for the 900E flip-flop. Figure 9F This is the cell layout corresponding to cell 900F of flip-flop 900E, according to some embodiments. In one or more embodiments, cell 900F is an example of a complex cell.

[0147] exist Figure 9EIn this circuit, flip-flop 900E includes various PMOS and NMOS transistors coupled to form circuits 951–955, transmission gates TG1m, TG2m, TG1s, and TG2s, and inverters INV1m, INV2m, INV1s, and INV2s. Transmission gates TG1m and TG2m and inverters INV1m and INV2m are configured as a master latch circuit. Transmission gates TG1s and TG2s and inverters INV1s and INV2s are configured as a slave latch circuit. Flip-flop 900E includes inputs D, SI, SE, and CP, and an output Q. Flip-flop 900E has more than five interconnects, including four inputs D, SI, SE, CP, output Q, and various other interconnects in one or more of the circuits 951–955, the master latch circuit, and the slave latch circuit. In some embodiments, as described herein, this high number of interconnects is used to classify flip-flop units (such as unit 900F) into complex units.

[0148] exist Figure 9F In the cell 900F, the boundary, active region, gate region, MD contact structure, VD via, VG via, and M0 conductor are similar to those in... Figure 1B , 1C The structures described in 9B and 9D. For simplicity, apart from several M0 conductors, other features are not numbered and are not described in detail here.

[0149] The M0 conductors of cell 900F are configured according to the metal pattern configuration of the column with five tracks to which cell 900F will be placed. Specifically, cell 900F includes an M0 conductor 960 as a VDD power rail, an M0 conductor 967 as a VSS power rail, and various M0 conductors as signal conductors on the five signal tracks in the M0 layer. Among the signal conductors, M0 conductors 961-966 are configured for inputs SE, CP, D, SI, and output Q. These M0 conductors have the same metal linewidth and the same metal spacing. The configuration of the M0 conductors in cell 900F is similar to Figures 3A-3G The metal pattern configuration of column 311. In some embodiments, one or more advantages described herein may be achieved by one or more integrated circuit layouts including cell 900F and / or integrated circuit devices manufactured according to these integrated circuit layouts.

[0150] In some embodiments, at least one of the methods discussed above is performed, in whole or in part, by at least one EDA system. In some embodiments, the EDA system may be used as part of the design department of the IC manufacturing system discussed below.

[0151] Figure 10A block diagram of an electronic design automation (EDA) system 1000 according to some embodiments.

[0152] In some embodiments, EDA system 1000 includes an APR system. According to some embodiments, the design layout method described herein represents a wire routing arrangement according to one or more embodiments, which may be implemented using EDA system 1000, for example.

[0153] In some embodiments, the EDA system 1000 is a general-purpose computing device including a processor 1002 and a non-transitory computer-readable storage medium 1004. Among other things, the storage medium 1004 is encoded, i.e., stores, computer program code 1006, such as a set of executable instructions. The processor 1002 executes the instructions 1006 to represent (at least partially represent) an EDA tool that implements some or all of the methods described herein according to one or more embodiments (the processes and / or methods described below).

[0154] Processor 1002 is electrically coupled to computer-readable storage medium 1004 via bus 1008. Processor 1002 is also electrically coupled to I / O interface 1010 via bus 1008. Network interface 1012 is also electrically connected to processor 1002 via bus 1008. Network interface 1012 is connected to network 1014, enabling processor 1002 and computer-readable storage medium 1004 to be connected to external components via network 1014. Processor 1002 is used to execute computer program code 1006 encoded in computer-readable storage medium 1004 to enable system 1000 to perform some or all of the mentioned processes and / or methods. In one or more embodiments, processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0155] In one or more embodiments, the computer-readable storage medium 1004 is an electronic system, magnetic system, optical system, electromagnetic system, infrared system, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1004 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1004 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0156] In one or more embodiments, storage medium 1004 stores computer program code 1006, which enables system 1000 (where such execution (at least partially) represents an EDA tool) to perform part or all of the process and / or method. In one or more embodiments, storage medium 1004 also stores information that facilitates the execution of part or all of the mentioned process and / or method. In one or more embodiments, storage medium 1004 stores a standard cell library 1007, which includes the standard cells disclosed herein.

[0157] EDA system 1000 includes an I / O interface 1010. The I / O interface 1010 is coupled to external circuitry. In one or more embodiments, the I / O interface 1010 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to hardware processor 1002.

[0158] EDA system 1000 also includes a network interface 1012 coupled to processor 1002. Network interface 1012 allows system 1000 to communicate with network 1014, to which one or more other computer systems are connected. Network interface 1012 includes a wireless network interface such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface such as Ethernet, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more systems 1000.

[0159] System 1000 is configured to receive information via I / O interface 1010. The information received via I / O interface 1010 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1002. The information is transmitted to processor 1002 via bus 1008. EDA system 1000 is configured to receive information related to the user interface (UI) via I / O interface 1010. This information is stored as user interface (UI) 1042 in computer-readable storage medium 1004.

[0160] In some embodiments, some or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application used by EDA system 1000. In some embodiments, the layout of integrated circuits including standard cells uses, for example, software available from the CADENCE DESIGN SYSTEMS division. Use a tool or another suitable layout generator to generate it.

[0161] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of the following: optical discs, such as DVDs; magnetic disks, such as hard disks; semiconductor memory, such as ROM, RAM, memory cards; and the like.

[0162] Figure 11 This is a block diagram of an integrated circuit (IC) manufacturing system 1100 and associated IC manufacturing processes according to some embodiments. In some embodiments, based on an integrated circuit layout, the manufacturing system 1100 manufactures at least one of the following: (A) one or more semiconductor photomasks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0163] exist Figure 11In this IC manufacturing system 1100, entities such as a design department 1120, a photomask department 1130, and an IC manufacturer / fabrication unit (“wafer department”) 1150 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of integrated circuit devices 1160. The entities in system 1100 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design department 1120, photomask department 1130, and IC wafer department 1150 are owned by a single larger department. In some embodiments, two or more of the design department 1120, photomask department 1130, and IC wafer department 1150 coexist in a common facility and use common resources.

[0164] Design department (or design team) 1120 generates IC design layout 1122. IC design layout 1122 includes various geometric patterns designed for integrated circuit device 1160. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the integrated circuit device 1160 to be manufactured. The various layers combine to form various IC features. For example, a portion of IC design layout 1122 includes various IC features, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, which will be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. Design department 1120 performs appropriate design procedures to form IC design layout 1122. Design procedures include one or more of logic design, physical design, or location and routing operations. IC design layout 1122 is presented in one or more data files containing geometric pattern information. For example, IC design layout 1122 may be expressed in GDSII file format or DFII file format.

[0165] The photomask department 1130 includes data preparation 1132 and photomask fabrication 1144. The photomask department 1130 uses an IC design layout 1122 to fabricate one or more photomasks 1145 for fabricating various layers of an integrated circuit device 1160 according to the IC design layout 1122. The photomask department 1130 performs photomask data preparation 1132, in which the IC design layout 1122 is converted into a representative data file (“RDF”). The photomask data preparation 1132 provides the RDF to the photomask fabrication 1144. The photomask fabrication 1144 includes a photomask writer. The photomask writer converts the RDF into an image on a substrate, such as photomask 1145 or semiconductor wafer 1153. The design layout 1122 is manipulated by the photomask data preparation 1132 to conform to the specific characteristics of the photomask writer and / or the requirements of the IC wafer department 1150. Figure 11 In this design, photomask data preparation 1132 and photomask fabrication 1144 are illustrated as separate components. In some embodiments, photomask data preparation 1132 and photomask fabrication 1144 may be collectively referred to as photomask data preparation.

[0166] In some embodiments, mask data preparation 1132 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that can cause self-diffraction, interference, other process effects, and the like. OPC adjustment IC design layout diagram 1122 is shown. In some embodiments, mask data preparation 1132 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masks, other suitable techniques, and combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0167] In some embodiments, mask data preparation 1132 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout 1122, which has already been processed in the OPC. This set of mask creation rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1122 to compensate for constraints during mask fabrication 1144, and can undo some modifications performed by the OPC to satisfy the mask creation rules.

[0168] In some embodiments, mask data preparation 1132 includes lithography process checking (LPC), a simulation of the process performed by the IC wafer division 1150 to manufacture integrated circuit device 1160. LPC simulates this process based on IC design layout 1122 to create a simulated fabricated device, such as integrated circuit device 1160. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other appropriate factors, and similar or combinations thereof. In some embodiments, after LPC has created the simulated fabricated device, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further improve the IC design layout 1122.

[0169] It should be understood that, for clarity, the above description of photomask data preparation 1132 has been simplified. In some embodiments, data preparation 1132 includes additional features such as logic operations (LOPs) to modify the IC design layout 1122 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1122 during data preparation 1132 can be performed in various different sequences.

[0170] Following photomask data preparation 1132 and during photomask fabrication 1144, a photomask 1145 or a set of photomasks 1145 is fabricated based on a modified IC design layout 1122. In some embodiments, photomask fabrication 1144 includes performing one or more photolithographic exposures based on the IC design layout 1122. In some embodiments, a mechanism of electron beams (e-beams) or multiple electron beams is used to form a pattern on the photomask (or mask) 1145 based on the modified IC design layout 1122. The photomask 1145 is formed using various techniques. In some embodiments, a binary technique is used to form the photomask 1145. In some embodiments, the photomask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque areas and transmits through the transparent areas. In one example, the binary photomask version of photomask 1145 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary photomask. In another example, photomask 1145 is formed using a phase-shifting technique. In the phase-shift mask (PSM) version of photomask 1145, various features in the pattern formed on the phase-shift mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shift mask can be an attenuation-type phase-shift mask or an alternating-type phase-shift mask. The photomask(s) generated by photomask fabrication 1144 are used in various processes. For example, such photomask(s) are used in ion implantation processes to form various doped regions in semiconductor wafer 1153, in etching processes to form various etched regions in semiconductor wafer 1153, and / or in other suitable processes.

[0171] The IC fab 1150 family includes an IC manufacturing company comprising one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, the IC fab 1150 family refers to a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end-of-line, FEOL) of multiple IC products, a second manufacturing facility for back-end manufacturing (back-end-of-line, BEOL) for interconnecting and packaging IC products, and a third manufacturing facility for other services provided by the foundry company.

[0172] IC fab 1150 includes manufacturing tool 1152 configured to perform various manufacturing operations on semiconductor wafer 1153 to manufacture IC device 1160 based on a photomask (e.g., photomask 1145). In various embodiments, manufacturing tool 1152 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., chemical vapor deposition (CVD) chamber or low-pressure chemical vapor deposition (LPCVD) furnace), chemical mechanical polishing (CMP) system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable processes as discussed herein.

[0173] IC fab 1150 uses photomask 1145, manufactured by photomask department 1130, to fabricate IC device 1160. Therefore, IC fab 1150 uses IC design layout 1122 at least indirectly to fabricate IC device 1160. In some embodiments, semiconductor wafer 1153 is fabricated by IC fab 1150 using photomask 1145 to form IC device 1160. In some embodiments, IC fabrication includes performing one or more lithography exposures at least indirectly based on IC design layout 1122. Semiconductor wafer 1153 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 1153 further includes one or more of various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent fabrication steps).

[0174] In some embodiments, an integrated circuit (IC) device includes a plurality of columns of semiconductor devices and a metal layer. The plurality of columns extend along a first axis and are arranged side-by-side along a second axis perpendicular to the first axis. The metal layer includes a plurality of conductors arranged along a plurality of tracks extending along the first axis. Each of the plurality of columns includes a first active region of a first conductivity type and a second active region of a second conductivity type different from the first active region, the second active region being spaced apart from the first active region along the second axis. The plurality of columns includes a first column and a second column having the same first height along the second axis. The plurality of tracks includes a first track in the first column and a second track in the second column. A first number of first tracks differs from a second number of second tracks.

[0175] In some embodiments, the integrated circuit device includes multiple metal layers. The metal layers are located on the front or back side of the integrated circuit device, closest to the first active region and the second active region.

[0176] In some embodiments, the plurality of conductors includes a plurality of first conductors arranged along the plurality of first tracks and a plurality of second conductors arranged along the plurality of second tracks. In some embodiments, along a second axis, the plurality of first conductors have a first width, and the plurality of second conductors have a second width. The second width is different from the first width. In some embodiments, along the second axis, the plurality of first conductors are spaced apart from each other by a first spacing, and the plurality of second conductors are spaced apart from each other by a second spacing. The second spacing is different from the first spacing. In some embodiments, the integrated circuit device further includes a first via electrically coupled to the plurality of first conductors and having a first via size, and a second via electrically coupled to the plurality of second conductors and having a second via size. The second via size is different from the first via size.

[0177] In some embodiments, the plurality of conductors includes a plurality of power rails. The plurality of first rails in a first column are arranged between a first pair of adjacent power rails. The second rails in a second column are arranged between a second pair of adjacent power rails. The plurality of conductors includes a plurality of first conductors arranged along the plurality of first rails and a plurality of second conductors arranged along the plurality of second rails. In some embodiments, along a second axis, the plurality of first conductors have a first width, and the plurality of second conductors have a second width, the second width being different from the first width. In some embodiments, along the second axis, the plurality of first conductors are spaced apart from each other by a first spacing, and the plurality of second conductors are spaced apart from each other by a second spacing. The second spacing is different from the first spacing. In some embodiments, along the second axis, one of the first pair of adjacent power rails has a first power rail width, and one of the second pair of adjacent power rails has a second power rail width. The second power rail width is different from the first power rail width. In some embodiments, the integrated circuit device further includes a plurality of first vias electrically coupled to the plurality of first conductors and having a first via size, and a plurality of second vias electrically coupled to the plurality of second conductors and having a second via size, wherein the second via size is different from the first via size.

[0178] In some embodiments, the plurality of conductors includes a plurality of first conductors arranged along the plurality of first tracks and a plurality of second conductors arranged along the plurality of second tracks. Along a second axis, the plurality of first conductors have a first width and are spaced apart from each other by a first spacing. The plurality of second conductors includes at least one second conductor having a second width along the second axis and a pair of adjacent second conductors. The second width is greater than the first width and is spaced apart from each other by a second spacing. The second spacing is different from the first spacing.

[0179] In some embodiments, the at least one second conductor includes the output of a circuit of an integrated circuit device. At least one of the pair of adjacent second conductors includes an input of a circuit and has a width along a second axis that is less than the second width.

[0180] In some embodiments, the plurality of columns comprise a repeating pattern of a column set along a second axis. The column set includes a first column and a second column.

[0181] In some embodiments, the plurality of columns comprises a repeating pattern of a column set along a second axis. The column set includes a first column subset and a second column subset. Each of the first column subsets has a first height and a first number of tracks among the plurality of tracks along the second axis. The first column subset includes a first column. Each of the second column subsets has a first height and a second number of tracks among the plurality of tracks along the second axis. The second column subset includes a second column.

[0182] In some embodiments, the number of columns in the first subset is equal to the number of columns in the second subset.

[0183] In some embodiments, the number of columns in the first subset is different from the number of columns in the second subset.

[0184] In some embodiments, the plurality of columns comprise a repeating pattern of a column set along a second axis. The column set includes a first column, a second column, and a third column. The third column has a first height along the second axis. The plurality of tracks also includes a plurality of third tracks within the third column. The third number of the plurality of third tracks differs from the first number of the first track and the second number of the second track.

[0185] In some embodiments, the plurality of columns comprise a repeating pattern of a column set along a second axis. The column set includes a first column, a second column, and a third column. The third column has a second height along the second axis. The second height differs from the first height.

[0186] In some embodiments, the column set further includes a fourth column. The fourth column has a second height along the second axis. The plurality of tracks also includes a plurality of third tracks in the third column and a plurality of fourth tracks in the fourth column. The third number of the third plurality of tracks differs from the fourth number of the fourth plurality of tracks.

[0187] In some embodiments, the plurality of conductors includes a plurality of first conductors arranged along the plurality of first tracks and a plurality of second conductors arranged along the plurality of second tracks. Semiconductor devices in a first column are electrically coupled to form a first circuit via the plurality of first conductors. Semiconductor devices in a second column are electrically coupled to form a second circuit via the plurality of second conductors, the second circuit being different from the first circuit. A first number of first tracks in the first column is greater than a second number of second tracks in the second column. The number of the plurality of first conductors in the first circuit is greater than the number of the plurality of second conductors in the second circuit.

[0188] In some embodiments, a method of manufacturing an integrated circuit (IC) device includes forming a plurality of semiconductor devices on a front side of a substrate, and depositing a metal layer on the substrate and patterning the metal layer. The patterned metal layer includes a plurality of power rails extending along a first axis and spaced apart from each other by a first height along a second axis perpendicular to the first axis, and a plurality of conductors arranged between the plurality of power rails and electrically coupling the plurality of semiconductor devices into a plurality of circuits of the IC device. The plurality of conductors includes a first conductor between a first pair of adjacent power rails in the plurality of power rails, and a second conductor between a second pair of adjacent power rails in the plurality of power rails. The metal layer includes at least one of the following: (a) the first conductor has a first number of rails along which it is arranged, and the second conductor has a second number of rails along which it is arranged; (b) along the second axis, the first conductor has a first width, and the second conductor has a second width different from the first width; (c) along the second axis, the first conductors are spaced apart from each other by a first spacing, and the second conductors are spaced apart from each other by a second spacing different from the first spacing; or (d) along the second axis, the first power rail in the first pair of adjacent power rails has a first power rail width, and the second power rail in the second pair of adjacent power rails has a second power rail width different from the first power rail width.

[0189] In some embodiments, a plurality of metal layers are deposited and patterned on a front or back side of a substrate, with the back side relative to the front side in the thickness direction of the substrate. Of the plurality of metal layers, the metal layer is closest to the plurality of semiconductor devices.

[0190] In some embodiments, the method further includes: forming a plurality of first vias electrically coupled to the plurality of first conductors and a plurality of second vias electrically coupled to the plurality of second conductors, wherein the first via size of the first vias is different from the second via size of the second vias.

[0191] In some embodiments, the plurality of second conductors includes at least one second conductor having a second width greater than the first width along the second axis and a pair of adjacent second conductors.

[0192] In some embodiments, a method is at least partially executed by a processor, the method comprising: in response to a predetermined threshold number of interconnects in an integrated circuit (IC) device layout, obtaining a first layout of cells and storing the first layout in a cell library on a non-transitory computer-readable storage medium. The first layout has a first height and a first number of metal-zero (M0) tracks in the first layout. The method further comprises: in response to a predetermined threshold number of interconnects in the cells not exceeding the second threshold, obtaining a second layout and a third layout of cells. The second layout has a first height and a second number of M0 tracks in the second layout, the second number being less than the first number. The third layout has a first height and a third number of M0 tracks in the third layout, the third number being less than the second number. The method further comprises storing at least one of the second or third layouts in the cell library.

[0193] In some embodiments, obtaining at least one of the first layout, the second layout, or the third layout includes arranging first to third conductors correspondingly along a first to a third metal zero-layer track. A second metal zero-layer track is located between and adjacent to the first and third metal zero-layer tracks. The first conductor has a first width greater than a second width of the second and third conductors, and the first conductor corresponds to the output of the unit. A first spacing between the first and second conductors is less than a second spacing between the second and third conductors. At least one of the second or third conductors corresponds to the input of the unit.

[0194] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can use this disclosure as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications to this document without departing from its spirit and scope.

Claims

1. An integrated circuit device, characterized in that, The integrated circuit device includes: A plurality of columns of semiconductor devices, the plurality of columns extending along a first axis and arranged side-by-side along a second axis perpendicular to the first axis; and The metal layer includes a plurality of conductors arranged along a plurality of tracks extending along the first axis. in Each of the plurality of columns includes: The first active region of the first conductivity type, and A second active region of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, is spaced apart from the first active region along the second axis. The plurality of columns includes a first column and a second column having the same first height along the second axis. The plurality of tracks includes a plurality of first tracks in the first column and a plurality of second tracks in the second column, and The first number of the plurality of first tracks is different from the second number of the plurality of second tracks.

2. The integrated circuit device according to claim 1, characterized in that... The plurality of conductors includes: A plurality of first conductors arranged along the plurality of first tracks, and A plurality of second conductors arranged along the plurality of second orbits, and In at least one of the following aspects: Along the second axis, the plurality of first conductors have a first width, and the plurality of second conductors have a second width, the second width being different from the first width. Along the second axis, the plurality of first conductors are spaced apart by a first gap, and the plurality of second conductors are spaced apart by a second gap, the second gap being different from the first gap, or The integrated circuit device further includes a first via electrically coupled to the plurality of first conductors and having a first via size, and a second via electrically coupled to the plurality of second conductors and having a second via size, wherein the second via size is different from the first via size.

3. The integrated circuit device according to claim 1, characterized in that... The plurality of conductors includes a plurality of power rails. The plurality of first tracks in the first column are arranged between a first pair of adjacent power tracks among the plurality of power tracks. The second track in the second column is arranged between the second pair of adjacent power rails among the plurality of power rails. The plurality of conductors includes: A plurality of first conductors arranged along the plurality of first tracks, and A plurality of second conductors arranged along the plurality of second orbits, and In at least one of the following aspects: Along the second axis, the plurality of first conductors have a first width, and the plurality of second conductors have a second width, the second width being different from the first width. Along the second axis, the plurality of first conductors are spaced apart by a first gap, and the plurality of second conductors are spaced apart by a second gap, the second gap being different from the first gap. Along the second axis, a first power rail in the first pair of adjacent power rails has a first power rail width, and a second power rail in the second pair of adjacent power rails has a second power rail width, the second power rail width being different from the first power rail width, or The integrated circuit device further includes a plurality of first vias electrically coupled to the plurality of first conductors and having a first via size, and a plurality of second vias electrically coupled to the plurality of second conductors and having a second via size, wherein the second via size is different from the first via size.

4. The integrated circuit device according to claim 1, characterized in that... The plurality of conductors includes: A plurality of first conductors arranged along the plurality of first tracks, and Multiple second conductors arranged along the multiple second orbits, Along the second axis, the plurality of first conductors have a first width and are spaced apart from each other by a first spacing, and The plurality of second conductors includes: At least one second conductor having a second width along the second axis, the second width being greater than the first width, and A pair of adjacent second conductors are separated from each other by a second gap, which is different from the first gap.

5. The integrated circuit device according to claim 1, characterized in that... The plurality of columns comprise a repeating pattern of column sets along the second axis, and The column set includes the first column and the second column.

6. The integrated circuit device according to claim 1, characterized in that... The plurality of columns comprise a repeating pattern of column sets along the second axis, and The column set includes: A first subset of columns, each having the first height along the second axis and a first number of tracks from the plurality of tracks, wherein the first subset of columns includes the first column, and The second subset comprises a plurality of tracks along the second axis having the first height and the second number of the plurality of tracks, wherein the second subset includes the second column.

7. The integrated circuit device according to claim 1, characterized in that... The plurality of columns comprises a repeating pattern of column sets along the second axis. The column set includes: The first column, The second column, and The third column, having the first height along the second axis. The plurality of tracks also includes a plurality of third tracks in the third column, and The third quantity of the plurality of third tracks is different from the first quantity of the first track and the second quantity of the second track.

8. The integrated circuit device according to claim 1, characterized in that... The plurality of columns comprises a repeating pattern of column sets along the second axis. The column set includes: The first column, The second column, and The third column has a second height along the second axis, which is different from the first height.

9. The integrated circuit device according to claim 8, characterized in that... The column set also includes: The fourth column, having the second height along the second axis, The plurality of tracks also includes a plurality of third tracks in the third column and a plurality of fourth tracks in the fourth column, and The third number of the third plurality of orbits is different from the fourth number of the fourth plurality of orbits.

10. The integrated circuit device according to claim 1, characterized in that... The plurality of conductors includes: A plurality of first conductors arranged along the plurality of first tracks, and Multiple second conductors arranged along the multiple second orbits, The semiconductor devices in the first column are electrically coupled to form a first circuit through the plurality of first conductors. The semiconductor devices in the second column are electrically coupled to form a second circuit via the plurality of second conductors. This second circuit differs from the first circuit. The first quantity of the first track in the first column is greater than the second quantity of the second track in the second column, and The number of the plurality of first conductors in the first circuit is greater than the number of the plurality of second conductors in the second circuit.

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