A chip timing convergence optimization system and method based on defect awareness

Abstract

The application discloses a chip timing convergence optimization system and method based on defect awareness. The system imports a manufacturing defect map and generates a reliability matrix to score a physical path; a defect awareness optimization engine dynamically sorts and optimizes a critical path in combination with the score; and a layout iteration module recalculates the score and adjusts a strategy according to an updated layout to realize collaborative optimization of timing convergence and defect avoidance. The application introduces manufacturing defect information into a timing optimization process to improve chip manufacturing yield while ensuring timing performance.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit back-end design and manufacturing optimization, and in particular relates to a chip timing convergence optimization system and method based on defect awareness, which is applicable to chip physical implementation and yield improvement under advanced process nodes. Background Technology

[0002] In integrated circuit design, especially in the back-end physical implementation of digital chips, timing closure is a core step in ensuring the correctness of chip functionality and performance, and is a key factor in determining whether the chip can be successfully tape-out and mass-produced. Current mainstream EDA tools, when performing STA (Simultaneous Step-Off), primarily rely on the resistance and capacitance parameters extracted from the design netlist and layout to model and optimize path delays. Typical operations include buffer insertion, gate-level replacement, and rerouting.

[0003] However, as process nodes continue to evolve to 5nm and below, the impact of physical fluctuations and defect distribution in the manufacturing process on chip performance and yield is becoming increasingly prominent. At advanced process nodes, existing timing convergence processes have significant shortcomings: 1. Failure to consider actual manufacturing defect distribution: STA (Signal-Side Execution) only sorts paths based on electrical models, without considering potential defect hotspots during manufacturing, ignoring physical failure risks; 2. Inappropriate optimization resource allocation: The lack of a path robustness evaluation mechanism may cause the optimizer to allocate resources to high-risk paths, actually increasing the failure rate. This can lead to seemingly STA-compliant paths exhibiting high failure rates during manufacturing, severely impacting chip yield and stability.

[0004] While some DFY tools have incorporated defect detection and process platform feedback, such as Foundry's PFA system, an effective coupling mechanism between defect maps and STA paths has not yet been established, and dynamic optimization methods for defect awareness are lacking. Therefore, there is an urgent need for a design method and system that can detect and mitigate physical defect risks in advance during the timing convergence phase.

[0005] Terminology Definition

[0006] STA (Static Timing Analysis): Static timing analysis evaluates signal propagation delay in digital circuits to ensure timing constraints are met.

[0007] Defect Map: A chip defect map that shows the distribution of physical areas prone to defects during historical manufacturing.

[0008] Physical Path: The physical path represents all signal transmission paths from the clock source to the register endpoint. It is the set of all physical connections that exist after placement and routing.

[0009] Critical Path: The most time-sensitive logical path, that is, the path with the smallest timing margin or the largest delay in STA analysis. It is a potential "bottleneck path" and a subset of the physical path.

[0010] Timing Closure: Timing closure refers to the fact that a design can be delivered after meeting functional correctness and timing requirements.

[0011] ML (Machine Learning): Machine Learning;

[0012] LVS (Layout vs. Schematic): Consistency check between layout and circuit structure. Summary of the Invention

[0013] The purpose of this invention is to overcome the shortcomings of the prior art and provide a chip timing convergence optimization system and method based on defect awareness. Its core idea is to introduce manufacturing defect distribution information as a key constraint into the path evaluation and optimization decision-making process of static timing analysis, thereby achieving synergy between timing performance optimization and manufacturing yield improvement.

[0014] The present invention is implemented as follows: Firstly, the present invention provides a defect-aware chip timing convergence optimization system, comprising:

[0015] The defect map import and modeling module is used to perform gridded modeling of the chip layout, calculate the defect probability or risk level of each grid cell, and generate a reliability matrix for the chip area. The reliability matrix is ​​a two-dimensional numerical structure that describes the defect risk distribution in the chip space, where each matrix element represents the reliability value of the corresponding area.

[0016] The path scoring module is used to calculate the proportion of high-defect areas traversed by each physical path in the chip layout using the reliability matrix, thereby obtaining a path score to quantify the manufacturing risk of the path.

[0017] The Defect-Aware Static Temporal Analysis (STA) optimization engine uses the path score as a spatial constraint to dynamically prioritize critical paths and perform temporal optimization operations based on the ranking results to prevent new paths from entering low-reliability areas and complete layout updates.

[0018] The layout iteration and feedback mechanism module is used to recalculate the path score of each physical path after the layout is updated, and dynamically adjust the optimization strategy to achieve synergistic optimization of timing convergence and defect avoidance.

[0019] Preferably, the path scoring employs robust scoring. More preferably, the robust scoring... The calculation is as follows:

[0020]

[0021] in Indicates the center coordinates as The reliability value of the area This indicates that the physical path P is at the center coordinates. The coverage length of the area, Let P be the total length of the physical path.

[0022] Preferably, the defect distribution data imported by the defect map import and modeling module comes from at least one of the manufacturing yield platform, process line feedback data, or on-chip sensor monitoring data.

[0023] Preferably, after obtaining the robustness score, the path scoring module further weights and fuses the robustness score with the corresponding path's DFM manufacturability score to generate a comprehensive scoring index, and uses the comprehensive scoring index as the final path score.

[0024] Secondly, the present invention provides a defect-aware chip timing convergence optimization method, comprising the following steps:

[0025] By performing a gridded model of the chip layout, the defect probability or risk level of each grid cell is calculated, thereby generating a reliability matrix for the chip region.

[0026] The proportion of high-defect regions traversed by each physical path in the chip layout is calculated using the reliability matrix, and then a path score is obtained.

[0027] During static time series analysis, the path score is used as a spatial constraint to dynamically prioritize critical paths and perform time series optimization based on the ranking results to prevent new paths from entering low reliability areas and complete layout updates.

[0028] After the layout is adjusted, the path score is recalculated and iteratively optimized until the time-series convergence requirements are met.

[0029] Thirdly, the present invention provides a method for improving chip yield, which involves optimizing chip timing convergence by applying the above-mentioned method to the chip layout.

[0030] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described thereon.

[0031] Fifthly, the present invention provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the program to describe the method thereon.

[0032] This invention introduces a defect distribution map from the manufacturing process and scores each physical path, enabling the system to quantify the manufacturing failure risk of each path. Based on this, during timing optimization, low-risk paths are prioritized for optimization, while high-risk paths are guided to avoid defect hotspots. This collaborative mechanism reduces the probability of critical paths failing due to manufacturing defects from the design stage, and field tests show it effectively improves overall chip yield. For example, at specific nodes (such as 5nm test chips), the path failure rate decreases by 18%, the overall yield improves by approximately 1.2%, path resource allocation is significantly optimized, ineffective optimization of high-risk paths is reduced, and design efficiency is improved.

[0033] This invention uses path scoring as an optimization constraint, enabling the defect-aware STA optimization engine to comprehensively balance timing urgency and defect risk. This avoids ineffective or harmful over-optimization of high-risk paths and intelligently directs valuable optimization resources to low-risk paths, thereby improving the efficiency of timing convergence and the quality of design iteration. Attached Figure Description

[0034] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a flowchart of the chip timing convergence optimization system provided in an embodiment of the present invention.

[0036] Figure 2 This is a diagram showing the overlay of the defect map and layout paths.

[0037] Figure 3 This is a comparison chart before and after path optimization.

[0038] Figure 4 This is a schematic diagram of the path robustness scoring mechanism. Detailed Implementation

[0039] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0040] like Figure 1 As shown, this embodiment of the invention provides a defect-aware chip timing convergence optimization system, which includes:

[0041] The defect map import and modeling module is used to perform gridded modeling of the chip layout, calculate the defect probability or risk level of each grid cell, and generate a reliability matrix for the chip region. This matrix represents the defect risk field of the entire chip. The reliability matrix is ​​a two-dimensional numerical structure describing the distribution of defect risk in the chip space, where each matrix element represents the reliability value of the corresponding region; the reliability value ranges from 0 to 1, with lower values ​​indicating higher risk.

[0042] This embodiment can receive and process raw defect distribution information from external yield management systems, process line test data, or on-chip monitoring units, such as chip defect maps provided by yield platforms or foundries. This data may exist in the form of GDSII layer stacks or coordinate lists. The above data sources are obtained through legal and compliant means.

[0043] In one embodiment, the specific implementation process of the defect map import and modeling module is as follows:

[0044] First, the chip layout area is divided into two-dimensional grid cells according to a preset resolution (e.g., 1μm×1μm or a variable grid size that is automatically adjusted according to the hierarchical structure), and a unique coordinate index (x, y) is assigned to each grid cell.

[0045] Then, based on the spatial density, defect type, and severity of each defect point in the defect distribution data of the imported chip defect map, the comprehensive defect probability value D(x, y) of each grid cell is calculated.

[0046] The probability of this defect can be obtained through the following weighted method:

[0047]

[0048] in:

[0049] N is the number of defect points that fall within the neighborhood of this grid;

[0050] This represents the Euclidean distance from the k-th defect point to the center of the mesh.

[0051] This is a spatial diffusion parameter used to control the range of defect influence;

[0052] The weights for defect types, such as photolithography defects and etching residues, can be predefined by process engineers.

[0053] Calculated The value ranges from 0 to 1, with higher values ​​indicating a greater probability of defects occurring.

[0054] Finally, the defect probability is mapped inversely to the reliability value R(x, y);

[0055]

[0056] A two-dimensional reliability matrix for the entire chip region is formed using the reliability values ​​R(x, y). This matrix can be viewed as a "spatial reliability heatmap", where high reliability regions (R(x,y) close to 1) correspond to regions with low manufacturing risk, and low reliability regions (R(x,y) close to 0) correspond to regions with concentrated defects.

[0057] This reliability matrix will serve as input data for the subsequent "path scoring module," used to calculate the weighted robustness score of each physical path when it traverses different risk areas, thus achieving a quantitative mapping from defect distribution to path risk assessment.

[0058] Therefore, by probabilistically modeling the spatial distribution of defects, the reliability matrix transforms unstructured defect map data into a computable two-dimensional weight field, providing a precise risk quantification basis for subsequent path robustness analysis and optimization.

[0059] The path scoring module uses the reliability matrix to calculate the proportion of high-defect regions traversed by each physical path in the chip layout, thereby obtaining a path score to quantify the manufacturing risk of that path. The reliability matrix provides the path scoring module with spatially distributed defect risk weight information.

[0060] Specifically, after performing routine initial placement and routing and STAR, all physical paths to be analyzed are extracted from the post-placement design. For each physical path, it is discretized into a series of line segments, and the coverage ratio of high-defect areas traversed by each line segment is calculated (see [link to documentation]). Figure 2 Then, the path score of the path is calculated.

[0061] In one embodiment, the path scoring uses only robustness scoring. Robustness scoring quantifies the inherent sensitivity of the path to manufacturing defects, laying the groundwork for subsequent time-series path configurations that tolerate physical failures and enhancing system robustness.

[0062] The robustness score It is calculated by taking a reliability-weighted average of the physical path through each region, as follows:

[0063]

[0064] in Indicates the center coordinates as The reliability value of the area This indicates that the physical path P is at the center coordinates. The coverage length of the area, The total length of the physical path P. A higher robustness score indicates a greater risk of the path being affected by defect distribution; the score can be used as a reference indicator for path optimization priority.

[0065] See appendix Figure 4 , attached Figure 4 A schematic diagram illustrating the calculation principle of path robustness scoring is shown. In this diagram, the chip layout area is divided into several grid cells, each corresponding to a reliability value generated by the "Defect Map Import and Modeling Module". Darker colors indicate lower reliability and higher defect risk; lighter colors indicate higher reliability and lower manufacturing risk. The physical path P is typically distributed in the layout as a wire, and its spatial trajectory may traverse multiple high-defect areas. (Appendix) Figure 4 The solid lines in the diagram illustrate different paths passing through high-defect areas. The system discretizes the paths into several line segments and calculates their coverage length or area in each high-defect area, while also extracting the defect level of that area (derived from the reliability matrix).

[0066] Therefore, the more defect-risk areas a path traverses, the higher its robustness score and the greater the manufacturing risk; conversely, the lower the robustness score and the stronger the robustness when a path avoids high-risk areas.

[0067] In another embodiment, the path scoring is based not only on the aforementioned robustness score (R p Furthermore, a Design for Manufacturability (DFM) score can be incorporated for integrated calculation to form a comprehensive score index, which can then be used as a path score. This DFM manufacturability score measures the feasibility, process consistency, and controllability of the physical path in the layout manufacturing process, thereby simultaneously considering manufacturing yield and design performance during the timing optimization process.

[0068] Specifically, the DFM Manufacturability Score (DFM_Score) can be summarized by the following three types of manufacturability indicators:

[0069] (1) Lithography Feasibility Index (S_litho): This index characterizes the process window width and proximity effect in the lithography imaging process of the path region. Its calculation method can be expressed as:

[0070]

[0071] Where E_OPC represents the mean optical proximity correction error in the path region, and E_max is the maximum acceptable error value for the process. The larger the S_litho value, the better the lithographic consistency and process stability in that region.

[0072] (2) Geometric complexity index (S_geo): Used to measure the geometric complexity, line width fluctuation and spacing changes in the region adjacent to the path. The calculation formula is as follows:

[0073] S_geo = 1 - (C_layout / C_ref)

[0074] Where C_layout represents the geometric complexity factor of this region (calculated from the boundary change rate and wiring density), and C_ref is the reference standard complexity value. The larger the S_geo value, the more regular the layout structure and the better the manufacturability.

[0075] (3) Process stability index (S_proc): used to reflect the repeatability and uniformity of the area where the path is located in the manufacturing process of multiple batches, and can be defined as:

[0076] S_proc = Y_local / Y_nominal

[0077] Where Y_local is the local average yield of the region, and Y_nominal is the target process yield. The closer this ratio is to 1, the smaller the manufacturing fluctuation in the region.

[0078] In summary, the DFM manufacturability score can be defined by the following weighted model:

[0079] DFM_Score(P) = α·S_litho + β·S_geo + γ·S_proc

[0080] Here, α, β, and γ are weighting coefficients, which are adjusted according to different process nodes (such as 5nm, 3nm) and circuit types (logic circuits, memory cells, etc.). The higher the score, the lower the manufacturing risk and the stronger the manufacturability of the path.

[0081] Furthermore, the present invention will use robustness scoring (R... p The final path score (Final_Score) is fused with the DFM manufacturability score to form a comprehensive path score, which is used as the path priority input for the defect-aware STA optimization engine. The fusion relationship can be defined as follows:

[0082] Final_Score(P) = w1·R_P + w2·(1 - DFM_Score(P))

[0083] Here, w1 and w2 are the weight parameters for robustness and manufacturability scores, respectively, and can be adaptively adjusted based on experimental data. This comprehensive scoring mechanism enables the optimization process to maintain temporal performance while effectively avoiding high-defect-risk areas in manufacturing, achieving synergistic optimization of temporal convergence and process yield.

[0084] The Defect-Aware STA Optimization Engine, as the core optimization controller of the system, receives and parses scoring data from the path scoring module, building upon the traditional Static Time Series Analysis (STA) process. This engine uses the path scores as spatial constraints to dynamically prioritize critical paths and performs time series optimization operations based on the ranking results. This prevents new paths from entering low-reliability regions and completes layout updates. The Defect-Aware STA Optimization Engine prioritizes time series optimization operations on paths with low defect risk. If the path scoring only uses robustness scoring, which quantifies the defect risk level of a path, a higher score indicates a greater risk of the path being affected by defects. Therefore, the Defect-Aware STA Optimization Engine prioritizes performing time series optimization operations on paths with lower robustness scores (i.e., lower defect risk).

[0085] Specifically, the optimization engine does not directly perform timing optimization on all physical paths. Instead, it uses the path scores as spatial constraints and identifies a set of critical paths (CPath Set) through Static Timing Analysis (STA). These CPath Sets are the paths with the smallest timing margins or the longest delays. Based on this, the defect-aware STA optimization engine combines the path score results with the STA analysis results to dynamically prioritize the critical paths within the Critical Path Set. The prioritization considers both timing slack and defect risk (represented by the path score). For example, the path score uses only a robustness score to quantify the defect risk of a path. A lower robustness score indicates a smaller proportion of high-defect areas traversed by the path and a lower risk of being affected by manufacturing fluctuations. The optimization engine prioritizes performing optimization operations on critical paths with lower defect risk (determined by the path score), such as buffer insertion, gate replacement, or rerouting. This ensures timing convergence efficiency while avoiding the introduction of new devices or traces in high-risk areas, minimizing the risk of introducing new defects during the optimization process. For paths located in high-defect-risk regions (e.g., paths with high robustness scores), the optimization engine can employ more conservative optimization strategies. These include reducing cell replacements in these regions, limiting trace density, or prioritizing inter-layer switching to avoid defect hotspots, thus preventing the generation of new failure points within defect-concentrated areas. Through this mechanism, the optimization engine achieves a synergistic balance between performance improvement and defect avoidance during timing convergence, enabling the chip to significantly improve manufacturing yield and reliability while meeting timing requirements.

[0086] Therefore, by introducing path scoring constraints, this invention enables the defect-aware STA optimization engine to automatically distinguish the defect risk level of a path in the optimization decision-making process, thereby prioritizing the optimization of low-risk paths and avoiding the risks of high-risk paths, while taking into account both timing performance and manufacturing feasibility.

[0087] See the comparison results of the optimization engine before and after path optimization. Figure 3 For paths within high-defect-risk regions, the system may tend to employ optimization operations with minimal impact on local device density, such as moderate gate-level replacement (selecting standard cells with better driving capabilities) or cross-layer rewiring (migrating some signals to lower-risk metal layers), to reduce the likelihood of introducing new manufacturing defects in high-risk regions. Conversely, for paths within low-defect-risk regions, more aggressive timing optimization techniques can be used, such as buffer insertion, driver enhancement, or line length optimization, to accelerate timing convergence. Through these methods, the optimization engine can effectively avoid high-risk regions while ensuring global timing constraints are met, thereby achieving a dynamic balance between timing performance optimization and manufacturing reliability.

[0088] The layout iteration and feedback mechanism module supports multiple rounds of optimization iterations. Whenever the layout changes due to optimization operations (e.g., the insertion of a buffer causing routing changes) or updated defect map data is imported, the path scoring module recalculates the path score, and the defect-aware STA optimization engine adjusts its optimization direction accordingly. After each optimization, the layout iteration and feedback module re-references the reliability matrix to update the path risk assessment in real time, achieving dynamic closed-loop optimization. This closed-loop mechanism ensures that while the design converges towards the time-series objective, its physical implementation continuously evolves towards a low-defect-risk region.

[0089] In another embodiment, the path scoring module can also be implemented using a pre-trained machine learning model.

[0090] Preferably, the model can employ a graph neural network (GNN), an attention mechanism model, or a combination thereof.

[0091] The model takes the topological characteristics of the path, the type and size of the logical units it passes through, the surrounding wiring congestion information, and the defect score of the area as input.

[0092] By learning the mapping relationship between historical manufacturing data and path failure rates, the predicted failure probability or robustness score of the path is output.

[0093] Compared to traditional path scoring methods based on geometric statistics, this embodiment utilizes a machine learning model to automatically capture complex spatial and semantic association features.

[0094] This establishes a more accurate correlation between high-dimensional design parameters and defect distribution, improving the accuracy and generalization ability of path scoring.

[0095] Provides a physical layout of the chip after placement and routing. High-defect regions, or "Defect Zones," represent physical locations historically or predicted to be prone to process defects. (See attached...) Figure 2 As can be seen, the original path directly traverses multiple high-defect areas, and its physical implementation may unfortunately fall into a high-risk manufacturing zone. This invention, through analysis of the defect map and the original path, systematically identifies high-risk sections. The optimization goal is to migrate the physical trajectory of the path from defect-dense areas to relatively "clean" areas, which requires the following adjustments: the total path length may be slightly increased, or the topology may need adjustment.

[0096] See appendix Figure 3 In (a), the original path before optimization directly traversed the core defect area; see appendix. Figure 3In section (b), the path optimized by this invention undergoes a significant change, actively bypassing the core defect area. The new path may manifest as: partial detour: finding a "corridor" with lower defect density near the original high-risk section; inter-layer switching: switching the routing to another metal layer by adding vias, bypassing the defect area from above or below; topology reconfiguration: the starting or ending point of the path remains unchanged, but the units passed through and the routing sequence are adjusted to completely avoid the risk area. These operations reduce the manufacturing risk score of the path, thereby improving its robustness.

[0097] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A defect-aware chip timing convergence optimization system, characterized in that, include: The defect map import and modeling module is used to generate a reliability matrix for the chip area by performing gridded modeling of the chip layout and calculating the defect probability or risk level of each grid cell. The path scoring module is used to calculate the proportion of high-defect areas traversed by each physical path in the chip layout using the reliability matrix, thereby obtaining a path score to quantify the manufacturing risk of the path. The defect-aware static time-series analysis and optimization engine is used to use the path score as a spatial constraint to dynamically prioritize critical paths and perform time-series optimization operations based on the ranking results, thereby preventing new paths from entering low-reliability areas and completing layout updates. The layout iteration and feedback mechanism module is used to recalculate the path score of each physical path after the layout is updated, and dynamically adjust the optimization strategy to achieve synergistic optimization of timing convergence and defect avoidance.

2. The system according to claim 1, characterized in that, The path scoring uses a robust scoring method.

3. The system according to claim 2, characterized in that, The robustness score The calculation is as follows:

4. Among them Indicates the center coordinates as The reliability value of the area This indicates that the physical path P is at the center coordinates. The coverage length of the area, Let P be the total length of the physical path.

5. The system according to claim 1, characterized in that, The timing optimization operations performed by the defect-aware static timing analysis and optimization engine include at least one of the following: buffer insertion, gate-level replacement, and rerouting.

6. The system according to claim 2, characterized in that, The defect-aware static timing analysis and optimization engine prioritizes timing optimization operations on paths with low defect risk.

7. The system according to claim 2, characterized in that, After obtaining the robustness score, the path scoring module also performs a weighted fusion of the robustness score and the corresponding path's DFM manufacturability score to generate a comprehensive scoring index, and uses the comprehensive scoring index as the final path score.

8. A defect-aware chip timing convergence optimization method, based on the system described in claims 1-6, characterized in that, Includes the following steps: By performing a gridded model of the chip layout, the defect probability or risk level of each grid cell is calculated, thereby generating a reliability matrix for the chip region. The proportion of high-defect regions traversed by each physical path in the chip layout is calculated using the reliability matrix, and then a path score is obtained. During static time series analysis, the path score is used as a spatial constraint to dynamically prioritize critical paths and perform time series optimization based on the ranking results to prevent new paths from entering low reliability areas and complete layout updates. After the layout is adjusted, the path score is recalculated and iteratively optimized until the time-series convergence requirements are met.

9. A method for improving chip yield, characterized in that, The chip layout is optimized for chip timing convergence using the method described in claim 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 7-8.

11. An electronic device, characterized in that, It includes a memory and a processor, the memory storing a computer program, and the processor executing the program to implement the method as described in any one of claims 7-8.

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