A multi-path power supply priority switching circuit and electronic device
The multi-power priority switching circuit, designed entirely with hardware, overcomes the shortcomings of existing power priority control technologies, achieving efficient and stable power switching, improving the reliability and real-time performance of the power supply system, and reducing control costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- NANCHANG HUAQIN ELECTRONIC TECH CO LTD
- Filing Date
- 2025-06-25
- Publication Date
- 2026-06-16
Smart Images
Figure CN224367583U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of power switching technology, and in particular to a multi-channel power priority switching circuit and electronic device. Background Technology
[0002] With the continuous development of the industry, the demand for power supply interfaces for various products has shown a significant upward trend, and the types of power supply interfaces are also constantly increasing. In some products, the traditional two-way power switching function can no longer fully meet the increasingly complex and diverse actual use scenarios. Some products even need to have three or more power switching functions to adapt to different usage needs. For example, in the current design of POS machines, multiple power supply methods have emerged, including POGO, DC, TYPE-C, and Y cable.
[0003] Currently, existing products mainly implement multi-channel power supply functions in the following two ways:
[0004] (1) Structural error prevention: The power supply priority is controlled by physically blocking the interface at the structural end. However, in actual development, due to various limitations, it is difficult to fully realize the expected priority control function through physical blocking.
[0005] (2) Software control: Various control methods are used through the I / O ports, such as controlling the conduction or cutoff of MOSFETs, or controlling the on / off of different OVP circuits through the I / O ports, to achieve power supply priority control. However, in actual development, the software control scheme has certain shortcomings in terms of reliability, determinism and real-time performance compared to the pure hardware scheme, and its control cost is relatively high.
[0006] In view of the above, in order to better meet the product's requirements for multi-power supply functions, improve the reliability, determinism and real-time performance of the power supply system, and reduce control costs, it is necessary to improve and optimize the existing technology.
[0007] The above information is provided as background information only to aid in understanding this disclosure and does not constitute an assertion or admission that any of the above content can be used as prior art relative to this disclosure. Utility Model Content
[0008] This invention provides a multi-channel power supply priority switching circuit and electronic device, which can effectively solve the shortcomings of existing multi-channel power supply priority control, improve the reliability, determinism and real-time performance of the power supply system, and reduce control costs.
[0009] To achieve the above objectives, this utility model provides the following technical solution:
[0010] In a first aspect, this utility model provides a multi-power priority switching circuit, including a first power input terminal, a second power input terminal, a third power input terminal, a first power branch, a second power branch, a third power branch, and a power output terminal.
[0011] The first power input terminal has the highest input voltage, and the second power input terminal has the same input voltage as the third power input terminal.
[0012] The first power input terminal is connected to the power output terminal through the first power branch, the second power input terminal is connected to the power output terminal, the first power branch and the third power branch through the second power branch, and the third power input terminal is connected to the power output terminal through the third power branch.
[0013] When only one of the first power input terminal, the second power input terminal, and the third power input terminal is powered, the output voltage of the power output terminal is equal to the input voltage of the corresponding input terminal.
[0014] When the first power input terminal and the second power input terminal are powered simultaneously, the first power branch is turned on, and the second power branch is turned off because it receives the input voltage of the first power branch. The output voltage of the power output terminal is equal to the input voltage of the first power input terminal.
[0015] When the first power input terminal and the third power input terminal are powered at the same time, the first power branch is turned on and the third power branch is turned on. However, since the input voltage of the first power input terminal is greater than the input voltage of the third power input terminal, the output voltage of the power output terminal is equal to the input voltage of the first power input terminal.
[0016] When the second power input terminal and the third power input terminal are powered simultaneously, the second power branch is turned on, and the third power branch is turned off due to receiving the input voltage of the second power branch. The output voltage of the power output terminal is equal to the input voltage of the second power input terminal.
[0017] Furthermore, in the multi-power priority switching circuit, the first power branch includes diode D1;
[0018] The positive terminal of diode D1 is connected to the first power input terminal, and the negative terminal of diode D1 is connected to the power output terminal.
[0019] Furthermore, in the multi-power priority switching circuit, the third power supply branch includes a third PMOS transistor T3 and a fourth PMOS transistor T4.
[0020] The drain (D) of the third PMOS transistor T3 is connected to the third power input terminal, and the source (S) of the third PMOS transistor T3 is connected to the source (S) of the fourth PMOS transistor T4.
[0021] The drain of the fourth PMOS transistor T4 is connected to the power output terminal.
[0022] The gate (G) of the third PMOS transistor T3 and the gate (G) of the fourth PMOS transistor T4 are respectively connected to the second power supply branch.
[0023] Furthermore, in the multi-power priority switching circuit, the second power supply branch includes a fifth PMOS transistor T5, a first NMOS transistor T1, and a second NMOS transistor T2;
[0024] The drain (D) of the fifth PMOS transistor T5 is connected to the second power input terminal, the source (S) of the fifth PMOS transistor T5 is connected to the power output terminal, and the gate (G) of the fifth PMOS transistor T5 is connected to the first power input terminal.
[0025] The gate (G) of the first NMOS transistor T1 is connected to the second power input terminal, the source (S) of the first NMOS transistor T1 is grounded, and the drain (D) of the first NMOS transistor T1 is connected to the gate (G) of the second NMOS transistor T2.
[0026] The source (S) of the second NMOS transistor T2 is grounded, and the drain (D) of the second NMOS transistor T2 is connected to the gate (G) of the third PMOS transistor T3 and the gate (G) of the fourth PMOS transistor T4, respectively.
[0027] Furthermore, the multi-power supply priority switching circuit also includes a fourth resistor R4;
[0028] One end of the fourth resistor R4 is connected to the first power input terminal, and the other end of the fourth resistor R4 is grounded.
[0029] Furthermore, the multi-power priority switching circuit also includes a second resistor R2 and a third resistor R3;
[0030] One end of the second resistor R2 is connected between the source (S) of the third PMOS transistor T3 and the source (S) of the fourth PMOS transistor T4, and the other end of the second resistor R2 is connected to the gate (G) of the second NMOS transistor T2.
[0031] One end of the third resistor R3 is connected between the source (S) of the third PMOS transistor T3 and the source (S) of the fourth PMOS transistor T4, and the other end of the third resistor R3 is connected to the drain (D) of the second NMOS transistor T2.
[0032] Furthermore, the multi-power supply priority switching circuit also includes a first resistor R1;
[0033] One end of the first resistor R1 is connected to the gate of the second NMOS transistor T2, and the other end of the first resistor R1 is grounded.
[0034] Furthermore, in the multi-power priority switching circuit, the first power input terminal is a POGO input terminal;
[0035] The second power input terminal is a DC input terminal;
[0036] The third power input terminal is a TYPE-C input terminal.
[0037] Furthermore, in the multi-power supply priority switching circuit, the input voltage of the first power supply input terminal is 9V;
[0038] The input voltage at the second power input terminal is 5V;
[0039] The input voltage of the third power input terminal is 5V.
[0040] Secondly, this utility model provides an electronic device, including a multi-power priority switching circuit as described in the first aspect above.
[0041] Compared with the prior art, the present invention has the following beneficial effects:
[0042] This invention provides a multi-power supply priority switching circuit and electronic device. Through a pure hardware circuit design, it achieves efficient priority switching of multiple power supplies. Compared with existing technologies, this circuit can accurately switch power supplies according to predetermined priorities under various power input scenarios. Leveraging the fast response characteristics of pure hardware circuits, it achieves rapid real-time power switching, ensuring stable equipment operation. This design not only significantly improves the reliability, determinism, and real-time performance of power supply but also reduces control costs and avoids delays and malfunctions that may occur in software control. Furthermore, this circuit has wide applicability, adapting to various power supply methods and providing an efficient and stable power solution for complex and ever-changing practical application scenarios, demonstrating significant practical value and promising prospects for widespread adoption.
[0043] This invention has other features and advantages that will be apparent from or will be set forth in detail in the accompanying drawings and the following detailed description, which together serve to explain the particular principles of this invention. Attached Figure Description
[0044] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0045] Figure 1 This is a functional module diagram of a multi-power supply priority switching circuit provided in Embodiment 1 of this utility model;
[0046] Figure 2 This is a schematic diagram of the circuit principle of a multi-power supply priority switching circuit provided in Embodiment 1 of this utility model;
[0047] Figure 3 This is a schematic diagram of the circuit principle of a multi-power priority switching circuit (first power branch is on) provided in Embodiment 1 of this utility model;
[0048] Figure 4 This is a schematic diagram of the circuit principle of a multi-power priority switching circuit (second power branch is turned on) provided in Embodiment 1 of this utility model;
[0049] Figure 5 This is a schematic diagram of the circuit principle of a multi-power priority switching circuit (third power branch is turned on) provided in Embodiment 1 of this utility model.
[0050] Figure label:
[0051] First power input terminal 1, second power input terminal 2, third power input terminal 3, first power branch 4, second power branch 5, third power branch 6, power output terminal 7. Detailed Implementation
[0052] To illustrate the possible application scenarios, technical principles, implementable specific solutions, and achievable objectives and effects of this application in detail, the following description, in conjunction with the listed specific embodiments and accompanying drawings, provides a detailed explanation. The embodiments described herein are merely illustrative of the technical solutions of this application and are therefore intended to limit the scope of protection of this application.
[0053] In this document, the term "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The term "embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment, nor does it specifically limit its independence or connection with other embodiments. In principle, in this application, as long as there are no technical contradictions or conflicts, the technical features mentioned in each embodiment can be combined in any way to form corresponding implementable technical solutions.
[0054] Unless otherwise defined, the technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the use of related terms herein is merely for the purpose of describing particular embodiments and is not intended to limit this application.
[0055] In the description of this application, the term "and / or" is used to describe the logical relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A exists, B exists, and A and B exist simultaneously. Additionally, the character " / " in this document generally indicates that the preceding and following objects have an "or" logical relationship.
[0056] In this application, terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any actual quantity, hierarchy or order relationship between these entities or operations.
[0057] Unless otherwise specified, the use of terms such as “comprising,” “including,” “having,” or other similar expressions in this application is intended to cover non-exclusive inclusion, which does not exclude the presence of additional elements in a process, method, or product that includes the stated elements, such that a process, method, or product that includes a list of elements may include not only those defined elements but also other elements not expressly listed, or elements inherent to such a process, method, or product.
[0058] In this application, expressions such as "greater than", "less than", and "exceeding" are understood to exclude the stated number; expressions such as "above", "below", and "within" are understood to include the stated number. Furthermore, in the description of the embodiments of this application, "multiple" means two or more (including two), and similar expressions related to "multiple" are also understood in this way, such as "multiple groups" and "multiple times", unless otherwise explicitly specified.
[0059] In the description of the embodiments of this application, the space-related expressions used, such as "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "vertical," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," indicate the orientation or positional relationship based on the orientation or positional relationship shown in the specific embodiments or drawings. They are only for the purpose of describing the specific embodiments of this application or for the reader's understanding, and do not indicate or imply that the device or component referred to must have a specific position, a specific orientation, or be constructed or operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.
[0060] Unless otherwise expressly specified or limited, the terms "installation," "connection," "linking," "fixing," and "setting," as used in the description of the embodiments of this application, should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral setting; it can be a mechanical connection, an electrical connection, or a communication connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two components or the interaction between two components. For those skilled in the art to which this application pertains, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.
[0061] Example 1
[0062] Please refer to Figure 1 This utility model embodiment provides a multi-power priority switching circuit. The overall architecture of the circuit consists of several key parts, including a first power input terminal 1, a second power input terminal 2, a third power input terminal 3, a first power branch 4, a second power branch 5, a third power branch 6, and a power output terminal 7.
[0063] Regarding the input voltage characteristics, the input voltage of the first power input terminal 1 is the maximum value among all power input terminals, while the input voltages of the second power input terminal 2 and the third power input terminal 3 are the same. This voltage characteristic setting lays the foundation for the subsequent power priority switching logic.
[0064] From the circuit connection perspective, the first power input terminal 1 is connected to the power output terminal 7 through the first power branch 4, enabling the electrical energy from the first power input terminal 1 to be transmitted to the power output terminal 7 via the first power branch 4. The second power input terminal 2 is connected to the power output terminal 7, the first power branch 4, and the third power branch 6 through the second power branch 5. This complex connection method provides the physical basis for priority switching between power supplies. The third power input terminal 3 is connected to the power output terminal 7 through the third power branch 6, ensuring that the electrical energy from the third power input terminal 3 can be transmitted to the power output terminal 7.
[0065] The working principle of this circuit under different power input conditions is explained in detail below:
[0066] When only one of the three power input terminals (first power input terminal 1, second power input terminal 2, and third power input terminal 3) is supplying power, the output voltage of the power output terminal 7 will be directly equal to the input voltage of the corresponding power input terminal. This is because, under single-power supply conditions, the corresponding power branch is in a conducting state, and electrical energy can be directly transferred from the power input terminal to the power output terminal 7 without interference from other power sources.
[0067] When the first power input terminal 1 and the second power input terminal 2 are powered simultaneously, the first power branch 4 will be in a conducting state, and the second power branch 5 will automatically turn off after receiving the input voltage from the first power branch 4. At this time, the output voltage of the power output terminal 7 will be equal to the input voltage of the first power input terminal 1, realizing the priority switching of the first power input terminal 1 to the second power input terminal 2.
[0068] When the first power input terminal 1 and the third power input terminal 3 are powered simultaneously, both the first power branch 4 and the third power branch 6 are in the conducting state. However, since the input voltage of the first power input terminal 1 is greater than the input voltage of the third power input terminal 3, according to the voltage priority logic of the circuit, the output voltage of the power output terminal 7 will be equal to the input voltage of the first power input terminal 1, ensuring the dominant position of the first power input terminal 1 in terms of power supply priority.
[0069] When the second power input terminal 2 and the third power input terminal 3 are powered simultaneously, the second power branch 5 is turned on, and the third power branch 6 automatically turns off after receiving the input voltage from the second power branch 5. At this time, the output voltage of the power output terminal 7 is equal to the input voltage of the second power input terminal 2, realizing the priority switching of the second power input terminal 2 to the third power input terminal 3.
[0070] The multi-power priority switching circuit designed in this embodiment adopts a pure hardware circuit design concept. Compared with the prior art, this circuit exhibits significant advantages. Under various power input scenarios, it can accurately and flawlessly switch power according to predetermined priority rules. Leveraging the fast response characteristics of pure hardware circuits, this circuit can complete real-time power switching in a very short time, effectively ensuring the stable operation of the equipment. This design not only significantly improves the reliability, determinism, and real-time performance of power supply but also significantly reduces control costs. Compared to software control schemes, pure hardware circuits avoid delays and faults that may occur during software operation, improving system stability and anti-interference capabilities. Furthermore, this circuit has wide applicability and can flexibly adapt to various power supply methods, achieving efficient power priority switching whether it is common DC power supply or other special power supply forms. Therefore, this circuit provides an efficient and stable power solution for complex and ever-changing practical application scenarios, possessing significant practical value and broad application prospects, and is expected to be widely used in various electronic devices.
[0071] To facilitate a more intuitive and in-depth understanding of the working principle and characteristics of the multi-power priority switching circuit described in this embodiment, a detailed example will be provided below using a specific power input terminal type. Specifically, the first power input terminal 1 is set as a POGO input terminal, the second power input terminal 2 as a DC input terminal, and the third power input terminal 3 as a TYPE-C input terminal.
[0072] Regarding input voltage settings, considering practical application scenarios and common power supply specifications, the input voltage of the first power input terminal 1 (POGO input terminal) can be set to, for example, 9V. The input voltages of the second power input terminal 2 (DC input terminal) and the third power input terminal 3 (TYPE-C input terminal) can both be, for example, 5V. This voltage setting conforms to the common voltage output range of different power interfaces and also provides a clear basis for subsequent power priority switching logic based on voltage differences.
[0073] In the circuit design of this embodiment, the power supply priority is clearly defined in descending order as follows: POGO input terminal, DC input terminal, and TYPE-C input terminal. This priority order is determined based on actual usage requirements and product characteristics, aiming to ensure that when multiple power supplies are connected simultaneously, the power supply with higher voltage and better power supply stability is used first to guarantee the normal operation of the equipment.
[0074] Based on the above power input type, input voltage setting, and power priority order, the following details the operating state of this circuit under different power input combinations:
[0075] When only one of the POGO input, DC input, or TYPE-C input is powered, the output voltage of power output terminal 7 will be directly equal to the input voltage of the corresponding power input terminal. For example, if only the POGO input is powered, and its input voltage is 9V, then the output voltage of power output terminal 7 will be 9V; if only the DC input or TYPE-C input is powered, since their input voltages are both 5V, the output voltage of power output terminal 7 will also be 5V.
[0076] When the POGO input and DC input are powered simultaneously, according to the circuit priority design, the POGO input (first power input 1) has a higher priority than the DC input (second power input 2). At this time, the first power branch 4 is turned on, allowing the power from the POGO input to be smoothly transferred to the power output 7. After receiving the input voltage (9V) from the first power branch 4, the first power branch 5 will automatically turn off, thus preventing interference from the DC input to the power output 7. Therefore, the output voltage of the power output 7 will be equal to the input voltage of the POGO input, i.e., 9V.
[0077] When both the POGO input and the TYPE-C input are powered simultaneously, the POGO input has a higher priority than the TYPE-C input, according to the power priority order. Both the first power branch 4 and the first power branch 6 are on. However, since the input voltage of the POGO input (9V) is greater than the input voltage of the TYPE-C input (5V), according to the circuit's voltage priority logic, the output voltage of the power output terminal 7 will be equal to the input voltage of the POGO input, i.e., 9V. At this time, although the TYPE-C input receives power, its lower priority will not affect the voltage of the power output terminal 7.
[0078] When both the DC input and the TYPE-C input are powered simultaneously, the first power supply branch 5 is turned on, and the electrical energy from the DC input is transferred to the power output 7. Upon receiving the input voltage (5V) from the first power supply branch 5, the first power supply branch 6 will turn off, thus preventing interference from the TYPE-C input to the power output 7. Therefore, the output voltage of the power output 7 will be equal to the input voltage of the DC input, i.e., 5V.
[0079] The above examples clearly demonstrate that the multi-power priority switching circuit designed in this embodiment can accurately and efficiently switch power supplies according to the preset power priority order under different power input combinations, ensuring that the voltage at the power output terminal 7 always matches the voltage at the power input terminal with the highest priority, thereby guaranteeing the stable operation of the equipment.
[0080] Please refer to Figure 2In one embodiment of this invention, the circuit structure of the first power supply branch 4 is designed in detail. Specifically, the first power supply branch 4 is mainly composed of diode D1. This simple component selection reflects the simplicity and efficiency of the circuit design.
[0081] Regarding the circuit connection, the positive terminal of diode D1 is closely connected to the first power input terminal 1, while the negative terminal of diode D1 is directly connected to the power output terminal 7. This connection method ensures that the electrical energy at the first power input terminal 1 can be unidirectionally transferred to the power output terminal 7 through diode D1.
[0082] The following details the working principle of this circuit when only the first power input terminal 1 is powered:
[0083] When only the first power input terminal 1 is powered, due to the unidirectional conductivity of diode D1, the input voltage of the first power input terminal 1 can smoothly flow into the positive terminal of diode D1 and out from the negative terminal of diode D1, ultimately being transmitted to the power output terminal 7. In this process, diode D1 plays a crucial role in power transmission, and because its forward voltage drop is relatively small (with proper selection), its impact on the input voltage is negligible. Therefore, the output voltage of the power output terminal 7 is almost equal to the input voltage of the first power input terminal 1, achieving efficient power transmission. The power supply path is as follows: Figure 3 As shown, the transmission process of electrical energy from the first power input terminal 1, through diode D1, and finally to the power output terminal 7 is clearly demonstrated.
[0084] This design of the first power supply branch 4 based on diode D1 is not only simple in structure and low in cost, but also has high reliability and stability. It ensures a stable voltage output at the power output terminal 7 even when only the first power input terminal 1 is powered, providing a reliable power guarantee for the normal operation of subsequent circuits. At the same time, this design also lays the foundation for the overall implementation of the subsequent multi-power supply priority switching circuit, enabling the circuit to accurately switch power supplies according to predetermined priority rules under various power input scenarios.
[0085] Please refer to this again. Figure 2 In one embodiment of this invention, the circuit architecture of the third power supply branch 6 is carefully designed. Specifically, the third power supply branch 6 is mainly composed of a third PMOS transistor T3 and a fourth PMOS transistor T4. This design using PMOS transistors can fully utilize the characteristics of PMOS transistors to achieve specific circuit functions.
[0086] Regarding the circuit connections, the drain (D) of the third PMOS transistor T3 is directly connected to the third power input terminal 3, allowing the power from the third power input terminal 3 to be directly transferred to the third PMOS transistor T3. The source (S) of the third PMOS transistor T3 is connected to the source (S) of the fourth PMOS transistor T4, forming a common node. This connection facilitates the coordinated operation of the two PMOS transistors. The drain (D) of the fourth PMOS transistor T4 is connected to the power output terminal 7, ensuring that the power processed by the third power branch 6 can be transferred to the power output terminal 7. Furthermore, the gate (G) of the third PMOS transistor T3 and the gate (G) of the fourth PMOS transistor T4 are respectively connected to the second power branch 5. This connection allows the state of the second power branch 5 to affect the on or off states of the third PMOS transistor T3 and the fourth PMOS transistor T4, thereby enabling control of the third power branch 6.
[0087] The following details the working principle of this circuit when only the third power input terminal 3 is powered:
[0088] When only the third power input terminal 3 is powered, since the second power branch 5 does not provide an effective cutoff signal to the gates of the third PMOS transistor T3 and the fourth PMOS transistor T4, the third PMOS transistor T3 and the fourth PMOS transistor T4 are in a conducting state under the voltage of the third power input terminal 3. The input voltage of the third power input terminal 3 passes sequentially through the drain and source of the third PMOS transistor T3, and the source and drain of the fourth PMOS transistor T4, and is finally transmitted to the power output terminal 7. During this process, since the PMOS transistors have low on-resistance in the conducting state, the loss of input voltage is small. Therefore, the output voltage of the power output terminal 7 is almost equal to the input voltage of the third power input terminal 3, realizing efficient power transmission. The power supply path is as follows: Figure 5 As shown, the transmission process of electrical energy from the third power input terminal 3, through the third PMOS transistor T3 and the fourth PMOS transistor T4, and finally to the power output terminal 7 is clearly demonstrated.
[0089] This design of the third power supply branch 6, based on the third PMOS transistor T3 and the fourth PMOS transistor T4, is not only structurally sound and functionally clear, but also highly flexible and scalable. It ensures a stable voltage output at the power supply output terminal 7 even when only the third power input terminal 3 is powered, providing reliable power for the normal operation of subsequent circuits. Furthermore, through its connection with the second power supply branch 5, this design can also work collaboratively with other power supply branches to achieve priority switching between multiple power supplies.
[0090] Please refer to this again. Figure 2In one embodiment of this invention, the circuit structure of the second power supply branch 5 is designed in a meticulous and ingenious manner. Specifically, the second power supply branch 5 is mainly composed of a fifth PMOS transistor T5, a first NMOS transistor T1, and a second NMOS transistor T2. This combination design makes full use of the characteristics of the PMOS transistor and the NMOS transistor to achieve specific power control functions.
[0091] Regarding circuit connections:
[0092] The drain (D) of the fifth PMOS transistor T5 is directly connected to the second power input terminal 2, allowing the power from the second power input terminal 2 to be directly transferred to the fifth PMOS transistor T5. The source (S) of the fifth PMOS transistor T5 is connected to the power output terminal 7, ensuring that the power processed by the fifth PMOS transistor T5 can be transferred to the power output terminal 7. The gate (G) of the fifth PMOS transistor T5 is connected to the first power input terminal 1, allowing the state of the first power input terminal 1 to affect the on or off state of the fifth PMOS transistor T5.
[0093] The gate (G) of the first NMOS transistor T1 is connected to the second power input terminal 2, allowing the input voltage at the second power input terminal 2 to control the conduction or cutoff of the first NMOS transistor T1. The source (S) of the first NMOS transistor T1 is grounded, providing a stable reference potential for the circuit. The drain (D) of the first NMOS transistor T1 is connected to the gate (G) of the second NMOS transistor T2, thereby transmitting the state of the first NMOS transistor T1 to the second NMOS transistor T2.
[0094] The source (S) of the second NMOS transistor T2 is grounded, providing a reference potential for the circuit. The drain (D) of the second NMOS transistor T2 is connected to the gate (G) of the third PMOS transistor T3 and the gate (G) of the fourth PMOS transistor T4, respectively. This connection allows the state of the second NMOS transistor T2 to control the on or off states of the third PMOS transistor T3 and the fourth PMOS transistor T4, thereby controlling the third power supply branch 6.
[0095] The following details the working principle of this circuit when only the second power input terminal 2 is powered:
[0096] When only the second power input terminal 2 is powered, since there is no voltage input to the first power input terminal 1, the gate voltage (G) of the fifth PMOS transistor T5 is low (relative to the source). According to the conduction characteristics of PMOS transistors, the fifth PMOS transistor T5 is in the conducting state. At this time, the input voltage of the second power input terminal 2 is transmitted to the power output terminal 7 through the drain and source terminals of the fifth PMOS transistor T5. Because the fifth PMOS transistor T5 has a low on-resistance in the conducting state, the loss of input voltage is small. Therefore, the output voltage of the power output terminal 7 is almost equal to the input voltage of the second power input terminal 2, realizing efficient power transmission.
[0097] Simultaneously, the input voltage at the second power input terminal 2 raises the gate voltage of the first NMOS transistor T1. When this voltage reaches the conduction threshold of the first NMOS transistor T1, T1 turns on. After T1 turns on, its drain voltage decreases, approaching ground potential. This causes the gate voltage of the second NMOS transistor T2 to also be low (relative to its source), and T2 is in the off state. Because T2 is off, its drain voltage increases, which does not generate an effective turn-on signal for the gates of the third PMOS transistor T3 and the fourth PMOS transistor T4. Therefore, T3 and T4 are also in the off state, ensuring that only the power from the second power input terminal 2 can be transmitted to the power output terminal 7. The power supply path is as follows: Figure 4 As shown, the transmission process of electrical energy from the second power input terminal 2, through the fifth PMOS transistor T5, and finally to the power output terminal 7 is clearly demonstrated.
[0098] This design of the second power supply branch 5, based on the fifth PMOS transistor T5, the first NMOS transistor T1, and the second NMOS transistor T2, is not only structurally sound and functionally clear, but also possesses high reliability and stability. It ensures a stable voltage output at the power output terminal 7 even when only the second power input terminal 2 is powered, providing a reliable power guarantee for the normal operation of subsequent circuits. Furthermore, through connection and interaction with other power supply branches, this design can also achieve priority switching of multiple power supplies, meeting the needs of complex and ever-changing power input scenarios.
[0099] Please refer to this again. Figure 2 In one embodiment of this invention, a fourth resistor R4 is also included;
[0100] One end of the fourth resistor R4 is connected to the first power input terminal 1, and the other end of the fourth resistor R4 is grounded.
[0101] It should be noted that the fourth resistor R4 mainly acts as a pull-down resistor here. When there is no voltage input at the first power input terminal 1 or it is in a high impedance state, the fourth resistor R4 can stably pull the potential of the first power input terminal 1 to the ground potential, avoiding circuit malfunctions or abnormal states caused by potential uncertainty, thereby ensuring that the circuit can maintain stable operation under various working conditions.
[0102] Please refer to this again. Figure 2 In one embodiment of this invention, a second resistor R2 and a third resistor R3 are also included;
[0103] One end of the second resistor R2 is connected between the source (S) of the third PMOS transistor T3 and the source (S) of the fourth PMOS transistor T4, and the other end of the second resistor R2 is connected to the gate (G) of the second NMOS transistor T2.
[0104] One end of the third resistor R3 is connected between the source (S) of the third PMOS transistor T3 and the source (S) of the fourth PMOS transistor T4, and the other end of the third resistor R3 is connected to the drain (D) of the second NMOS transistor T2.
[0105] It should be noted that the second resistor R2 serves as a current limiter and voltage divider here. It can limit the current flowing into the gate of the second NMOS transistor T2 to prevent excessive current from damaging the component. At the same time, it provides a suitable gate voltage for the second NMOS transistor T2 through the voltage divider effect, ensuring that it can work normally.
[0106] The third resistor R3 mainly acts as a pull-up resistor here. When the second NMOS transistor T2 is turned off, the third resistor R3 can pull up the drain potential of the second NMOS transistor T2, ensuring that the gate of the third PMOS transistor T3 and the fourth PMOS transistor T4 can obtain a sufficiently high voltage to maintain the cut-off state, thereby avoiding the circuit from being turned on by potential fluctuations.
[0107] Please refer to this again. Figure 2 In one embodiment of this invention, a first resistor R1 is also included;
[0108] One end of the first resistor R1 is connected to the gate of the second NMOS transistor T2, and the other end of the first resistor R1 is grounded.
[0109] It should be noted that the first resistor R1 also acts as a pull-down resistor here. It can further stabilize the gate potential of the second NMOS transistor T2. When the second NMOS transistor T2 is in the off state, the first resistor R1 can pull the gate potential to ground potential, preventing the second NMOS transistor T2 from being turned on erroneously due to the gate potential rise caused by leakage current or other interference factors, thereby ensuring the stability and reliability of the circuit.
[0110] Although this application frequently uses terms such as "first power input terminal" and "first power branch," the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of this utility model; interpreting them as any kind of additional limitation would contradict the spirit of this utility model.
[0111] Example 2
[0112] This utility model provides an electronic device, including a multi-power priority switching circuit as described in Embodiment 1 above.
[0113] Understandably, this multi-power priority switching circuit, as a key module of the electronic device's power management system, possesses the ability to intelligently identify and switch between different power inputs. It can automatically switch between multiple power inputs according to preset priority rules, ensuring that if a power input fails or its voltage becomes unstable, the electronic device can quickly and seamlessly switch to other available power inputs, thereby maintaining the device's continuous and stable operation.
[0114] In summary, the electronic device provided by this utility model embodiment, by integrating the multi-power priority switching circuit as described in Embodiment 1 above, achieves intelligent management and efficient switching of power supply, providing a strong guarantee for the stable operation of the electronic device. This design not only improves the reliability and safety of the device but also reduces the device failure rate caused by power supply problems and extends the service life of the device.
[0115] Finally, it should be noted that although the above embodiments have been described in the text and drawings of this application, this should not limit the scope of patent protection of this application. Any technical solutions that are based on the essential concept of this application and utilize the content described in the text and drawings of this application, resulting in equivalent structural or procedural substitutions or modifications, as well as the direct or indirect application of the technical solutions of the above embodiments to other related technical fields, are all included within the scope of patent protection of this application.
Claims
1. A multi-power supply priority switching circuit, characterized in that, It includes a first power input terminal, a second power input terminal, a third power input terminal, a first power branch, a second power branch, a third power branch, and a power output terminal; The first power input terminal has the highest input voltage, and the second power input terminal has the same input voltage as the third power input terminal. The first power input terminal is connected to the power output terminal through the first power branch, the second power input terminal is connected to the power output terminal, the first power branch and the third power branch through the second power branch, and the third power input terminal is connected to the power output terminal through the third power branch. When only one of the first power input terminal, the second power input terminal, and the third power input terminal is powered, the output voltage of the power output terminal is equal to the input voltage of the corresponding input terminal. When the first power input terminal and the second power input terminal are powered simultaneously, the first power branch is turned on, and the second power branch is turned off because it receives the input voltage of the first power branch. The output voltage of the power output terminal is equal to the input voltage of the first power input terminal. When the first power input terminal and the third power input terminal are powered at the same time, the first power branch is turned on and the third power branch is turned on. However, since the input voltage of the first power input terminal is greater than the input voltage of the third power input terminal, the output voltage of the power output terminal is equal to the input voltage of the first power input terminal. When the second power input terminal and the third power input terminal are powered simultaneously, the second power branch is turned on, and the third power branch is turned off due to receiving the input voltage of the second power branch. The output voltage of the power output terminal is equal to the input voltage of the second power input terminal.
2. The multi-power supply priority switching circuit according to claim 1, characterized in that, The first power supply branch includes diode D1; The positive terminal of diode D1 is connected to the first power input terminal, and the negative terminal of diode D1 is connected to the power output terminal.
3. The multi-power supply priority switching circuit according to claim 2, characterized in that, The third power supply branch includes a third PMOS transistor T3 and a fourth PMOS transistor T4; The drain (D) of the third PMOS transistor T3 is connected to the third power input terminal, and the source (S) of the third PMOS transistor T3 is connected to the source (S) of the fourth PMOS transistor T4. The drain of the fourth PMOS transistor T4 is connected to the power output terminal. The gate (G) of the third PMOS transistor T3 and the gate (G) of the fourth PMOS transistor T4 are respectively connected to the second power supply branch.
4. The multi-power supply priority switching circuit according to claim 3, characterized in that, The second power supply branch includes a fifth PMOS transistor T5, a first NMOS transistor T1, and a second NMOS transistor T2; The drain (D) of the fifth PMOS transistor T5 is connected to the second power input terminal, the source (S) of the fifth PMOS transistor T5 is connected to the power output terminal, and the gate (G) of the fifth PMOS transistor T5 is connected to the first power input terminal. The gate (G) of the first NMOS transistor T1 is connected to the second power input terminal, the source (S) of the first NMOS transistor T1 is grounded, and the drain (D) of the first NMOS transistor T1 is connected to the gate (G) of the second NMOS transistor T2. The source (S) of the second NMOS transistor T2 is grounded, and the drain (D) of the second NMOS transistor T2 is connected to the gate (G) of the third PMOS transistor T3 and the gate (G) of the fourth PMOS transistor T4, respectively.
5. The multi-power supply priority switching circuit according to claim 4, characterized in that, It also includes the fourth resistor R4; One end of the fourth resistor R4 is connected to the first power input terminal, and the other end of the fourth resistor R4 is grounded.
6. The multi-power supply priority switching circuit according to claim 5, characterized in that, It also includes the second resistor R2 and the third resistor R3; One end of the second resistor R2 is connected between the source (S) of the third PMOS transistor T3 and the source (S) of the fourth PMOS transistor T4, and the other end of the second resistor R2 is connected to the gate (G) of the second NMOS transistor T2. One end of the third resistor R3 is connected between the source (S) of the third PMOS transistor T3 and the source (S) of the fourth PMOS transistor T4, and the other end of the third resistor R3 is connected to the drain (D) of the second NMOS transistor T2.
7. The multi-power supply priority switching circuit according to claim 6, characterized in that, It also includes the first resistor R1; One end of the first resistor R1 is connected to the gate of the second NMOS transistor T2, and the other end of the first resistor R1 is grounded.
8. The multi-power supply priority switching circuit according to claim 7, characterized in that, The first power input terminal is a POGO input terminal; The second power input terminal is a DC input terminal; The third power input terminal is a TYPE-C input terminal.
9. The multi-power supply priority switching circuit according to claim 8, characterized in that, The input voltage at the first power input terminal is 9V; The input voltage at the second power input terminal is 5V; The input voltage of the third power input terminal is 5V.
10. An electronic device, characterized in that, Includes a multi-power priority switching circuit as described in any one of claims 1-9.