A redundant communication testing device

Abstract

The utility model discloses a kind of redundancy communication test devices, comprising: host computer (11), lower computer (12) and measured product (13), the host computer (11) is connected with the lower computer (12) by Ethernet;The lower computer (12) is connected with the measured product (13) by redundant serial bus.This redundancy communication test device of the utility model can realize the function of sending data packet to double network simultaneously when double network redundancy communication function test, and serial port baud rate can be self-defined;At the same time, reduce host computer software development workload, simplify test equipment connection structure.

Description

Technical Field

[0001] This utility model relates to the field of communication testing technology, and in particular to a redundant communication testing device. Background Technology

[0002] The RS485 bus, with its simple physical interface, long communication distance, and convenient networking, is a commonly used serial bus communication method between industrial field devices. For products in high-reliability applications, dual-network redundant communication is often employed to improve communication reliability. During product development, various tests are required to verify redundant communication functionality, including single-network communication, dual-network communication, and fault data packet injection. For dual-network communication testing, a common method is to connect two RS485 bus conversion devices, such as a USB-to-RS485 converter module, to the two RS485 communication ports of the product under test (DUT), and then connect the other end to two USB ports on a PC. The host computer software then sends data packets to the two communication ports of the DUT and simultaneously receives and processes the response data packets from the DUT. Another method is to directly use a serial converter module (serial server) with two RS485 serial ports. The two RS485 serial ports of the DUT are connected to the two serial ports of the serial server, and the host computer software sends custom data packets to the two serial ports to achieve redundant communication testing.

[0003] The above testing methods all have the following drawbacks:

[0004] 1) The two networks cannot send data packets simultaneously;

[0005] 2) The serial port baud rate cannot be customized;

[0006] 3) The development of the host computer software is labor-intensive and the setup of the testing environment is complicated. Summary of the Invention

[0007] Based on the above-mentioned technical problems, this utility model proposes a redundant communication testing device to solve the problems in the prior art where dual networks cannot send data packets simultaneously, the serial port baud rate cannot be customized, the workload of upper computer software development is large, and the setup of the testing environment is cumbersome.

[0008] To achieve the above objectives, according to one aspect of this utility model, a redundant communication testing device is proposed, comprising: a host computer 11, a slave computer 12, and a product under test 13, wherein the host computer 11 is connected to the slave computer 12 via Ethernet; and the slave computer 12 is connected to the product under test 13 via a redundant serial bus.

[0009] Optionally, the lower-level machine 12 includes a data processing and communication module 121, a redundant serial transceiver module 122, and a power management module 123.

[0010] The data processing and communication module 121 is connected to the Ethernet via an Ethernet interface and is connected to the redundant serial transceiver module 122.

[0011] The redundant serial transceiver module 122 is connected to the redundant serial bus via a serial port.

[0012] The power management module 123 is connected to an external power source via a power supply interface, and is also connected to the data processing and communication module 121 and the redundant serial transceiver module 122.

[0013] Optionally, the redundant serial transceiver module 122 is a two-channel serial differential signal conversion circuit.

[0014] Optionally, the serial port differential signal conversion circuit includes a serial transceiver 1221 and an interface circuit 1222.

[0015] The serial transceiver 1221 is connected to the interface circuit 1222;

[0016] The interface circuit 1222 is connected to the serial port.

[0017] Optionally, the interface circuit 1222 includes two RS resistors, one varistor RT, and two protection devices TVS.

[0018] The same side of the two RS resistors is grounded through a TVS protection device;

[0019] The varistor RT is connected between the two RS resistors in the circuit.

[0020] Optionally, the data processing and communication module 121 includes a programmable logic chip 1211, an Ethernet protocol stack chip 1212, a network transformer 1213, and a memory chip 1214.

[0021] The programmable logic chip 1211 is connected to the Ethernet protocol stack chip 1212 and the memory chip 1214 respectively;

[0022] The Ethernet protocol stack chip 1212 is connected to the network transformer 1213.

[0023] Optionally, the power management module 123 includes an interface protection circuit 1231, a power isolation module 1232, and a three-way voltage converter.

[0024] The interface protection circuit 1231 is connected to an external power source through a power supply interface and is also connected to the power isolation module 1232.

[0025] The power isolation module 1232 is connected to the three voltage converters respectively.

[0026] Optionally, the voltage of the external power supply is a DC voltage of 0-36V, the voltage of the first voltage conversion output is 3.3V, the voltage of the second voltage conversion output is 2.5V, and the voltage of the third voltage conversion output is 1.2V.

[0027] Optionally, the power isolation module 1232 is a DC / DC converter.

[0028] Optionally, the redundant serial bus is an RS485 bus.

[0029] Based on the above technical solution, this utility model has at least the following beneficial effects:

[0030] 1. Implement the function of simultaneously sending data packets to both networks and customizing the serial port baud rate when testing the dual-network redundant communication function;

[0031] 2. Reduce the workload of upper computer software development and simplify the connection structure of test equipment. Attached Figure Description

[0032] The accompanying drawings, which form part of this specification, are used to provide a further understanding of this utility model. The illustrative embodiments and descriptions of this utility model are used to explain this utility model and do not constitute an undue limitation thereof. In the drawings:

[0033] Figure 1 This is a schematic diagram of the structure of a redundant communication testing device according to one embodiment of the present invention;

[0034] Figure 2 This is a schematic diagram of the lower-level machine 12 according to one embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the serial port differential signal conversion circuit according to one embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of the interface circuit 1222 according to one embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of the structure of the data processing and communication module 121 according to one embodiment of the present invention;

[0038] Figure 6 This is a schematic diagram of the power management module 123 according to one embodiment of the present invention;

[0039] Figure 7 This is a schematic diagram of the serial port baud rate timing of one embodiment of the present invention. Detailed Implementation

[0040] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0041] The present invention will be further described in detail below with reference to specific embodiments, which should not be construed as limiting the scope of protection claimed by the present invention.

[0042] Example

[0043] To address the problems in existing technologies such as the inability of dual networks to send data packets simultaneously, the inability to customize serial port baud rates, the large workload of host computer software development, and the cumbersome setup of test environments, this utility model proposes a redundant communication test device.

[0044] According to one aspect of this utility model, a redundant communication testing device is proposed, such as... Figure 1 As shown, it includes: host computer 11, slave computer 12 and product under test 13.

[0045] This invention employs a host-server architecture. The host computer 11 is connected to the slave computer 12 via Ethernet; the slave computer 12 is connected to the product under test 13 via a redundant serial bus. The redundant serial bus is an RS485 bus. The slave computer 12 is constructed using FPGA-based hardware circuitry to achieve bidirectional data transmission between one Ethernet interface and two RS485 serial ports. The host computer 11 consists of a general-purpose PC and application software, used to implement custom data packet sending and receiving data packet parsing functions.

[0046] like Figure 2 As shown, the lower-level machine 12 further includes a data processing and communication module 121, a redundant serial port transceiver module 122, and a power management module 123.

[0047] Specifically, the data processing and communication module 121 is connected to an Ethernet network via an Ethernet interface and is connected to the redundant serial transceiver module 122; the redundant serial transceiver module 122 is connected to a redundant serial bus via a serial port; the power management module 123 is connected to an external power supply via a power supply interface and is connected to the data processing and communication module 121 and the redundant serial transceiver module 122 respectively.

[0048] The redundant serial transceiver module 122 is a two-channel serial differential signal conversion circuit.

[0049] Furthermore, such as Figure 3 As shown, the structure of each serial port differential signal conversion circuit is exactly the same. The serial port differential signal conversion circuit includes a serial transceiver 1221 and an interface circuit 1222.

[0050] The serial transceiver 1221 is connected to the interface circuit 1222; the interface circuit 1222 is connected to the serial port. In one embodiment, the serial transceiver 1221 is composed of a high-speed RS485 serial transceiver chip ADM3076, used to realize differential-to-single-ended conversion of RS485 bus physical layer level signals, and to realize bus data transmission and reception. The interface circuit 1222 is used to realize termination matching and transient overvoltage protection of the RS485 bus.

[0051] like Figure 4 As shown, the interface circuit 1222 includes two RS resistors, one varistor RT, and two TVS protection devices. The same side of the two RS resistors is grounded through the TVS protection devices; the varistor RT is connected between the circuits containing the two RS resistors. The RS resistors are current-limiting resistors to prevent transient overvoltage.

[0052] In one embodiment, such as Figure 5 As shown, the data processing and communication module 121 includes a programmable logic chip 1211, an Ethernet protocol stack chip 1212, a network transformer 1213, and a memory chip 1214.

[0053] Specifically, the programmable logic chip 1211 is connected to the Ethernet protocol stack chip 1212 and the memory chip 1214 respectively; the Ethernet protocol stack chip 1212 is connected to the network transformer 1213.

[0054] The FPGA programmable logic chip 1211, together with the logic program, parses the data packets sent by the host computer 11 through the network port and sends them to the corresponding serial port. At the same time, it sends the data packets received by the serial port to the host computer 11 through the network port.

[0055] The Ethernet protocol stack chip 1212 is used to implement the physical layer, data link layer, network layer, and transport layer protocol functions that conform to the IEEE 802.3 Ethernet communication standard, thereby enabling interface and communication with third-party network devices.

[0056] Network transformer 1213 provides electrical isolation for Ethernet interfaces.

[0057] The memory chip 1214 is used to store the configuration information of the serial bus under test, as well as the configured lower-level network parameters, including the IP address and port number of the device's network port.

[0058] In one embodiment, such as Figure 6 As shown, the power management module 123 includes an interface protection circuit 1231, a power isolation module 1232, and a three-way voltage converter.

[0059] The interface protection circuit 1231 is connected to an external power source through a power supply interface and is also connected to the power isolation module 1232; the power isolation module 1232 is connected to three voltage converters respectively.

[0060] The external power supply has a DC voltage of 0-36V. The first voltage conversion output is 3.3V, the second voltage conversion output is 2.5V, and the third voltage conversion output is 1.2V. The power isolation module 1232 is a DC / DC converter.

[0061] Interface protection circuit 1231 is used to implement overvoltage, undervoltage, and overcurrent protection for the power supply port. DC / DC power isolation module 1232 is used to achieve electrical isolation between the power supply input and the device, and to convert DC 9-36V input voltage to DC 5V. DC / DC voltage conversion circuit is used to convert 5V power supply to the voltages required by various functional circuits of the device, including 3.3V, 2.5V, and 1.2V.

[0062] In one embodiment, the host computer 11 is implemented by a LabVIEW-based application. Since the redundant communication status judgment of the transmitted data has been implemented on the slave computer 12, the functions implemented by the host computer program are relatively simple, including transmitting data packets, parsing received data packets, and setting slave computer parameters.

[0063] 1) Send data packet assembly

[0064] The host computer program interface inputs the data to be sent, and then selects the communication mode (A network communication, B network communication, AB dual network communication) to determine the location (A port, B port, or AB port) to which the data is sent. The data packet sent by the host computer consists of two parts: "sent data" and "redundant communication flag," as shown in Table 1 below. The "redundant communication flag" is determined manually by selecting the communication mode in the software program interface.

[0065] Table 1 Data Packet Format

[0066] Data distribution Redundant communication flag 0 to 256 bytes 1 byte

[0067] 2) Parsing received data packets

[0068] Each data packet uploaded by the lower-level computer 12 includes serial port location information. After receiving the data packet, the upper-level computer 11 parses the serial port location information and the data packet content, and displays it on the software interface.

[0069] 3) Lower-level machine parameter settings

[0070] The host computer 11 sets the relevant configuration parameters of the slave computer 12 by issuing parameter setting commands. The configuration parameters include the slave computer's network port parameters (IP address, port number) and serial port parameters (baud rate, start bit, stop bit, parity bit). After receiving the setting parameters, the slave computer saves them to the EEPROM chip.

[0071] The lower-level machine 12 uses an FPGA chip to perform functions such as redundancy status judgment of data packets sent by the upper-level machine 11, serial port data transmission and reception, serial port baud rate setting, and parameter setting.

[0072] 1) Issue data redundancy status judgment function

[0073] Each data packet sent by the host computer 11 carries a redundancy status judgment flag. This flag consists of 1 byte and represents the sending direction of the data packet (serial port A, serial port B, serial port AB), as shown in Table 2 below.

[0074] Table 2 Redundancy Status Judgment Flags

[0075] Flag Data transmission serial port 8'b0000_0001 Port A 8'b0000_0010 B 8'b0000_0011 A, B

[0076] The data pass-through unit in the FPGA's internal logic program detects this flag bit and sends the data packet to the corresponding serial port transmission buffer based on the detection result.

[0077] After the serial port transmitting unit detects data in the corresponding data buffer, it initiates data transmission, thereby sending the data packet sent by the host computer 11 to the product under test 13 via the serial port, thus testing the communication function of the product under test. When testing the single-network communication function of the product under test 13, the host computer program sets the redundancy status judgment flag attached to the sent data packet to 8'd1 or 8'd2; when testing the dual-network communication function of the product under test 13, the host computer program sets the redundancy status judgment flag attached to the sent data packet to 8'd3.

[0078] 2) Serial port data transmission and reception function

[0079] This function is implemented through FPGA logic code, which uploads data received through serial ports A and B to the host computer 11 via the network port. The logic program implements this function by including serial port transceiver units for A and B, a network transceiver unit, and a data processing unit.

[0080] The serial transceiver unit interfaces with an RS485 transceiver to implement serial data transmission and reception. Since the RS485 bus is a half-duplex communication mode, when the device is in standby mode, the FPGA uses the "transmit / receive" enable pin on the RS485 transceiver chip to put the RS485 serial port into "receive" mode. In "receive" mode, if the FPGA detects data transmission on the serial port (start bit detected), it will receive the data at the set baud rate.

[0081] When the FPGA receives transparent data from the host computer 11 via the network port, the FPGA controls the RS485 transceiver to enter "transmit" mode. It then transmits the data byte-by-byte through the serial port at the set baud rate according to the set serial port parameters. After data transmission is complete, the FPGA controls the RS485 transceiver to return to "receive" mode.

[0082] The Ethernet transceiver unit interfaces with the protocol stack chip to implement Ethernet data transmission and reception functions. Since the Ethernet bus operates in full-duplex mode, data transmission and reception are independent of each other.

[0083] When the serial port receiving unit receives data, the received data is placed into the network port transmit RAM (ping-pong RAM) in real time. Simultaneously, the data receiving timer (generated by the network port transmit timing module) monitors the time interval between received byte data. When the interval exceeds 10 times the time taken to receive a single byte of data, it is considered that a single packet of data on the RS485 bus has been successfully transmitted. After the packaged data is accompanied by the serial port location information (port A or port B), data transmission is initiated. The packaged data is sent to the transmit buffer in the Ethernet protocol stack chip, and then transmission is started. The protocol stack chip implements the IP / UDP protocol in hardware. After passing through this chip, the data is encapsulated into standard UDP protocol data packets and sent to the host computer. Conversely, when the Ethernet interface receives a data packet from the host computer, the FPGA first reads the data from the protocol stack chip's receive buffer into the data pass-through unit, performs a redundant communication status check, and then sends it to the corresponding serial port.

[0084] The data pass-through unit is used to determine the redundant communication status of the transmitted data and to buffer the transmitted and received data.

[0085] 3) Serial port baud rate setting function

[0086] The continuous baud rate setting function is implemented by FPGA logic. The FPGA system clock is 100MHz, and the baud rate can be continuously set from 50bps to 5Mbps through frequency division and counting. Figure 7As shown, the "baud rate generation module" of the serial transceiver unit automatically generates a transmit counter clock at a frequency of 20 times the baud rate set by the host computer. Under the control of this clock, the transmit counter period counts from zero, and when the count value reaches 20, it sends a "transmit enable" pulse signal. Serial data is transmitted bit by bit under the control of this "transmit enable" pulse.

[0087] 4) Parameter setting function

[0088] This function is implemented by the parameter parsing module in the FPGA logic program. The parameter setting function includes network port parameter settings and serial port parameter settings. Network port settings include IP address, port number, and gateway address (MAC address and subnet mask are fixed values ​​and cannot be set by the user).

[0089] Serial port settings include baud rate (50bps–5Mbps), data bits (5, 7, 8 bits), stop bits (1, 1.5, 2 bits), and parity bits (odd parity, even parity).

[0090] The device uses different packet type identifiers to distinguish parameter setting data packets from normal transmission data packets in its network port communication protocol. When the network port receives data from the host computer, it first determines the type of data packet based on this identifier, and then processes it accordingly.

[0091] In summary, it can be seen from the above description that the embodiments of this utility model achieve the following technical effects:

[0092] 1. Implement the function of simultaneously sending data packets to both networks and customizing the serial port baud rate when testing the dual-network redundant communication function;

[0093] 2. Reduce the workload of upper computer software development and simplify the connection structure of test equipment.

[0094] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

[0095] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0096] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0097] It should be understood that the various parts of this utility model can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0098] It should be noted that, in the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this utility model. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

Claims

1. A redundant communication testing device, characterized in that, include: The host computer (11), the slave computer (12), and the product under test (13) The host computer (11) is connected to the slave computer (12) via Ethernet; The lower-level machine (12) is connected to the product under test (13) through a redundant serial bus; The lower-level machine (12) includes a data processing and communication module (121), a redundant serial transceiver module (122), and a power management module (123). The data processing and communication module (121) is connected to the Ethernet via an Ethernet interface and is connected to the redundant serial transceiver module (122). The redundant serial transceiver module (122) is connected to the redundant serial bus via a serial port. The power management module (123) is connected to an external power source through a power supply interface, and is also connected to the data processing and communication module (121) and the redundant serial transceiver module (122). The data processing and communication module (121) includes a programmable logic chip (1211), an Ethernet protocol stack chip (1212), a network transformer (1213), and a memory chip (1214). The programmable logic chip (1211) is connected to the Ethernet protocol stack chip (1212) and the memory chip (1214) respectively; The Ethernet protocol stack chip (1212) is connected to the network transformer (1213); The programmable logic chip (1211) achieves continuous baud rate setting from 50bps to 5Mbps through frequency division counting.

2. The apparatus according to claim 1, characterized in that, The redundant serial transceiver module (122) is a two-channel serial differential signal conversion circuit.

3. The apparatus according to claim 2, characterized in that, The serial port differential signal conversion circuit includes a serial transceiver (1221) and an interface circuit (1222). The serial transceiver (1221) is connected to the interface circuit (1222); The interface circuit (1222) is connected to the serial port.

4. The apparatus according to claim 3, characterized in that, The interface circuit (1222) includes two RS resistors, one varistor RT, and two protection devices TVS. The same side of the two RS resistors is grounded through a TVS protection device; The varistor RT is connected between the two RS resistors in the circuit.

5. The apparatus according to claim 1, characterized in that, The power management module (123) includes an interface protection circuit (1231), a power isolation module (1232), and a three-way voltage converter. The interface protection circuit (1231) is connected to an external power supply through a power supply interface and is also connected to the power isolation module (1232). The power isolation module (1232) is connected to the three voltage converters respectively.

6. The apparatus according to claim 5, characterized in that, The external power supply has a DC voltage of 0-36V. The first voltage conversion output voltage is 3.3V, the second voltage conversion output voltage is 2.5V, and the third voltage conversion output voltage is 1.2V.

7. The apparatus according to claim 5, characterized in that, The power isolation module (1232) is a DC / DC converter.

8. The apparatus according to claim 1, characterized in that, The redundant serial bus is an RS485 bus.

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