power module

Abstract

The utility model belongs to power module technical field, concretely relates to a kind of power module.The power module includes: from bottom to top layer stack arrangement bottom layer DBC, middle layer DBC and top layer DBC;Each layer DBC includes layer stack arrangement positive copper layer, ceramic layer and back copper layer;The positive copper layer of bottom layer DBC, middle layer DBC and top layer DBC is collector region, emitter region and gate region respectively.The power module of the utility model adopts laminated DBC design, the internal insulation capacity of module can be controlled by the thickness of each layer ceramic layer, without etching groove filling sealant mode to carry out insulation, avoid the deficiency in the prior art;The dielectric strength of ceramic is smaller than several orders of magnitude than filling sealant by temperature change, so it can be long-term service under.This way, collector region, emitter region and gate region are at different heights, not in the same plane, so the mutual inductance between gate loop and power loop is very small, and the module stray inductance is small.

Description

Technical Field

[0001] This utility model belongs to the field of power module technology, and specifically relates to a power module. Background Technology

[0002] In recent years, the increasing voltage, power, and power density of power devices and modules have become important future development directions. Therefore, high-voltage power devices and modules with excellent performance are widely used in automotive motor drives, wind power generation, oil and gas drilling, avionics power supplies, and military applications. However, the operating voltage and temperature of power modules offered by existing high-voltage power module manufacturers are far from meeting the limits of wide-bandgap semiconductor materials. Although researchers have successfully developed high-voltage and ultra-high-voltage SiC and IGBT chips and modules, one of the remaining bottlenecks is the reliability of high-voltage power module packaging materials under multi-physics coupling stress, such as insulation breakdown caused by partial discharge during long-term service. As the size of high-voltage power modules decreases while the operating voltage and temperature increase, the packaging insulation material is subjected to greater electrical and thermal stress, placing higher demands on its insulation performance.

[0003] Taking IGBT chips as an example, the internal chip-to-DBC design of a traditional power module is shown in the attached figure. Figure 1 As shown, the etching tank divides the DBC positive copper layer into three regions: the gate region, the collector region, and the emitter region. The insulation between these three regions is achieved by filling the etching tanks with potting compound. This potting compound, after high-temperature curing, possesses a certain dielectric strength, thus ensuring the module's internal insulation. However, during thermal cycling and long-term service, the potting compound develops cracks. The dielectric strength at these cracks is extremely low, leading to insulation failure in the high-voltage power module. In offshore wind power applications, under high temperature, high humidity, and high pressure conditions, H2S reacts with the gas to form copper sulfide (Cu2S) crystals within the etching tank. Over long-term service, this causes short circuits in the collector and emitter regions, resulting in power module failure. Furthermore, in this type of power module, the current flows in the gate, collector, and emitter regions all on the same plane of the DBC positive copper surface, leading to significant mutual inductance and high stray inductance. Utility Model Content

[0004] The purpose of this invention is to provide a power module that solves the technical problem of poor insulation performance in traditional power modules that rely on etching grooves for partitioning.

[0005] This application provides a power module, including:

[0006] The bottom-up DBC, middle-up DBC, and top-up DBC are stacked from bottom to top.

[0007] Each layer of DBC includes a stacked front copper layer, a ceramic layer, and a back copper layer;

[0008] The positive copper layers of the bottom DBC, middle DBC, and top DBC are the collector region, emitter region, and gate region, respectively.

[0009] In one embodiment of this application, the power module includes a plurality of power semiconductor chips;

[0010] The back gold layer collector of the power semiconductor chip is connected to the positive copper layer of the bottom DBC, the positive gold layer emitter is connected to the positive copper layer of the middle DBC, and the gate is connected to the positive copper layer of the top DBC.

[0011] In one embodiment of this application, the power module includes:

[0012] The power circuit upper bridge area and the power circuit lower bridge area are provided, and the bottom layer DBC, middle layer DBC and top layer DBC are provided in each bridge area;

[0013] The DC+ power terminal is connected to the positive copper layer of the bottom DBC in the bridge area of ​​the power circuit.

[0014] The AC power terminal is connected to the positive copper layer of the bottom DBC in the lower bridge area of ​​the power circuit.

[0015] The DC-power terminal is connected to the positive copper layer of the middle layer DBC in the lower bridge area of ​​the power circuit.

[0016] In one embodiment of this application, the back copper layer of the top DBC in the upper bridge region of the power circuit is connected to the positive copper layer of the bottom DBC in the lower bridge region of the power circuit through a solid solderable material.

[0017] In one embodiment of this application, the power module further includes:

[0018] Heat dissipation base plate; the back copper layer of the underlying DBC is connected to the heat dissipation base plate;

[0019] The outer casing is mounted on a heat dissipation base plate, and the interior of the casing is filled with potting compound.

[0020] In one embodiment of this application, the power semiconductor chip includes IGBT, FRD, RC-IGBT, SiC, and GaN semiconductor power chips.

[0021] In one embodiment of this application, the ceramic layer thickness of the underlying DBC is not less than 0.32 mm;

[0022] The ceramic layer thickness of the middle layer DBC and the top layer DBC is not less than 0.25 mm.

[0023] In one embodiment of this application, the thickness of the front and back copper layers of the underlying DBC is not less than 0.25 mm;

[0024] The thickness of the front and back copper layers of the middle layer DBC and the top layer DBC is not less than 0.15mm.

[0025] In one embodiment of this application, the height of the outer shell is not less than 2mm;

[0026] The height of the potting compound is greater than 1.47 mm.

[0027] The beneficial effects of this utility model are:

[0028] Unlike existing technologies, this application provides a power module. The power module includes a bottom layer DBC, a middle layer DBC, and a top layer DBC stacked from bottom to top; each DBC layer includes a stacked positive copper layer, a ceramic layer, and a back copper layer; the positive copper layers of the bottom, middle, and top DBCs are the collector region, emitter region, and gate region, respectively. This utility model's power module adopts a stacked DBC design, and the module's internal insulation capability can be controlled by the thickness of each ceramic layer, eliminating the need for etching tanks and filling with sealant for insulation, thus avoiding the shortcomings of existing technologies. The dielectric strength of ceramic is several orders of magnitude less affected by temperature changes than that of potting compound, allowing for long-term service. Furthermore, the collector region, emitter region, and gate region are at different heights and not on the same plane, therefore the mutual inductance between the gate circuit and the power circuit is minimal, resulting in low stray inductance in the module.

[0029] Other features and advantages of this invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objectives and other advantages of this invention are realized and obtained through the structures particularly pointed out in the description and the accompanying drawings.

[0030] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0031] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of a traditional power module;

[0033] Figure 2 This is a perspective view of a power module according to a preferred embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of the DBC stack-up of a power module according to a preferred embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of the DBC structure of a power module according to a preferred embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of the heat dissipation path of a power module in a preferred embodiment of the present invention compared to a conventional package;

[0037] Figure 6 This is a cross-sectional view of a power module according to a preferred embodiment of the present invention.

[0038] In the picture:

[0039] 1.1 Etching tank, 1.2 Gate region, 1.3 Collector region, 1.4 Emitter region, 1.5 Encapsulating resin, 1.6 Copper sulfide crystal;

[0040] 2.1 Power semiconductor chip, 2.2 Bonding wire, 2.3 Bottom layer DBC, 2.4 Middle layer DBC, 2.5 Top layer DBC, 2.6 DC+ power terminal, 2.7 DC- power terminal, 2.8 AC power terminal, 2.9 Solid solderable material, 2.10 Ceramic layer;

[0041] Heat dissipation path 1 (3.1), heat dissipation path 2 (3.2);

[0042] 4.1 Heat dissipation base plate; 4.2 potting compound; 4.3 outer casing;

[0043] Power circuit upper bridge region 5.1, power circuit lower bridge region 5.2. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0045] This application provides a power module, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application. Furthermore, the descriptions of each embodiment have their own emphasis; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments.

[0046] See Figure 1 Traditional power modules have the following shortcomings:

[0047] 1. Taking IGBT chips as an example, in the traditional power module internal chip to DBC design, the etching tank 1.1 divides the DBC positive copper layer into three regions, including the gate region 1.2, the collector region 1.3, and the emitter region 1.4; the insulation between the three is achieved by filling the etching tank with potting compound 1.5. After the potting compound is cured at high temperature, it has a certain dielectric strength, thereby ensuring the insulation inside the module; however, the potting compound develops crack defects during thermal cycling and long-term service. The defect dielectric strength at the crack is extremely low, leading to the insulation failure of the high-voltage power module;

[0048] 2. In the field of offshore wind power application, under high temperature, high humidity and high pressure, H2S reacts with the gas to generate copper sulfide (Cu2S) crystals 1.6. Under long-term service, the collector and emitter areas short-circuit, and the power module fails.

[0049] 3. In the gate region 1.2, collector region 1.3, and emitter region 1.4, the current flow is all on the positive copper surface of the DBC, which has a significant impact on mutual inductance and results in high stray inductance of the module.

[0050] To address the technical problems of existing technologies, see [link to relevant documentation]. Figures 2 to 4 One embodiment of this application provides a power module, which includes: a bottom layer DBC2.3, a middle layer DBC2.4, and a top layer DBC2.5 stacked from bottom to top; each DBC layer includes a positive copper layer, a ceramic layer, and a back copper layer stacked together; the positive copper layers of the bottom layer DBC2.3, the middle layer DBC2.4, and the top layer DBC2.5 are the collector region, the emitter region, and the gate region, respectively.

[0051] In this embodiment, the positive copper layer of the bottom DBC2.3 does not require etching grooves to fill with sealant for insulation design; with the use of a stacked DBC design, the internal insulation capability of the module can be controlled by the thickness of the ceramic layer 2.10 of each DBC stacked in the Z direction. The dielectric strength of the ceramic is affected by temperature changes by several orders of magnitude less than that of the potting compound. Therefore, under long-term service, the shortcomings of the prior art can be avoided.

[0052] In this embodiment, the heat dissipation path under the chip is less restricted by the DBC layout, resulting in lower junction-case thermal resistance compared to traditional power modules. See attached figure for details. Figure 5 As shown, traditional power modules, due to the DBC positive copper etching groove design, result in two heat dissipation paths for the power chip: heat dissipation path 1 (3.1): copper-ceramic-copper solid heat transfer and heat dissipation path 2 (3.2): copper-potting compound-ceramic-copper. However, the potting compound has extremely low thermal conductivity, which affects the heat dissipation of the module. In this embodiment, the DBC positive copper layer is not etched, so the heat dissipation path only includes copper-ceramic-copper solid heat transfer, resulting in low thermal resistance of the module junction.

[0053] In this embodiment, the gate region, collector region, and emitter region are all distributed on the positive copper layers of the top layer DBC2.5, the bottom layer DBC2.3, and the middle layer DBC2.4. Each DBC is located at a different height on the Z-axis and is not on the same plane. Therefore, the mutual inductance between the gate circuit and the power circuit is minimal, and the stray inductance of the module is small.

[0054] In this embodiment, optionally, the DBC can be a direct copper-clad ceramic substrate; the thickness and material of the ceramic layer can be adjusted according to the voltage level of the power module; the material of the ceramic layer is not limited to Al2O3, Si3N4, AlN and other materials.

[0055] In this embodiment, the power module includes multiple power semiconductor chips 2.1; the back gold layer collector of the power semiconductor chip 2.1 is connected to the positive copper layer of the bottom layer DBC2.3, the positive gold layer emitter is connected to the positive copper layer of the middle layer DBC2.4, and the gate is connected to the positive copper layer of the top layer DBC2.5.

[0056] Furthermore, in one embodiment, the power module includes: an upper bridge region 5.1 and a lower bridge region 5.2 of the power circuit, and each bridge region is provided with the bottom layer DBC2.3, the middle layer DBC2.4, and the top layer DBC2.5; a DC+ power terminal 2.6, connected to the positive copper layer of the bottom layer DBC2.3 in the upper bridge region 5.1 of the power circuit; an AC power terminal 2.8, connected to the positive copper layer of the bottom layer DBC2.3 in the lower bridge region 5.2 of the power circuit; and a DC- power terminal 2.7, connected to the positive copper layer of the middle layer DBC2.4 in the lower bridge region 5.2 of the power circuit. The back copper layer of the top layer DBC2.5 in the upper bridge region 5.1 of the power circuit is connected to the positive copper layer of the bottom layer DBC2.3 in the lower bridge region 5.2 of the power circuit through a solid solderable material 2.9.

[0057] For details, see Figure 2 Within the upper bridge region 5.1 of the power circuit, the DC+ power terminal 2.6 is interconnected with the positive copper layer of the bottom layer DBC2.3 via ultrasonic welding; the positive copper layer of the bottom layer DBC2.3 is interconnected with the collector of the back gold layer of the power semiconductor chip 2.1 via conventional welding, diffusion welding, or sintering techniques; the emitter of the positive gold layer of the power semiconductor chip 2.1 is interconnected with the upper copper layer of the middle layer DBC2.4 via wire bonding 2.2; the upper copper layer of the middle layer DBC2.4 is interconnected with the back copper layer of the top layer DBC2.5 via conventional welding or sintering techniques; the back copper layer of the top layer DBC2.5 within the upper bridge region 5.1 of the power circuit is connected to the positive copper layer of the bottom layer DBC2.3 within the lower bridge region 5.2 of the power circuit via a solid solderable material 2.9;

[0058] Within the lower bridge region 5.2 of the power circuit, the positive copper layer of the bottom layer DBC2.3 is interconnected with the collector of the back gold layer of the power semiconductor chip 2.1 through conventional soldering, diffusion soldering, or sintering techniques. The emitter of the positive gold layer of the power semiconductor chip 2.1 is connected to the upper copper layer of the middle layer DBC2.4 through wire bonding 2.2. The positive copper layer of the middle layer DBC2.4 is interconnected with the DC-power terminal 2.7 through ultrasonic soldering, forming the entire power circuit. The AC-end power terminal 2.8 is interconnected with the positive copper layer of the bottom layer DBC2.3 within the lower bridge region 5.2 of the power circuit through ultrasonic soldering.

[0059] The gate circuit is interconnected with the chip gate by the positive copper layer of the top layer DBC2.5, and interconnected with the signal terminals by ultrasonic welding technology.

[0060] In this embodiment, it can be obtained from Figure 2 As can be seen, the collector current of the power circuit is distributed on the positive copper layer of DBC2.3; the emitter current is distributed on the positive gold layer of the chip, the positive copper layer of the middle layer DBC2.4, and the back copper layer of the top layer DBC2.5; the gate circuit is distributed on the positive copper layer of the top layer DBC2.5. Under this design, the power circuit and the drive circuit are not on the same horizontal plane. Under this design, the high voltage power module will have a smaller stray inductance than the traditional power module.

[0061] In this embodiment, in addition to the circuit design described above, the high-voltage power module also needs to meet the requirements for module heat dissipation. Optionally, the power module further includes: a heat dissipation base plate 4.1; the back copper layer of the bottom layer DBC2.3 can be connected to the heat dissipation base plate 4.1 by conventional welding or sintering; and a housing 4.3, which covers the heat dissipation base plate 4.1, and the inside of the housing 4.3 is filled with potting compound 4.2 to ensure that arcing does not occur during the operation of the high-voltage power module and to ensure the basic insulation characteristics of the module. In addition, the power module can be electrically and creepage-proofed through the power module housing 4.3 to ensure external insulation of the module, and interconnected with the heat dissipation base plate 4.1 through sealant.

[0062] In this embodiment, optionally, the power semiconductor chip 2.1 includes, but is not limited to, third-generation semiconductor power chips such as IGBT, FRD, RC-IGBT, SiC, and GaN.

[0063] In some applications, the DBC includes a back copper layer, a ceramic layer, and a front copper layer. The thickness and material of the ceramic layer can be adjusted according to the voltage level of the power module. For example, for voltage levels of 1.2–6.5 kV or even higher, the ceramic layer thickness of the bottom layer DBC2.3 is no less than 0.32 mm; the ceramic layer thickness of the middle layer DBC2.4 and the top layer DBC2.5 is no less than 0.25 mm; the ceramic layer material is not limited to Al2O3, Si3N4, AlN, etc.; the front and back copper layer thickness of the bottom layer DBC2.3 is no less than 0.25 mm; the front and back copper layer thickness of the middle layer DBC2.4 and the top layer DBC2.5 is no less than 0.15 mm. Due to the use of DBC stacking and soldering interconnect technology, the height of the outer shell 4.3 is no less than 2 mm; the height of the internal potting compound 4.2 must be greater than 1.47 mm, completely covering the bonding leads 2.2 on the top layer DBC2.5.

[0064] In summary, the power module of this invention comprises a bottom DBC, a middle DBC, and a top DBC stacked from bottom to top; each DBC layer includes a stacked positive copper layer, a ceramic layer, and a back copper layer; the positive copper layers of the bottom, middle, and top DBCs are the collector region, emitter region, and gate region, respectively. In other words, the power module of this invention adopts a stacked DBC design, and the internal insulation capability of the module can be controlled by the thickness of each ceramic layer, eliminating the need for etching tanks and filling with sealant for insulation, thus avoiding the shortcomings of existing technologies; the dielectric strength of ceramic is several orders of magnitude less affected by temperature changes than that of potting compound, thus allowing for long-term service. Furthermore, the collector region, emitter region, and gate region are at different heights and are not on the same plane, therefore the mutual inductance between the gate circuit and the power circuit is minimal, resulting in low stray inductance of the module.

[0065] It should be noted that all the devices (parts whose specific structures are not specified) selected in this application are general standard parts or parts known to those skilled in the art, and their structures and principles can be known to those skilled in the art through technical manuals or conventional experimental methods.

[0066] In the description of the embodiments of this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0067] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0068] Based on the above-described preferred embodiments of this utility model, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the technical concept of this utility model. The technical scope of this utility model is not limited to the contents of the specification.

Claims

1. A power module, characterized in that, include: The bottom layer DBC (2.3), middle layer DBC (2.4), and top layer DBC (2.5) are stacked from bottom to top. Each layer of DBC includes a stacked front copper layer, a ceramic layer, and a back copper layer; The positive copper layers of the bottom layer DBC (2.3), the middle layer DBC (2.4), and the top layer DBC (2.5) are the collector region, the emitter region, and the gate region, respectively.

2. The power module according to claim 1, characterized in that, The power module includes multiple power semiconductor chips (2.1). The back gold layer collector of the power semiconductor chip (2.1) is connected to the positive copper layer of the bottom DBC (2.3), the positive gold layer emitter is connected to the positive copper layer of the middle DBC (2.4), and the gate is connected to the positive copper layer of the top DBC (2.5).

3. The power module according to claim 1, characterized in that, The power module includes: The power loop upper bridge region (5.1) and the power loop lower bridge region (5.2) are provided, and the bottom layer DBC (2.3), the middle layer DBC (2.4) and the top layer DBC (2.5) are provided in each bridge region. The DC+ power terminal (2.6) is connected to the positive copper layer of the bottom DBC (2.3) in the upper bridge area (5.1) of the power circuit; The AC power terminal (2.8) is connected to the positive copper layer of the bottom layer DBC (2.3) in the lower bridge area (5.2) of the power circuit; The DC-power terminal (2.7) is connected to the positive copper layer of the middle layer DBC (2.4) in the lower bridge region (5.2) of the power circuit.

4. The power module according to claim 3, characterized in that, The back copper layer of the top DBC (2.5) in the upper bridge region (5.1) of the power circuit is connected to the positive copper layer of the bottom DBC (2.3) in the lower bridge region (5.2) of the power circuit through a solid solderable material (2.9).

5. The power module according to claim 1, characterized in that, The power module also includes: Heat dissipation base plate (4.1); the back copper layer of the bottom layer DBC (2.3) is connected to the heat dissipation base plate (4.1); The outer casing (4.3) is mounted on the heat dissipation base plate (4.1), and the interior of the outer casing (4.3) is filled with potting compound (4.2).

6. The power module according to claim 2, characterized in that, The power semiconductor chip (2.1) includes IGBT, FRD, RC-IGBT, SiC, and GaN semiconductor power chips.

7. The power module according to claim 1, characterized in that, The thickness of the ceramic layer of the underlying DBC (2.3) is not less than 0.32 mm; The ceramic layer thickness of the middle layer DBC (2.4) and the top layer DBC (2.5) is not less than 0.25 mm.

8. The power module according to claim 1, characterized in that, The thickness of the front and back copper layers of the underlying DBC (2.3) is not less than 0.25mm; The thickness of the front and back copper layers of the middle layer DBC (2.4) and the top layer DBC (2.5) is not less than 0.15mm.

9. The power module according to claim 5, characterized in that, The height of the outer shell (4.3) is not less than 2mm; The height of the potting compound (4.2) is greater than 1.47 mm.

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