A detection system of Type-C interface
By reconfiguring the pins of the Type-C interface detection data line and controlling the main control chip, the Type-C interface can be tested with a single plug-in/plug-out, solving the problem of requiring two plug-ins/plug-outs in the existing technology, improving testing efficiency and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- JS TONSCEND CORP
- Filing Date
- 2025-06-12
- Publication Date
- 2026-06-19
AI Technical Summary
Existing Type-C interface testing systems require separate plugging and unplugging tests on both sides of the Type-C male connector, which increases testing time and cost.
By reconfiguring the pins of the detection data line, setting pin B5 as pin CC2, pin B6 as pin D+, and pin B7 as pin D-, and using the main control chip and the forward/reverse insertion control chip to control the conduction and disconnection of the MOSFET, the detection of the Type-C interface can be completed with a single insertion and removal.
This significantly shortens the testing process, reduces testing time and costs, and meets the requirements for using fast charging protocols.
Smart Images
Figure CN224383358U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of data interfaces, and in particular to a detection system for a Type-C interface. Background Technology
[0002] Unlike traditional USB interfaces, the Type-C interface uses a symmetrical pin design, eliminating the need to distinguish the plug's orientation and allowing for blind insertion in either direction, thus avoiding the tedious process of reversible insertion. Because the Type-C interface supports reversible insertion, higher power delivery, and faster transfer speeds, more and more devices are adopting Type-C as their charging and data transfer interface.
[0003] The Type-C interface is divided into female (Receptacle) and male (Plug) connectors. Please refer to [link / reference]. Figure 1 and Figure 2 Currently, when the front side of the Type-C male connector is inserted into the Type-C female connector, pins A5, A6, and A7 on the front side of the male connector are connected to pins A5, A6, and A7 on the female connector, respectively. When the back side of the Type-C male connector is inserted into the Type-C female connector, pins A5, A6, and A7 on the male connector are connected to pins B5, B6, and B7 on the female connector, thus enabling normal operation regardless of whether it is inserted in the correct orientation. However, if any of the pins A5, A6, A7, B5, B6, or B7 on the Type-C female connector has a cold solder joint, poor solder joint, or short circuit, the device will still function normally if the male connector is inserted into the female connector with a good solder joint. The device will only malfunction when the male connector is inserted into the female connector with a cold solder joint, poor solder joint, or short circuit, leading to misjudgment of the device's actual condition.
[0004] To reduce the possibility of misjudgment of the aforementioned devices, the Type-C interface (Type-C female connector) of devices now requires testing by inserting and unplugging the Type-C male connector from both sides and testing it separately. This greatly increases the testing time and cost.
[0005] Therefore, in order to reduce the testing steps for the Type-C interface of the device, thereby reducing testing time and cost, there is a need to provide an improved Type-C interface testing system. Utility Model Content
[0006] In view of this, this utility model proposes a Type-C interface detection system to solve the problem that portable charging devices are prone to unstable internal charging circuits and low reliability due to size issues.
[0007] The technical solution of this utility model is implemented as follows:
[0008] According to a first aspect, embodiments of the present invention provide a Type-C interface detection system, the circuit comprising:
[0009] Test data cable and test circuit;
[0010] The detection data cable has a first interface and a second interface. The first interface is a Type-C male connector, and the second interface is electrically connected to the detection circuit. The B5 pin on the reverse side of the first interface is configured as the CC2 pin, the B6 pin on the reverse side of the first interface is configured as the D+ pin, and the B7 pin on the reverse side of the first interface is configured as the D- pin.
[0011] The detection circuit includes:
[0012] The main control chip, signal sampling module, and reversible insertion control module are electrically connected to the main control chip. The signal sampling module is electrically connected to the reversible insertion control module. The reversible insertion control module is electrically connected to the first interface through the second interface. The main control chip controls the conduction and disconnection of the CC1 pin, CC2 pin, reverse D+ pin, and reverse D- pin through the reversible insertion control module.
[0013] In conjunction with the first aspect, in the first embodiment of the first aspect, the forward / reverse insertion control module includes:
[0014] The components include a forward / reverse insertion control chip U107, a first MOSFET MOS106, a second MOSFET MOS107, a first diode, a second diode, a third diode, a fourth diode, a first capacitor C30, and a connector PD1.
[0015] The first pin of the reversible insertion control chip U107 is connected to the input voltage. The second, third, and fourth pins of the reversible insertion control chip U107 are all electrically connected to the main control chip. The third pin of the reversible insertion control chip U107 is electrically connected to the negative terminal of the first diode, and the positive terminal of the first diode is grounded. The fourth pin of the reversible insertion control chip U107 is electrically connected to the negative terminal of the second diode, and the positive terminal of the second diode is grounded. The fifth pin of the reversible insertion control chip U107 is grounded. The twelfth to fifteenth pins of the reversible insertion control chip U107 are all electrically connected to the connector PD1. The sixteenth pin of the reverse insertion control chip U107 is grounded and connected to the input voltage through the first capacitor C30 in series.
[0016] The first pin of connector PD1 is electrically connected to the VBUS1 terminal, the eighth pin of connector PD1 is grounded, the fourth to seventh pins of connector PD1 are electrically connected to the forward / reverse insertion control chip U107 respectively, and the second and third pins of connector PD1 are electrically connected to the CC1 and CC2 pins of the first interface respectively.
[0017] In conjunction with the first embodiment of the first aspect, in the second embodiment of the first aspect, the forward / reverse insertion control module further includes:
[0018] The first MOSFET is MOS106, the second MOSFET is MOS107, the third diode and the fourth diode;
[0019] The second and third pins of connector PD1 are electrically connected to the source of the first MOSFET MOS106 and the source of the second MOSFET MOS107, respectively. The gate of the first MOSFET MOS106 is electrically connected to the first enable signal of the main control chip, and the drain of the first MOSFET MOS106 is electrically connected to the signal sampling module. The negative terminal of the third diode is electrically connected between the source of the first MOSFET MOS106 and the second pin of connector PD1. The positive terminal of the third diode is grounded and electrically connected to the signal sampling module. The gate of the second MOSFET MOS107 is electrically connected to the second enable signal of the main control chip, and the drain of the second MOSFET MOS107 is electrically connected to the signal sampling module. The negative terminal of the fourth diode is electrically connected between the source of the second MOSFET MOS107 and the third pin of connector PD1. The positive terminal of the fourth diode is grounded and electrically connected to the signal sampling module.
[0020] In conjunction with the second embodiment of the first aspect, in the third embodiment of the first aspect, the signal sampling module includes:
[0021] The first capacitor C128, the second capacitor C129, the first resistor R177, the second resistor R178, the third resistor R179, and the fourth resistor R180;
[0022] The drain of the first MOSFET MOS106 is electrically connected to the main control chip via a third resistor R179 in series. The anode of the third diode is electrically connected between the third resistor R179 and the main control chip via a first capacitor C128 and a first resistor R177 connected in parallel. The drain of the second MOSFET MOS107 is electrically connected to the main control chip via a fourth resistor R180 in series. The anode of the fourth diode is electrically connected between the fourth resistor R180 and the main control chip via a second capacitor C129 and a second resistor R178 connected in parallel.
[0023] In conjunction with the third embodiment of the first aspect, in the fourth embodiment of the first aspect, the detection circuit further includes a protocol control module, which includes:
[0024] Protocol control chip U108, Zener diode, third capacitor C131, fifth resistor R187, sixth resistor R188, and third MOSFET MOS108;
[0025] Pin 17 of the protocol control chip U108 is grounded. Pin 16 of the protocol control chip U108 is electrically connected to the source of the third MOSFET MOS108. The gate of the third MOSFET MOS108 is grounded through a series Zener diode and electrically connected to the drain of the third MOSFET MOS108 through a series fifth resistor R187. The positive terminal of the Zener diode is grounded, and the negative terminal of the Zener diode is electrically connected to the gate of the third MOSFET MOS108. The drain of the third MOSFET MOS108 is grounded through a sixth resistor R188 and a third capacitor C131 connected in series. The sixth resistor R188 and the third capacitor C131 are electrically connected to the VBUS1 terminal. Pin 3 of the protocol control chip U108 is electrically connected between the drain of the first MOSFET MOS106 and the signal sampling module. Pin 4 of the protocol control chip U108 is electrically connected between the drain of the second MOSFET MOS107 and the signal sampling module.
[0026] In conjunction with the fourth embodiment of the first aspect, in the fifth embodiment of the first aspect, the first pin of the protocol control chip U108 is electrically connected to the main control chip through a seventh resistor R189 and an eighth resistor R189 arranged in series in sequence. A ninth resistor R190 and a fourth capacitor C133 are arranged in parallel between the eighth resistor R189 and the main control chip.
[0027] In conjunction with the fourth embodiment of the first aspect, in the sixth embodiment of the first aspect, the second pin of the protocol control chip U108 is electrically connected to the main control chip through a tenth resistor R185 and an eleventh resistor R191 arranged in series in sequence. A twelfth resistor R192 and a fifth capacitor C134 are arranged in parallel between the eleventh resistor R191 and the main control chip.
[0028] In conjunction with the fourth embodiment of the first aspect, in the seventh embodiment of the first aspect, the fifth pin of the protocol control chip U108 is connected to the input voltage and grounded through the sixth capacitor C132 in series, the sixth pin of the protocol control chip U108 is grounded through the thirteenth resistor R185 in series, and the eighth pin of the protocol control chip U108 is grounded through the fourteenth resistor R186 in series.
[0029] The Type-C interface detection system of this invention has the following advantages over the prior art:
[0030] By reconfiguring and defining the pins of the first interface of the improved detection data line, both sides of the improved detection data line can be used with the matching detection circuit. The first and second enable signals transmitted by the main control chip control the conduction and disconnection of the corresponding first MOSFET MOS106 and second MOSFET MOS107. Combined with the reversible insertion control chip U107, this controls the conduction and disconnection of the second or third pin of connector PD1, thereby controlling the electrical connection between the CC1 pin on the front side of the first interface or the reconfigured and redefined CC2 pin on the reverse side and the Type-C interface of the device under test. Therefore, after using the improved detection data line and detection circuit and connecting it to the device under test, there is no need to adjust the orientation of the Type-C male connector to the Type-C interface of the device under test. The contact surface eliminates the need for secondary plugging and unplugging. The first interface, whether it's the front or back of the Type-C male connector, is selected via a single plug-and-unplug control chip U107, a MOSFET, and an analog switch. This allows for testing of the Type-C interface of the device under test with only one plug-and-unplug operation. Data transmission and reading through the first interface determine the functionality of the Type-C interface. This testing method significantly shortens the testing process, reducing testing time and cost. The main control chip controls the on / off state of the corresponding pins of the U107 connector, thereby controlling the electrical connection between the D+ or D- pin on the back of the first interface and the Type-C interface of the device under test. This ensures the test data line meets fast charging protocol requirements and satisfies the needs of fast charging applications. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 This is a schematic diagram of the pins of a Type-C female connector in the prior art;
[0033] Figure 2 A schematic diagram of the male pins of a Type-C connector in existing technology.
[0034] Figure 3 This is a schematic diagram of the Type-C interface detection system of this utility model;
[0035] Figure 4This is a schematic diagram of pins B5 to B7 on the reverse side of the first interface in the Type-C interface detection system of this utility model;
[0036] Figure 5 This is a circuit diagram of the signal sampling module and the forward / reverse insertion control module in the Type-C interface detection system of this utility model;
[0037] Figure 6 This is a circuit diagram of the forward / reverse insertion control module in the Type-C interface detection system of this utility model;
[0038] Figure 7 This is a circuit diagram of the forward / reverse insertion control module in the Type-C interface detection system of this utility model;
[0039] Figure 8 This is a circuit diagram of the main control chip in the Type-C interface detection system of this utility model. Detailed Implementation
[0040] The technical solutions of this utility model will be clearly and completely described below with reference to the embodiments of this utility model. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this utility model.
[0041] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0042] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0043] Unlike traditional USB interfaces, the Type-C interface uses a symmetrical pin design, eliminating the need to distinguish the plug's orientation and allowing for blind insertion in either direction, thus avoiding the tedious process of reversible insertion. Because Type-C supports reversible insertion, higher power delivery, and faster data transfer rates, more and more devices are adopting it as their charging and data transfer interface.
[0044] The Type-C interface is divided into female (Receptacle) and male (Plug) connectors. Please refer to [link / reference]. Figure 1 and Figure 2 Currently, when the front side of the Type-C male connector is inserted into the Type-C female connector, pins A5, A6, and A7 on the front side of the male connector are connected to pins A5, A6, and A7 on the female connector, respectively. When the back side of the Type-C male connector is inserted into the Type-C female connector, pins A5, A6, and A7 on the male connector are connected to pins B5, B6, and B7 on the female connector, thus enabling normal operation regardless of whether it is inserted in the correct orientation. However, if any of the pins A5, A6, A7, B5, B6, or B7 on the Type-C female connector has a cold solder joint, poor solder joint, or short circuit, the device will still function normally if the male connector is inserted into the female connector with a good solder joint. The device will only malfunction when the male connector is inserted into the female connector with a cold solder joint, poor solder joint, or short circuit, leading to misjudgment of the device's actual condition.
[0045] To reduce the possibility of misjudgment of the aforementioned devices, the Type-C interface (Type-C female connector) of devices now requires testing by inserting and unplugging the Type-C male connector from both sides and testing it separately. This greatly increases the testing time and cost.
[0046] In summary, in order to reduce the testing steps for the Type-C interface of the device, thereby reducing testing time and cost, an improved Type-C interface testing system is needed.
[0047] The Type-C interface testing system provided in this manual aims to offer a method for testing Type-C interfaces that significantly shortens the testing process and reduces testing time and costs.
[0048] Please see Figures 3 to 7 The system specifically includes:
[0049] The test data cable and the test circuit are provided. The test data cable has a first interface and a second interface. One end of the test data cable is configured as the first interface, and the second end of the test data cable is configured as the second interface. The first interface is a Type-C male plug, and the second interface is electrically connected to the test circuit.
[0050] like Figure 1 and Figure 2 As shown, the Type-C interface is divided into a female connector and a male connector. A complete Type-C interface has 24 pins, and the definitions of each pin are as follows:
[0051] VBUS pins: There are four VBUS voltage pins for inter-device power supply. These four pins will provide power regardless of whether the device is plugged in the correct orientation.
[0052] GND pins: There are four in total. These four pins provide power supply to devices regardless of whether the device is plugged in the right way or not.
[0053] TX+ / TX- and RX+ / RX- pins: four pairs in total, providing USB 3.0 high-speed signals;
[0054] D+ / D- pins: There are two pairs in total, providing USB 2.0 signals. At the female connector, these two pairs are shorted together.
[0055] CC / VCONN pins: The CC pin is a configuration pin used to detect device connection and orientation. It is also the communication line for the USB Power Delivery (PD) protocol. The VCONN pin is a pin that is symmetrical to the CC pin. When one pin is identified as the CC pin, the other is defined as the VCONN pin and is used to power the eMark cable.
[0056] SBU1 / SBU2 pins: Multiplexed pins, for example, to provide additional SBTX and SBRX.
[0057] The Type-C female connector has 24 pins with symmetrical pins on the top and bottom to meet the user's need for reversible insertion; the Type-C male connector has 22 pins. Currently, only one pair of D+ / D- pins is retained in the Type-C male connector, and one end of the existing Type-C data cable is configured as a Type-C male connector.
[0058] Unlike existing Type-C data cables, this testing data cable improves the first interface. Specifically, B5, B6, and B7 of the first interface are reconfigured and redefined. The B5 pin, which is the VCONN pin on the reverse side of the Type-C male connector, is configured as the CC2 pin, i.e., the CC pin on the reverse side, in this testing data cable. The B6 pin, which was originally an empty pin on the Type-C male connector, is configured as the D+ pin in this testing data cable. The B7 pin, which was originally another empty pin on the Type-C male connector, is configured as the D- pin in this testing data cable.
[0059] The pins on both sides of the first interface of this test data cable are arranged symmetrically, just like the Type-C female connector. By reconfiguring and defining the pins of the first interface of the test data cable, the improved test data cable can be used with the matching test circuit on both sides.
[0060] In this embodiment, the detection circuit includes:
[0061] The circuit comprises a main control chip, a signal sampling module, and a reversible insertion control module. Both the signal sampling module and the reversible insertion control module are electrically connected to the main control chip. The signal sampling module is electrically connected to the reversible insertion control module, which is electrically connected to the first interface via a second interface. The main control chip controls the conduction and disconnection of the CC1 and CC2 pins, as well as the reverse-side D+ and D- pins, through the reversible insertion control module. As the core of the entire control circuit, the main control chip controls the on / off state of the analog switch, which in turn controls the first interface of the test data line connected to the device under test (DUT) to be either the front or back of a Type-C male connector. Finally, data transmission and reading are performed through the first interface to determine if the Type-C interface of the DUT is functioning correctly. The main control chip can also control one pair of the two D+ / D- pins to be in a conducting state via the analog switch, thus ensuring that the test data line meets the requirements of the Quick Charge (QC) protocol.
[0062] The improved detection data line has symmetrical pins on both sides of the first interface, namely two pairs of D+ / D- pins and one pair of CC1 / CC2 pins. However, the electrical connection requirements of the QC protocol require the use of one CC pin and one pair of D+ / D- pins. In this embodiment, the switching can be completed by the signal issued by the I / O port of the main control chip, which meets the usage requirements of the QC protocol.
[0063] Specifically, the forward / reverse insertion control module includes:
[0064] The reversible insertion control chip U107, the first MOSFET MOS106, the second MOSFET MOS107, the first diode, the second diode, the third diode, the fourth diode, the first capacitor C30, and the connector PD1 constitute the reversible insertion control module, also known as the reversible insertion control circuit. The reversible insertion control chip U107 utilizes 10 pins. The first pin of the reversible insertion control chip U107 is connected to the input voltage. The second pin (Sel), the third pin (D+), and the fourth pin (D-) of the reversible insertion control chip U107 are all electrically connected to the main control chip. The third pin of the reversible insertion control chip U107 is electrically connected to the negative terminal of the first diode, and the positive terminal of the first diode is grounded. The fourth pin of the reversible insertion control chip U107 is electrically connected to the negative terminal of the second diode, and the positive terminal of the second diode is grounded. The fifth pin of the reversible insertion control chip U107, the GND pin, is grounded. The twelfth to fifteenth pins of the reversible insertion control chip U107, corresponding to the HSD1-, HSD1+, HSD2-, and HSD2+ pins respectively, are all electrically connected to the connector PD1. The sixteenth pin of the reverse insertion control chip U107, the / OE pin, is grounded and connected to the input voltage through the first capacitor C30 in series.
[0065] Connector PD1 has 8 pins. The first pin of connector PD1 is electrically connected to the VBUS1 terminal, the eighth pin of connector PD1 is grounded, and the fourth to seventh pins of connector PD1 are electrically connected to the HSD2+, HSD2-, HSD1+, and HSD1- pins of the reversible insertion control chip U107, respectively. The second and third pins of connector PD1 are electrically connected to the source of the first MOSFET MOS106 and the source of the second MOSFET MOS107, respectively. The gate of the first MOSFET MOS106 is electrically connected to the first enable signal of the main control chip, and the drain of the first MOSFET MOS106... The first diode is electrically connected to the signal sampling module. The negative terminal of the third diode is electrically connected between the source of the first MOS transistor MOS106 and the second pin of the connector PD1. The positive terminal of the third diode is grounded and electrically connected to the signal sampling module. The gate of the second MOS transistor MOS107 is electrically connected to the second enable signal of the main control chip. The drain of the second MOS transistor MOS107 is electrically connected to the signal sampling module. The negative terminal of the fourth diode is electrically connected between the source of the second MOS transistor MOS107 and the third pin of the connector PD1. The positive terminal of the fourth diode is grounded and electrically connected to the signal sampling module.
[0066] The second and third pins of connector PD1 are electrically connected to the CC1 pin (CC1-1) on the front side and the CC2 pin (CC1-2) on the back side of the first interface, respectively.
[0067] Preferably, the reversible insertion control chip U107 uses models such as FSUSB302B, FSUSB42, HUSB238A, CH224K, etc.; the main control chip uses models such as STM32G431RBT6, STM32G474RET6, STC1H361H2836A, etc., or STC series chips such as STC1H361H2836A. Based on this setup, the first and second enable signals transmitted by the main control chip can control the conduction and disconnection of the corresponding first MOSFET MOS106 and second MOSFET MOS107. Combined with the reversible insertion control chip U107, this controls the conduction and disconnection of the second or third pin of connector PD1, thereby controlling the electrical connection between the CC2 pin (CC1-1 is equivalent to the front CC1) or the CC1 pin (CC1-2 is equivalent to the back CC2) of the first interface and the Type-C interface (female) of the device under test. Therefore, after using the improved detection data line and detection circuit and connecting it to the device under test, there is no need to adjust the contact surface between the Type-C male connector and the Type-C interface of the device under test, i.e., no secondary insertion or removal is required. The reversible insertion control chip U107, the MOSFETs, and the analog switch formed by the reversible insertion control chip U107 select whether the first interface is the front or back of the Type-C male connector. Thus, only one insertion or removal is needed to test the Type-C interface of the device under test.
[0068] Specifically, the signal sampling module includes:
[0069] The first capacitor C128, the second capacitor C129, the first resistor R177, the second resistor R178, the third resistor R179, and the fourth resistor R180 constitute the signal sampling module, i.e., the voltage and current sampling circuit. Specifically, the drain of the first MOSFET MOS106 is electrically connected to the main control chip via the third resistor R179 in series. The anode of the third diode is electrically connected between the third resistor R179 and the main control chip via the first capacitor C128 and the first resistor R177 connected in parallel. The drain of the second MOSFET MOS107 is electrically connected to the main control chip via the fourth resistor R180 in series. The anode of the fourth diode is electrically connected between the fourth resistor R180 and the main control chip via the second capacitor C129 and the second resistor R178 connected in parallel.
[0070] It should be noted that the signal sampling module can perform current and voltage detection according to the QC protocol, and also has overcurrent and overvoltage detection functions. It can detect and sample the device under test, and at the same time provide short-circuit protection for the device under test.
[0071] In this embodiment, the detection circuit further includes a protocol control module, which includes:
[0072] The protocol control module, also known as the PD protocol control circuit, consists of a protocol control chip U108, a Zener diode, a third capacitor C131, a fifth resistor R187, a sixth resistor R188, and a third MOSFET MOS108. Pin 17 (GND) of the protocol control chip U108 is grounded. Pin 16 (VBUS) of the protocol control chip U108 is electrically connected to the source of the third MOSFET MOS108. The gate of the third MOSFET MOS108 is grounded via a series Zener diode and electrically connected to the drain of the third MOSFET MOS108 via a series fifth resistor R187. The anode of the Zener diode is grounded, and its cathode is electrically connected to the gate of the third MOSFET MOS108. The drain of the third MOSFET MOS108 is grounded via a series connection of the sixth resistor R188 and the third capacitor C131. The sixth resistor R188 and the third capacitor C131 are electrically connected to the VBUS1 terminal.
[0073] In order to enable the detection data line with the first interface to have PD protocol detection function, a protocol control module is set in the detection circuit. Only the part related to PD protocol control is introduced here.
[0074] Preferably, the protocol control chip U108 uses models such as HUSB238A, FSUSB42, and CH224K. With its minimalist design and high scalability, the protocol control chip U108 is an ideal solution for PD3.1 EPR powered devices. Its low power consumption, full protocol compatibility, and complete protection mechanism significantly reduce the upgrade threshold for Type-C interfaces.
[0075] The third pin, CC1, of the protocol control chip U108 is electrically connected between the drain of the first MOSFET MOS106 and the signal sampling module, and the fourth pin, CC2, of the protocol control chip U108 is electrically connected between the drain of the second MOSFET MOS107 and the signal sampling module.
[0076] In this embodiment, a protection component is provided around the protocol control chip U108. For example, the first pin, D+ pin, of the protocol control chip U108 is electrically connected to the main control chip through the seventh resistor R189 and the eighth resistor R189 connected in series. A ninth resistor R190 and a fourth capacitor C133 are connected in parallel between the eighth resistor R189 and the main control chip. The second pin, D- pin, of the protocol control chip U108 is electrically connected to the main control chip through the tenth resistor R185 and the eleventh resistor R191 connected in series. A twelfth resistor R192 and a fifth capacitor C134 are connected in parallel between the eleventh resistor R191 and the main control chip. The fifth pin, VDD pin, of the protocol control chip U108 is connected to the input voltage and grounded through the sixth capacitor C132 connected in series. The sixth pin, PORT / DBG_N pin, of the protocol control chip U108 is grounded through the thirteenth resistor R185 connected in series. The eighth pin, ADDR / ORIENT pin, of the protocol control chip U108 is grounded through the fourteenth resistor R186 connected in series.
[0077] The eighth to twelfth resistors can fix the corresponding signal line levels at a high level, stabilizing the signal line levels, reducing the impact of external noise on the signal, ensuring the reliability of data transmission, and ensuring that the circuit maintains a stable logic state when not driven by external forces. At the same time, in the configuration channel (CC1 / CC2) detection circuit of the Type-C interface, the pull-up resistors are used to identify the device insertion direction. When the Type-C interface is not inserted, the CC pin is kept at a high level through the pull-up resistor. After insertion, the CC pin level will change according to the insertion direction (such as becoming low level or floating), triggering subsequent logic judgments.
[0078] The Type-C interface detection system provided by this utility model reconfigures and defines the pins of the first interface of the detection data line, enabling both sides of the improved detection data line to cooperate with the matching detection circuit. The first and second enable signals transmitted by the main control chip control the conduction and disconnection of the corresponding first MOSFET MOS106 and second MOSFET MOS107. Combined with the reversible insertion control chip U107, the system controls the conduction and disconnection of the second or third pin of connector PD1, thereby controlling the electrical connection between the CC1 pin on the front side of the first interface or the reconfigured and redefined CC2 pin on the reverse side and the Type-C interface of the device under test. Therefore, after using the improved detection data line and detection circuit and connecting it to the device under test, there is no need to adjust the orientation of the Type-C male connector. The Type-C interface of the device does not require secondary plugging and unplugging. The first interface is selected as the front or back of the Type-C male connector by means of the forward and reverse insertion control chip U107, MOSFET, and an analog switch composed of the forward and reverse insertion control chip U107. Thus, the Type-C interface of the device under test can be tested with only one plugging and unplugging. Data transmission and reading are performed through the first interface to determine whether the Type-C interface of the device under test is good. This testing method greatly shortens the testing process and reduces testing time and cost. The main control chip controls the conduction and disconnection of the corresponding pins of the forward and reverse insertion control chip U107, thereby controlling the electrical connection of the D+ or D- pin on the reverse side of the first interface with the Type-C interface of the device under test, so that the test data line can meet the requirements of the fast charging protocol and meet the needs of fast charging application scenarios.
[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.
Claims
1. A detection system for a Type-C interface, characterized in that: The system includes: Test data cable and test circuit; The detection data cable has a first interface and a second interface. The first interface is a Type-C male connector, and the second interface is electrically connected to the detection circuit. The B5 pin on the reverse side of the first interface is configured as the CC2 pin, the B6 pin on the reverse side of the first interface is configured as the D+ pin, and the B7 pin on the reverse side of the first interface is configured as the D- pin. The detection circuit includes: The main control chip, signal sampling module, and reversible insertion control module are electrically connected to the main control chip. The signal sampling module is electrically connected to the reversible insertion control module. The reversible insertion control module is electrically connected to the first interface through the second interface. The main control chip controls the conduction and disconnection of the CC1 pin, CC2 pin, reverse D+ pin, and reverse D- pin through the reversible insertion control module.
2. The Type-C interface detection system as described in claim 1, characterized in that: The forward / reverse insertion control module includes: The components include a forward / reverse insertion control chip U107, a first MOSFET MOS106, a second MOSFET MOS107, a first diode, a second diode, a third diode, a fourth diode, a first capacitor C30, and a connector PD1. The first pin of the reversible insertion control chip U107 is connected to the input voltage. The second, third, and fourth pins of the reversible insertion control chip U107 are all electrically connected to the main control chip. The third pin of the reversible insertion control chip U107 is electrically connected to the negative terminal of the first diode, and the positive terminal of the first diode is grounded. The fourth pin of the reversible insertion control chip U107 is electrically connected to the negative terminal of the second diode, and the positive terminal of the second diode is grounded. The fifth pin of the reversible insertion control chip U107 is grounded. The twelfth to fifteenth pins of the reversible insertion control chip U107 are all electrically connected to the connector PD1. The sixteenth pin of the reverse insertion control chip U107 is grounded and connected to the input voltage through the first capacitor C30 in series. The first pin of connector PD1 is electrically connected to the VBUS1 terminal, the eighth pin of connector PD1 is grounded, the fourth to seventh pins of connector PD1 are electrically connected to the forward / reverse insertion control chip U107 respectively, and the second and third pins of connector PD1 are electrically connected to the CC1 and CC2 pins of the first interface respectively.
3. The Type-C interface detection system as described in claim 2, characterized in that: The forward / reverse insertion control module also includes: The first MOSFET is MOS106, the second MOSFET is MOS107, the third diode and the fourth diode; The second and third pins of connector PD1 are electrically connected to the source of the first MOSFET MOS106 and the source of the second MOSFET MOS107, respectively. The gate of the first MOSFET MOS106 is electrically connected to the first enable signal of the main control chip, and the drain of the first MOSFET MOS106 is electrically connected to the signal sampling module. The negative terminal of the third diode is electrically connected between the source of the first MOSFET MOS106 and the second pin of connector PD1. The positive terminal of the third diode is grounded and electrically connected to the signal sampling module. The gate of the second MOSFET MOS107 is electrically connected to the second enable signal of the main control chip, and the drain of the second MOSFET MOS107 is electrically connected to the signal sampling module. The negative terminal of the fourth diode is electrically connected between the source of the second MOSFET MOS107 and the third pin of connector PD1. The positive terminal of the fourth diode is grounded and electrically connected to the signal sampling module.
4. The Type-C interface detection system as described in claim 3, characterized in that: The signal sampling module includes: The first capacitor C128, the second capacitor C129, the first resistor R177, the second resistor R178, the third resistor R179, and the fourth resistor R180; The drain of the first MOSFET MOS106 is electrically connected to the main control chip via a third resistor R179 in series. The anode of the third diode is electrically connected between the third resistor R179 and the main control chip via a first capacitor C128 and a first resistor R177 connected in parallel. The drain of the second MOSFET MOS107 is electrically connected to the main control chip via a fourth resistor R180 in series. The anode of the fourth diode is electrically connected between the fourth resistor R180 and the main control chip via a second capacitor C129 and a second resistor R178 connected in parallel.
5. The Type-C interface detection system as described in claim 4, characterized in that: The detection circuit also includes a protocol control module, which includes: Protocol control chip U108, Zener diode, third capacitor C131, fifth resistor R187, sixth resistor R188, and third MOSFET MOS108; Pin 17 of the protocol control chip U108 is grounded. Pin 16 of the protocol control chip U108 is electrically connected to the source of the third MOSFET MOS108. The gate of the third MOSFET MOS108 is grounded through a series Zener diode and electrically connected to the drain of the third MOSFET MOS108 through a series fifth resistor R187. The positive terminal of the Zener diode is grounded, and the negative terminal of the Zener diode is electrically connected to the gate of the third MOSFET MOS108. The drain of the third MOSFET MOS108 is grounded through a sixth resistor R188 and a third capacitor C131 connected in series. The sixth resistor R188 and the third capacitor C131 are electrically connected to the VBUS1 terminal. Pin 3 of the protocol control chip U108 is electrically connected between the drain of the first MOSFET MOS106 and the signal sampling module. Pin 4 of the protocol control chip U108 is electrically connected between the drain of the second MOSFET MOS107 and the signal sampling module.
6. The Type-C interface detection system as described in claim 5, characterized in that: The first pin of the protocol control chip U108 is electrically connected to the main control chip through the seventh resistor R189 and the eighth resistor R189 set in series. The eighth resistor R189 and the main control chip are connected in parallel with the ninth resistor R190 and the fourth capacitor C133.
7. The Type-C interface detection system as described in claim 5, characterized in that: The second pin of the protocol control chip U108 is electrically connected to the main control chip through the tenth resistor R185 and the eleventh resistor R191, which are connected in series. The eleventh resistor R191 and the main control chip are connected in parallel with the twelfth resistor R192 and the fifth capacitor C134.
8. The Type-C interface detection system as described in claim 5, characterized in that: The fifth pin of the protocol control chip U108 is connected to the input voltage and grounded through the sixth capacitor C132 in series. The sixth pin of the protocol control chip U108 is grounded through the thirteenth resistor R185 in series, and the eighth pin of the protocol control chip U108 is grounded through the fourteenth resistor R186 in series.