A gigabit and 2.5G Ethernet port protection circuit

Abstract

The utility model relates to communication technical field, concretely is a kind of gigabit and 2.5G ethernet port protection circuit.The protection circuit includes: PHY side module, its anode input signal end (GPHY_MD IAP_P0) is connected to GE_AP_TSP0 through GC3, GR3, cathode input signal end (GPHY_MD IAN_P0) is connected to GE_AN_TSP0 through GC17, GR7;First TVS device (GTVS1) is connected between GE_AP_TSP0 and GE_AN_TSP0.The utility model constructs double filtering isolation network and dynamic impedance matching mechanism, integrates high-frequency ground loop, two-way TVS hierarchical protection and coupling capacitor sectional isolation in signal path, effectively solves the mutual interference problem of noise, surge and impedance mismatch under multi-rate scene.

Description

Technical Field

[0001] This utility model relates to the field of communication technology, specifically to a protection circuit for gigabit and 2.5G Ethernet ports. Background Technology

[0002] As Ethernet transmission rates evolve towards gigabit and 2.5Gbps and above, interface circuits must simultaneously meet the requirements of high-frequency signal integrity, surge protection, and wideband impedance matching. In existing technologies, filter networks and overvoltage protection devices are typically designed separately, leading to coupling conflicts between high-frequency noise suppression and surge energy dissipation paths. Especially in multi-rate scenarios, fixed-parameter filter capacitors and matching resistors are difficult to adapt to the characteristics of different frequency band signals, resulting in problems such as increased out-of-band noise coupling and residual transient overvoltage impacts. Utility Model Content

[0003] This disclosure presents a protection circuit for Gigabit and 2.5G Ethernet ports, with the aim of overcoming at least one of the defects present in the prior art.

[0004] To achieve the above objectives, the technical solution disclosed in this utility model is as follows:

[0005] According to one aspect of this disclosure, a gigabit and 2.5G Ethernet port protection circuit is provided, the protection circuit comprising:

[0006] The PHY side module has its positive input signal terminal (GPHY_MDIAP_P0) connected to GE_AP_TSP0 via GC3 and GR3, and its negative input signal terminal (GPHY_MDIAN_P0) connected to GE_AN_TSP0 via GC17 and GR7.

[0007] The first TVS device (GTVS1) is connected between GE_AP_TSP0 and GE_AN_TSP0;

[0008] The signal processing module is connected to GE_AP_TMP0 via GC9, and GE_AN_TSP0 is connected to GE_AN_TMP0 via GC13; GE_AP_TMP0 is connected to GR4 and GC4 in parallel and grounded, and GE_AN_TMP0 is connected to GR8, GC18 and GC20 in parallel and grounded.

[0009] The second TVS device (GTVS2) is connected between GE_AP_TMP0 and GE_AN_TMP0;

[0010] RJ45 side module: GE_AP_TMP0 is connected to RJ45_AP_P0 via GC10, and RJ45_AP_P0 is connected to SGND via GR1 and GC1; GE_AN_TMP0 is connected to RJ45_AN_P0 via GC14, and RJ45_AN_P0 is connected to SGND via GR11 and GC21.

[0011] Furthermore, GTVS1 is a bidirectional TVS diode, GC3 and GC17 are high-frequency filter capacitors, GR3, GR7, GR4 and GR8 are impedance matching resistors, GC9, GC13, GC10 and GC14 are signal coupling capacitors, and GR1, GR11, GC1 and GC21 form a high-frequency grounding loop.

[0012] Furthermore, the positive electrode path is connected sequentially as follows: GPHY_MDIAP_P0 via GC3 and GR3 to GE_AP_TSP0, then via GC9 to GE_AP_TMP0, and finally via GC10 to RJ45_AP_P0;

[0013] The negative path is symmetrically connected as follows: GPHY_MDIAN_P0 goes through GC17 and GR7 to GE_AN_TSP0, then through GC13 to GE_AN_TMP0, and finally through GC14 to RJ45_AN_P0.

[0014] Furthermore, GR3 and GR7 have a resistance of 22Ω±1%, GR4 and GR8 have a resistance of 56Ω±1%; GC9, GC13, GC10, and GC14 have a capacitance of 1nF-10nF; GC3 and GC17 have a capacitance of 10nF-100nF; GR1 and GR11 have a resistance of 100Ω±1%, and GC1 and GC21 have a capacitance of 1nF±5%.

[0015] Furthermore, the GTVS1 clamping voltage is ≤±30V, peak power is ≥400W, and response time is ≤1ns; the GC9 and GC13 have a dielectric loss of ≤0.01 at 2.5GHz, ESR of ≤50mΩ, and transmission loss of ≤3dB.

[0016] The beneficial effects of this utility model are:

[0017] This invention effectively solves the problem of mutual interference between noise, surge and impedance mismatch in multi-rate scenarios by constructing a dual filtering isolation network and a dynamic impedance matching mechanism, integrating a high-frequency grounding loop, bidirectional TVS hierarchical protection and segmented isolation of coupling capacitors in the signal path.

[0018] Specifically, by using a series RC grounding loop and a hierarchical layout of bidirectional TVS devices (GTVS1, GTVS2), common-mode noise is discharged to SGND through a low-impedance path. At the same time, the surge voltage is quickly clamped by utilizing the TVS response time of ≤1ns, avoiding noise reflection and residual voltage superposition caused by traditional single-stage protection.

[0019] Furthermore, based on the coordinated adjustment of coupling capacitors (GC9, GC13) and matching resistors (GR3, GR7), the transmission characteristics of signals above 2.5Gbps are dynamically adapted within the range of capacitance values ​​of 1nF-10nF and resistance values ​​of 22Ω-56Ω, so that the differential impedance fluctuates by ≤5% in the 100MHz-2.5GHz frequency band, significantly reducing high-frequency insertion loss and echo reflection.

[0020] Furthermore, by monitoring the TVS leakage current change in real time, the equivalent capacitance of the high-frequency grounding loop capacitors (GC1, GC21) is adjusted in reverse to overcome the impedance shift caused by temperature drift and device aging, ensuring a noise suppression ratio of ≥30dB and improving stability.

[0021] The above description is only an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, the preferred embodiments of this utility model are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0022] Figure 1 This is a flowchart of a method for processing gigabit and 2.5G Ethernet port signals in one embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of the overall circuit architecture of the FTTR Ethernet port in one embodiment of the present invention;

[0024] Figure 3 This is a design diagram of a Chebyshev filter and Schmitt matching circuit in one embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of the PAIR A differential signal pair circuit in one embodiment of the present invention;

[0026] Figure 5 This is a schematic diagram of the PAIR B differential signal pair circuit in one embodiment of the present invention;

[0027] Figure 6 This is a schematic diagram of the PAIR C differential signal pair circuit in one embodiment of the present invention;

[0028] Figure 7 This is a schematic diagram of the PAIR D differential signal pair circuit in one embodiment of the present invention. Detailed Implementation

[0029] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0030] In this embodiment of the invention, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in this embodiment of the invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0031] like Figures 1 to 7 As shown, the present invention provides the following preferred embodiments:

[0032] Example 1

[0033] To address the issues of high-frequency noise suppression and surge protection coupling conflicts, as well as insufficient dynamic impedance matching in traditional Ethernet interfaces, this embodiment proposes a signal processing method for Gigabit and 2.5G Ethernet ports, such as... Figure 1 As shown, the processing flow is as follows:

[0034] S100: A dual-filter isolation network is constructed on the differential signal transmission path between the RJ45 interface side and the PHY chip side. The dual-filter isolation network includes a high-frequency ground loop and a signal coupling path. The high-frequency ground loop is connected to the RJ45 interface pins (RJ45_AP_P0, RJ45_AN_P0) and signal ground (SGND) through series resistors (GR1, GR11) and capacitors (GC1, GC21). The signal coupling path is connected to the PHY chip side signal nodes (GE_AP_TMP0, GE_AN_TMP0) and RJ45 interface pins through coupling capacitors (GC10, GC14).

[0035] S200: Grounding filter capacitors (GC3, GC17) are set at the input of the PHY chip to filter out high-frequency noise from the input differential signal.

[0036] S300: A bidirectional overvoltage protection device (GTVS1) is connected between the differential signal nodes (GE_AP_TSP0, GE_AN_TSP0) on the PHY chip side, and coupling capacitors (GC9, GC13) are set between the differential signal nodes and the subsequent signal nodes (GE_AP_TMP0, GE_AN_TMP0) to form a surge voltage suppression and signal isolation structure.

[0037] S400: An impedance matching network is built on the PHY chip side. The impedance matching network includes matching resistors (GR4, GR8) and filter capacitors (GC4, GC18) connected in parallel to ground. Combined with series matching resistors (GR3, GR7), the target differential impedance of the differential signal transmission path is matched to 100Ω.

[0038] S500: Dynamically adjusts the filter network parameters according to the signal transmission rate. When the detected rate is ≥2.5Gbps, the filter characteristics are optimized by adjusting the capacitance values ​​of coupling capacitors (GC9, GC13) and the resistance values ​​of matching resistors (GR3, GR7).

[0039] S600: Real-time monitoring of the leakage current of the overvoltage protection device (GTVS1), dynamically adjusting the equivalent capacitance of the capacitors (GC1, GC21) in the high-frequency grounding circuit according to the changes in leakage current, and suppressing the interference of overvoltage on the signal.

[0040] Specifically, a high-frequency grounding loop and a signal coupling path are constructed on the differential signal transmission path between the RJ45 interface pins (RJ45_AP_P0, RJ45_AN_P0) and the PHY chip-side signal nodes (GE_AP_TMP0, GE_AN_TMP0). The high-frequency grounding loop uses a cascaded structure of series resistors (GR1, GR11) and capacitors (GC1, GC21). The resistance values ​​of GR1 and GR11 are set to 100Ω±1%, and GC1 and GC21 are NPO surface-mount capacitors with a capacitance of 1nF±5% and a withstand voltage of ≥50V. One end of the two capacitors is connected to the RJ45 interface pin, and the other end is connected to signal ground (SGND), forming a low-impedance discharge path for high-frequency noise ≥100MHz. The signal coupling path is composed of coupling capacitors (GC10, GC14). The capacitance range of GC10 and GC14 is 1nF-10nF. They are made of low-loss X7R ceramic capacitors. Their two ends are connected to the PHY chip side nodes (GE_AP_TMP0, GE_AN_TMP0) and the RJ45 interface pins, respectively, to realize the coupling transmission of AC differential signals and the isolation of DC components.

[0041] Furthermore, a grounding filter capacitor GC3 is placed between the positive input signal terminal (GPHY_MDIAP_P0) of the PHY chip and ground (GND), and a grounding filter capacitor GC17 is placed between the negative input signal terminal (GPHY_MDIAN_P0) and ground (GND). GC3 and GC17 are X7R capacitors with a capacitance of 10nF-100nF and an equivalent series inductance (ESL) ≤ 1nH. Their placement is close to the input pad of the PHY chip to minimize parasitic inductance of the leads, allowing high-frequency common-mode noise ≥100MHz to be discharged to ground through the low-impedance path of the capacitors, with a noise suppression ratio ≥30dB.

[0042] Furthermore, a bidirectional overvoltage protection device GTVS1 is connected between the differential signal nodes (GE_AP_TSP0, GE_AN_TSP0) on the PHY chip side. GTVS1 is a bidirectional TVS diode (such as SMBJ12CA) with a breakdown voltage of 12V±10% and a peak pulse power of 400W, with a response time ≤1ns, used to suppress surge voltage impacts from ±15V to ±30V. A coupling capacitor GC9 is set between GE_AP_TSP0 and the subsequent node GE_AP_TMP0, and a coupling capacitor GC13 is set between GE_AN_TSP0 and GE_AN_TMP0. Both have a capacitance range of 1nF-10nF, a withstand voltage ≥50V, and are made of C0G ceramic capacitors, used to isolate surge residual voltage and transmit effective signals.

[0043] Furthermore, on the PHY chip side, a matching resistor GR3 (22Ω±1%) is connected in series in the positive signal path, with its input terminal connected to GPHY_MDIAP_P0 and its output terminal connected to GE_AP_TSP0; a matching resistor GR7 (22Ω±1%) is connected in series in the negative signal path, with its input terminal connected to GPHY_MDIAN_P0 and its output terminal connected to GE_AN_TSP0. A matching resistor GR4 (56Ω±1%) and a filter capacitor GC4 (10nF) are connected in parallel between GE_AP_TSP0 and ground. A matching resistor GR8 (56Ω±1%) and a filter capacitor GC18 (10nF) are connected in parallel between GE_AN_TSP0 and ground. At the same time, GC20 (1nF) is connected in parallel between the ground terminal of GR8 and ground to compensate for high-frequency impedance deviation. By combining the resistance values ​​of GR3-GR4-GR7-GR8 with the capacitance values ​​of GC4-GC18-GC20, the differential impedance fluctuation of the differential signal path in the 100MHz to 2.5GHz frequency band is ≤5%, approaching the target value of 100Ω.

[0044] Furthermore, when a signal transmission rate ≥ 2.5Gbps is detected, the capacitance values ​​of coupling capacitors GC9 and GC13 are dynamically adjusted to the lower limit of 1nF using a digital potentiometer or programmable capacitor array, and the resistance values ​​of matching resistors GR3 and GR7 are simultaneously adjusted to the upper limit of 56Ω to improve the cutoff frequency and out-of-band rejection capability of high-frequency signals; when the rate < 2.5Gbps, the capacitance values ​​of GC9 and GC13 are restored to 10nF, and the resistance values ​​of GR3 and GR7 are restored to 22Ω to optimize the transmission efficiency of low-frequency signals.

[0045] Furthermore, a high-precision leakage current sensor is used to monitor the leakage current value of GTVS1 in real time. When the leakage current exceeds the threshold (e.g., 1μA), it is determined that the equivalent capacitance values ​​of GC1 and GC21 in the high-frequency grounding loop have shifted due to temperature or aging. The capacitance values ​​of GC1 and GC21 are dynamically adjusted from the nominal 1nF to 1.2nF (step accuracy ±0.05nF) through a digitally controlled capacitor array to offset the noise coupling enhancement problem caused by impedance mismatch.

[0046] The benefits of this embodiment are as follows: through the coordinated design of the high-frequency grounding loop and the signal coupling path, the path separation of noise suppression and surge protection is achieved at the physical layer; based on the dynamic parameter adjustment mechanism, the impedance matching network remains stable over a wide frequency band; and combined with the capacitive reactance compensation of leakage current feedback, the impact of overvoltage interference on signal integrity is significantly reduced.

[0047] Example 2

[0048] To address the issues of insufficient common-mode noise suppression and DC component interference caused by asymmetrical high-frequency grounding loops in traditional Ethernet interfaces, this embodiment provides a detailed implementation of a symmetrical dual-filter isolation network structure.

[0049] Furthermore, in the positive transmission path of the differential signal, series resistor GR1 (resistance 100Ω±1%, rated power 0.1W) and capacitor GC1 (capacitance 1nF±5%, withstand voltage 50V NP0 ceramic capacitor) are connected in sequence. One end of GR1 is connected to the positive pin RJ45_AP_P0 of the RJ45 interface, and the other end is connected to the non-grounded terminal of GC1. The grounded terminal of GC1 is connected to the signal ground SGND. In the negative transmission path, series resistor GR11 (parameters same as GR1) and capacitor GC21 (parameters same as GC1) are connected to RJ45_AN_P0 and SGND in the same topology to construct a high-frequency, low-impedance grounding loop. It should be understood that the symmetrical layout of GR1-GC1 and GR11-GC21 allows the high-frequency noise (≥100MHz) of the positive and negative terminals of the differential signal to be discharged to SGND through an equal impedance path, avoiding common-mode noise residue caused by path asymmetry.

[0050] Furthermore, a coupling capacitor GC10 (a C0G ceramic capacitor with a capacitance of 2.2nF ± 10% and a dielectric loss ≤ 0.01) is set between the PHY chip-side nodes GE_AP_TMP0 and RJ45_AP_P0, and a coupling capacitor GC14 (with the same parameters as GC10) is set between GE_AN_TMP0 and RJ45_AN_P0 to optimize the signal coupling path. It is understood that the capacitance values ​​of GC10 and GC14 must meet twice the capacitive reactance requirement corresponding to the lowest frequency of the transmitted signal (e.g., a cutoff frequency ≥ 1.25GHz for a 2.5Gbps signal) to ensure lossless transmission of the AC differential signal while blocking any DC bias voltage that may be introduced from the RJ45 side.

[0051] Furthermore, GR1 and GR11 employ thin-film resistors (such as the Vishay CRCW series) with a temperature coefficient ≤50ppm / ℃, ensuring a resistance deviation ≤±1.5% within the range of -40℃ to 85℃. GC1 and GC21 utilize low dielectric loss (DF≤0.1%) NPO capacitors with a capacitance-temperature characteristic of 0±30ppm / ℃ for coordinated design of grounding loop parameters, suppressing grounding loop impedance shifts caused by temperature changes. Additionally, the mounting positions of GC1 and GC21 are ≤3mm from the RJ45 pins, with lead lengths ≤1mm, thereby controlling parasitic inductance below 0.5nH and improving high-frequency noise discharge efficiency.

[0052] The advantages of this embodiment are: symmetrical discharge of common-mode noise is achieved through precise matching of the resistance and capacitance parameters of the positive and negative paths; the low-loss characteristics and optimized layout of the coupling capacitor effectively isolate DC interference and reduce signal transmission loss.

[0053] Example 3

[0054] To address the issues of insufficient high-frequency common-mode noise suppression and residual surge voltage at the PHY input, this embodiment refines the selection and layout of filter capacitors and TVS devices.

[0055] Specifically, a ground filter capacitor GC3 (22nF±10%, X7R material) is connected in parallel between the positive input signal terminal GPHY_MDIAP_P0 of the PHY chip and ground, and a GC17 (with the same parameters as GC3) is connected in parallel between the negative input signal terminal GPHY_MDIAN_P0 and ground. The equivalent series resistance (ESR) of GC3 and GC17 is ≤20mΩ, and the self-resonant frequency is ≥500MHz. They are placed in a 0402 package and adjacent to the power supply pins of the PHY chip (pitch ≤1mm) to minimize high-frequency noise path impedance. It should be understood that the capacitance change rate of X7R material is ≤±15% within the range of -55℃ to 125℃, which can meet the noise suppression requirements in a wide temperature environment.

[0056] Furthermore, a bidirectional TVS diode GTVS1 (such as a Littelfuse SMBJ12CA) is connected across the differential signal nodes GE_AP_TSP0 and GE_AN_TSP0. GTVS1 has a breakdown voltage of 12V ± 10%, a peak pulse current IPP = 50A (8 / 20μs waveform), and a junction capacitance ≤ 50pF. The cathode of GTVS1 is connected to GE_AP_TSP0, and the anode is connected to GE_AN_TSP0. The intermediate node is grounded through a 0Ω resistor (such as an RC0603 series), forming a three-terminal protection structure. It is understood that the junction capacitance of GTVS1 is connected in series with the signal line distributed capacitance (approximately 2pF), ensuring that the total equivalent capacitance is ≤ 1pF, thus preventing edge distortion for signals ≥ 2.5Gbps.

[0057] Furthermore, the mounting position of GTVS1 is ≤2mm away from the nodes of GE_AP_TSP0 and GE_AN_TSP0, and the leads use arc wiring to reduce parasitic inductance (≤3nH) and ensure that the surge current path impedance is ≤0.5Ω. Furthermore, the grounding terminals of GC3 and GC17 are connected to the analog ground plane of the PHY chip through independent vias, physically isolated from the grounding path of GTVS1, to prevent high-frequency noise from coupling to the TVS device through the ground loop.

[0058] The advantages of this embodiment are: through the coordinated layout of low ESR filter capacitors and low junction capacitance TVS, common mode noise suppression of ≥30dB is achieved over a wide temperature range; the three-terminal TVS structure combined with low impedance grounding design clamps ±30V surge voltage to below ±15V with residual voltage duration ≤10ns.

[0059] Example 4

[0060] To address the issues of impedance mismatch and dynamic rate adaptation across a wide frequency band, this embodiment refines the implementation of the impedance matching network and dynamic parameter adjustment mechanism.

[0061] Specifically, a matching resistor GR3 (33Ω±1%, thin-film resistor) is connected in series between the positive input terminal GPHY_MDIAP_P0 and node GE_AP_TSP0 of the PHY chip, and a GR7 (with the same parameters as GR3) is connected in series between the negative input terminals GPHY_MDIAN_P0 and GE_AN_TSP0. Node GE_AP_TMP0 is grounded through a parallel resistor GR4 (56Ω±1%) and a capacitor GC4 (10nF±10%, X7R material), while node GE_AN_TMP0 is grounded through parallel connections of GR8 (56Ω±1%), GC18 (10nF±10%), and GC20 (1nF±5%, NP0 material). It is important to understand that the resistor divider network formed by GR3-GR4 and GR7-GR8, combined with the capacitive reactance characteristics of GC4-GC18, makes the differential impedance approach 100Ω at 100MHz and the deviation ≤5Ω (i.e., fluctuation ≤5%) at 2.5GHz.

[0062] Furthermore, when the signal rate is ≥2.5Gbps, the coupling capacitors GC9 and GC13 are adjusted to 1nF using a digitally controlled capacitor array (such as Analog Devices AD5141), while the matching resistors GR3 and GR7 are adjusted to 56Ω using a digital potentiometer (such as Maxim MAX5401). This parameter combination effectively raises the cutoff frequency of the signal path to above 2.5GHz, achieving an out-of-band rejection ratio (OCR) ≥40dB. When the rate drops to 1Gbps, the capacitance of GC9 and GC13 returns to 10nF, and the resistance of GR3 and GR7 is adjusted to 22Ω, thereby reducing low-frequency insertion loss (≤0.5dB).

[0063] Furthermore, capacitor GC20 (1nF) is connected in parallel between the ground terminal of GR8 and ground. Its NP0 material has an equivalent series inductance (ESL) ≤0.2nH at 2.5GHz, used to offset the high-frequency impedance increase caused by the parasitic inductance of GR8 (approximately 0.5nH). Furthermore, the resistive film thickness of GR3 and GR7 is ≥0.5μm, and the sheet resistance accuracy is ≤±2%, ensuring a resistance deviation ≤±1% within the 10MHz-2.5GHz frequency band.

[0064] The advantages of this embodiment are: wide-band impedance matching is achieved through an adjustable RC network, and dynamic parameter adjustment allows the signal path to adapt to multi-rate transmission requirements; the introduction of high-frequency compensation capacitors effectively suppresses the impedance shift phenomenon as the frequency increases.

[0065] Example 5

[0066] To address the signal integrity degradation caused by the disconnect between filtering, surge suppression, and impedance matching functions in traditional Ethernet protection circuits, this embodiment provides a gigabit and 2.5G Ethernet port protection circuit, employing a modular and collaborative design for the Ethernet port protection circuit.

[0067] Specifically, a first grounding capacitor GC3 (22nF ± 10%, X7R material, rated voltage 16V) is placed between the positive input signal terminal GPHY_MDIAP_P0 of the PHY chip and ground (GND), and a second grounding capacitor GC17 (with the same parameters as GC3) is placed between the negative input signal terminal GPHY_MDIAN_P0 and ground. GC3 and GC17 are packaged in 0402 packages, with a distance of ≤1.5mm from the PHY chip input pins, a lead length of ≤0.5mm, and an equivalent series inductance (ESL) of ≤0.3nH. They are used to filter high-frequency common-mode noise ≥100MHz, with a noise suppression ratio ≥35dB. It should be understood that the capacitance stability (ΔC ≤ ±15%) of the X7R material within the range of -55℃ to 125℃ is suitable for filtering requirements in a wide temperature environment.

[0068] Furthermore, in the positive input signal path, a series resistor GR3 (resistance value 33Ω±1%, thin-film resistor, rated power 0.1W) connects GPHY_MDIAP_P0 and the first differential signal node GE_AP_TSP0; in the negative path, GR7 (parameters same as GR3) connects GPHY_MDIAN_P0 and GE_AN_TSP0. A bidirectional overvoltage protection device GTVS1 (such as Bourns CDSOT23-SM712) with a breakdown voltage of 12V±5%, a peak pulse current IPP=20A (8 / 20μs waveform), and a response time ≤0.5ns is connected between GE_AP_TSP0 and GE_AN_TSP0. Furthermore, the intermediate node of GTVS1 is grounded through a 0Ω resistor (RC0402 series), forming a low-impedance surge discharge path, clamping the ±30V surge voltage to below ±10V.

[0069] Furthermore, a first coupling capacitor GC9 (2.2nF ± 5%, C0G material) is set between the first differential signal node GE_AP_TSP0 and the subsequent node GE_AP_TMP0, and a second coupling capacitor GC13 (with the same parameters as GC9) is set between the second differential signal nodes GE_AN_TSP0 and GE_AN_TMP0. A third resistor GR4 (56Ω ± 1%) and a third capacitor GC4 (10nF, X7R material) are connected in parallel between GE_AP_TMP0 and ground; a fourth resistor GR8 (56Ω ± 1%), a fourth capacitor GC18 (10nF), and a compensation capacitor GC20 (1nF, NP0 material) are connected in parallel between GE_AN_TMP0 and ground. It can be understood that the combination of GR4-GC4 and GR8-GC18-GC20 forms complementary impedance characteristics in the 100MHz to 2.5GHz frequency band, making the differential impedance fluctuation ≤3%.

[0070] Furthermore, the subsequent node GE_AP_TMP0 is connected to the positive pin RJ45_AP_P0 of the RJ45 interface via a third coupling capacitor GC10 (2.2nF±5%, C0G material), and GE_AN_TMP0 is connected to RJ45_AN_P0 via a fourth coupling capacitor GC14 (parameters same as GC10). The mounting positions of GC10 and GC14 are ≤2mm from the RJ45 pins, and the leads use microstrip wiring (0.2mm line width, 0.15mm line spacing) to control the distributed capacitance ≤0.1pF and avoid signal edge distortion.

[0071] Furthermore, a fifth resistor GR1 (100Ω±1%) and a fifth capacitor GC1 (1nF, NP0 material) are connected in series between RJ45_AP_P0 and signal ground SGND; a sixth resistor GR11 (parameters same as GR1) and a sixth capacitor GC21 (parameters same as GC1) are connected in series between RJ45_AN_P0 and SGND. The symmetrical layout of GR1-GC1 and GR11-GC21 ensures that the high-frequency common-mode noise of the differential pair is discharged through an equal impedance path. The discharge path impedance is ≤5Ω at 100MHz, and the common-mode rejection ratio is ≥40dB.

[0072] Furthermore, GR1 and GR11 are thin-film resistors with a temperature coefficient ≤50ppm / ℃; GC1 and GC21 are NP0 ceramic capacitors with a dielectric loss tangent (DF) ≤0.001. Furthermore, GC9, GC10, GC13, and GC14 are made of C0G material with a capacitance-temperature characteristic of 0±30ppm / ℃, ensuring a capacitance value deviation ≤±0.5% within the range of -55℃ to 125℃, thus avoiding signal attenuation deviation caused by temperature.

[0073] The advantages of this embodiment are: through modular unit division and symmetrical topology design, the functions of filtering, surge protection and impedance matching are coupled; based on the low parasitic parameter layout and wide temperature stability material selection, the eye diagram opening of the differential signal path at a rate of 2.5Gbps is ≥80%, and the surge withstand capability meets the IEC 61000-4-5 Level 4 standard.

[0074] Example 6

[0075] To address the issue of insufficient synergy between noise suppression and impedance matching caused by the dispersed functionality of components in Ethernet protection circuits, this embodiment refines the selection and layout of bidirectional TVS diodes, high-frequency filter capacitors, and impedance matching resistors.

[0076] Specifically, the bidirectional TVS diode GTVS1 is a Littelfuse SMAJ12CA type device with a breakdown voltage of 12V±5%, dynamic resistance ≤0.5Ω, and junction capacitance ≤50pF. GTVS1 is connected across the differential signal nodes GE_AP_TSP0 and GE_AN_TSP0, and the intermediate ground pin is connected to the independent ground plane PGND through a wide copper foil (line width ≥0.5mm), with a lead length ≤1.5mm. It should be understood that the low junction capacitance of GTVS1 ensures that its impact on signal edge distortion in the 2.5GHz band is ≤0.1dB, while the minimization of dynamic resistance ensures that the residual voltage is ≤15V under a surge current peak of 50A (8 / 20μs waveform).

[0077] Furthermore, the first grounding capacitor GC3 and the second grounding capacitor GC17 are Murata GRM155R71H103KA88 series X7R capacitors (10nF ± 10%, rated voltage 50V), arranged symmetrically with the PHY chip input pins, with a spacing ≤ 2mm. The first resistor GR3 (22Ω ± 1%) and the second resistor GR7 (22Ω ± 1%) are Vishay CRCW0402 series thin-film resistors with a temperature coefficient ≤ 100ppm / ℃. The leads adopt a star grounding topology, allowing common-mode noise to be discharged to the ground plane nearby through GC3 and GC17. Furthermore, the third capacitor GC4 (10nF) and the fourth capacitor GC18 (10nF) are connected in parallel to the ground terminals of the matching resistors GR4 (56Ω) and GR8 (56Ω), forming a low-pass filter network with a cutoff frequency set to 160MHz to filter out out-of-band noise.

[0078] Furthermore, the first coupling capacitor GC9 and the second coupling capacitor GC13 are made of C0G material with a capacitance of 1nF ± 5%, a dielectric loss tangent ≤ 0.002, and an equivalent series inductance ≤ 0.2nH. The fifth resistor GR1 (100Ω) and the fifth capacitor GC1 (1nF) are connected in series between RJ45_AP_P0 and SGND, using a Kelvin connection to reduce contact resistance (≤ 10mΩ). It is understood that the capacitance deviation of GC1's NPO material is ≤ ± 0.3% within the temperature range of -55℃ to 125℃, ensuring the impedance stability of the high-frequency grounding loop.

[0079] The advantages of this embodiment are: by coordinating the layout of low junction capacitance TVS and high frequency filter capacitor, the functions of surge suppression and noise filtering are integrated; based on the topology optimization of star grounding and Kelvin connection, the differential impedance matching deviation in the 2.5GHz band is ≤2%.

[0080] Example 7

[0081] To address the issues of reduced common-mode noise suppression and phase distortion caused by asymmetric transmission paths in differential signals, this embodiment employs topology optimization based on symmetrical transmission paths.

[0082] Specifically, the positive input signal GPHY_MDIAP_P0 of the PHY chip is sequentially connected to GC3 (10nF) for grounding and filtering, GR3 (22Ω) for impedance matching, GE_AP_TSP0 node connected across GTVS1, GC9 (1nF) coupled to GE_AP_TMP0 node, and then grounded through GR4 (56Ω) and GC4 (10nF), finally coupled to RJ45_AP_P0 through GC10 (1nF), and then discharged to SGND through GR1 (100Ω) and GC1 (1nF). Furthermore, the layout spacing between GR3 and GR4 is ≤3mm, and the leads use equal-length serpentine routing (length tolerance ≤0.1mm) to control the transmission delay deviation of the positive path to ≤1ps. The configuration link is as follows: the positive path of differential signal transmission is connected in sequence: PHY chip positive input signal terminal (GPHY_MDIAP_P0) → first ground capacitor (GC3) → first resistor (GR3) → first differential signal node (GE_AP_TSP0) → bidirectional TVS diode (GTVS1) → first coupling capacitor (GC9) → first subsequent signal node (GE_AP_TMP0) → third resistor (GR4) in parallel with third capacitor (GC4) ground (GND) → third coupling capacitor (GC10) → RJ45 interface positive pin (RJ45_AP_P0) → fifth resistor (GR1) → fifth capacitor (GC1) → signal ground (SGND).

[0083] Furthermore, in the negative path, GPHY_MDIAN_P0 is sequentially connected to GC17 (10nF), GR7 (22Ω), the GE_AN_TSP0 node, GC13 (1nF), GR8 (56Ω), and GC18 (10nF) and GC20 (1nF) in parallel to ground. Finally, it is output to RJ45_AN_P0 via GC14 (1nF) and connected to SGND via GR11 (100Ω) and GC21 (1nF). It is important to understand that the 1nF NP0 capacitor of GC20 is connected in parallel to the ground terminal of GR8 to compensate for the impedance rise in the 2.5GHz band caused by the parasitic inductance of GR8 (approximately 0.5nH), ensuring that the impedance deviation between the positive and negative paths is ≤1Ω. The configuration link is as follows: PHY chip negative input signal terminal (GPHY_MDIAN_P0) → second ground capacitor (GC17) → second resistor (GR7) → second differential signal node (GE_AN_TSP0) → bidirectional TVS diode (GTVS1) → second coupling capacitor (GC13) → second subsequent signal node (GE_AN_TMP0) → fourth resistor (GR8) in parallel with fourth capacitor (GC18) and capacitor (GC20) grounded (GND) → fourth coupling capacitor (GC14) → RJ45 interface negative pin (RJ45_AN_P0) → sixth resistor (GR11) → sixth capacitor (GC21) → signal ground (SGND). The symmetrical layout reduces the signal phase deviation.

[0084] Furthermore, GR3 and GR7 are thin-film resistors manufactured from the same wafer batch, with a resistance deviation of ≤±0.5%; the mounting positions of GC9 and GC13 are symmetrical about the differential pair centerline, with a spacing tolerance of ≤0.05mm. Furthermore, the leads of GC10 and GC14 adopt a differential microstrip line structure (0.15mm linewidth, 0.3mm line spacing), with characteristic impedance controlled at 100Ω±3% to reduce signal reflection.

[0085] The advantages of this embodiment are: through the step-by-step mirror symmetry design of the positive and negative paths, the common-mode noise rejection ratio is improved to ≥45dB; based on equal-length wiring and parasitic parameter compensation, the phase deviation of the 2.5Gbps signal is controlled within ±5°.

[0086] Example 8

[0087] To address the issues of insufficient impedance matching accuracy across wide bandwidths and compatibility with multi-rate signals, this embodiment implements optimized implementation based on RC parameter configuration.

[0088] Specifically, GR3 and GR7 use 22Ω±1% thin-film resistors with a temperature coefficient ≤50ppm / ℃ and a rated power of 0.1W; GR4 and GR8 use 56Ω±1% resistors with a sheet resistance error ≤±0.5%. The resistance combinations of GR3-GR7 and GR4-GR8 result in a differential impedance of 100Ω±1Ω at 100MHz and a deviation ≤3Ω at 2.5GHz. Understandably, the low temperature drift characteristic of the resistors ensures impedance fluctuation ≤±1.5% within the range of -40℃ to 125℃.

[0089] Furthermore, coupling capacitors GC9-GC14 are selected as 1nF C0G capacitors (capacitance deviation ±5%), with an equivalent series resistance ≤30mΩ at 2.5GHz and a self-resonant frequency ≥3GHz. Grounding capacitors GC3 and GC17 are 10nF X7R capacitors with a dielectric loss tangent ≤0.025°, and are connected to an independent grounding layer via dual vias to reduce lead inductance (≤0.8nH). Furthermore, the high-frequency grounding loop GR1 and GR11 are selected as Susumu RR0510P-101-D type 100Ω±1% resistors, which, when connected in series with the 1nF NP0 capacitors of GC1 and GC21, achieve a common-mode discharge impedance ≤5Ω at 100MHz.

[0090] Furthermore, when the signal rate is 1Gbps, the 1nF capacitance of GC9-GC14 and the 22Ω resistance of GR3-GR7 combine to form a high-pass characteristic with a cutoff frequency of ≈7.2GHz; when the rate is switched to 2.5Gbps, the capacitance of GC9-GC14 is adjusted to 2.2nF by an external digital control switch, and the resistance of GR3-GR7 is switched to 33Ω, so that the cutoff frequency is increased to ≈4.5GHz, which can meet the needs of higher frequency signal transmission.

[0091] The advantages of this embodiment are: based on high-precision RC parameter configuration and dynamic switching mechanism, impedance matching accuracy of ≥96% is achieved in the 100MHz-2.5GHz frequency band; through adjustable cutoff frequency design, the signal path is adapted to dual-rate transmission of 1Gbps and 2.5Gbps.

[0092] Example 9

[0093] To address the issues of insufficient response speed and excessive high-frequency signal transmission loss in TVS devices, this embodiment optimizes the implementation based on the TVS clamping characteristics and the dielectric loss requirements of the coupling capacitor.

[0094] Specifically, the bidirectional TVS diode GTVS1 has a clamping voltage ≤30V (test condition IPP=5A), a peak pulse power of 600W (8 / 20μs waveform), and a response time ≤0.5ns. The cathode and anode of GTVS1 are connected to GE_AP_TSP0 and GE_AN_TSP0 respectively via wide copper foil (line width ≥0.6mm), with the intermediate ground pin directly pressed to a 2oz thick copper ground plane. The total inductance of the surge discharge path is ≤3nH. It should be understood that the junction capacitance of this TVS is ≤15pF, and the additional delay at the signal edge in the 2.5GHz band is ≤0.05ns.

[0095] Furthermore, coupling capacitors GC9 and GC13 are 1nF C0G capacitors with a dielectric loss tangent ≤0.001 and an equivalent series resistance ≤20mΩ. A coplanar waveguide structure (0.2mm linewidth, 0.1mm dielectric layer thickness) is used in the layout to achieve a distributed capacitance ≤0.05pF. Furthermore, GC10 and GC14 are 2.2nF capacitors from the same series, with an insertion loss ≤0.2dB and a phase linearity deviation ≤±1° / GHz in the 2.5GHz band.

[0096] Furthermore, the mounting positions of GC9-GC13 are ≤1.5mm away from the TVS device GTVS1, and the leads use curved wiring to reduce impedance surges caused by right-angle bends. The TVS grounding path is isolated from the signal ground plane by a ferrite bead to suppress high-frequency noise backflow. Understandably, the above design ensures that the total loss of the 2.5Gbps signal after passing through the protection circuit is ≤1.8dB, and the eye diagram jitter is ≤0.05UI.

[0097] The advantages of this embodiment are: by selecting ultrafast TVS and ultra-low loss capacitors, ns-level response suppression of ≤30V surge voltage can be achieved; based on coplanar waveguide layout and parasitic parameter control, the transmission loss of 2.5GHz signal is ≤2dB and the eye diagram compliance rate is ≥99%.

[0098] Example 10

[0099] To address the issue of insufficient adaptability to dynamic environments caused by fixed parameters in traditional Ethernet protection circuits, this embodiment integrates a signal processing module, protection circuit, and control module to construct an intelligent signal processing system with real-time parameter adjustment capabilities.

[0100] Specifically, the filter network control unit integrates a Johanson 2400 series programmable capacitor array (GC1, GC9, GC13, GC21 with capacitance adjustment range of 1nF-10nF and step accuracy of ±0.5nF) and an ADI AD5272 digital potentiometer (GR1, GR3, GR7, GR11 with resistance adjustment range of 50Ω-150Ω and resolution of 0.1Ω). GC1 and GC21 are connected via I...2 The AD5272 receives commands from the MCU via the C bus and dynamically adjusts the capacitance value according to a preset frequency response curve within the 10MHz to 2.5GHz frequency band to suppress noise at specific frequencies (such as 1.8GHz cellular interference). It's important to understand that the AD5272's end-to-end resistance temperature coefficient is ≤25ppm / ℃, ensuring that the temperature drift error during resistance adjustment is ≤±0.3%.

[0101] Furthermore, the impedance matching adjustment unit is equipped with Vishay 64W digital potentiometers (GR4, GR8, resistance range 20Ω-100Ω) and Murata DTC series adjustable capacitors (GC4, GC18, GC20, capacitance range 2.2nF-22nF). When the system detects a signal rate switch from 1Gbps to 2.5Gbps, the resistance of GR4 / GR8 changes from 56Ω to 33Ω, while the capacitance of GC4 / GC18 is adjusted from 10nF to 4.7nF, maintaining the differential impedance at 100Ω ± 2%. It is understood that this unit interconnects with the MCU via an SPI interface, supporting closed-loop feedback control based on eye diagram opening.

[0102] Furthermore, the surge monitoring unit employs a LEM HLSR32-P leakage current sensor to acquire the leakage current signal of the TVS device GTVS1 in real time (range 0-10mA, accuracy ±1μA). When the leakage current exceeds a threshold (e.g., 5mA), the sensor output signal is converted into a digital value by a TI ADS131A04 24-bit ADC (sampling rate 4kSPS, ENOB≥21 bits), and input to the MCU for proportional-integral (PI) calculation. Further, based on the calculation result, the MCU controls the programmable capacitor array of GC1 / GC21, gradually increasing the capacitance value from 1nF to 10nF to enhance the noise discharge capability of the high-frequency grounding loop.

[0103] Furthermore, the microcontroller selected is an STM32G474 (170MHz main frequency, built-in FPU), with its PI algorithm parameters set as proportional coefficient Kp = 0.8 and integral time Ti = 50ms. When the instantaneous leakage current of GTVS1 is ≥3mA, the MCU outputs a PWM signal to drive the adjustable capacitors GC1 / GC21, dynamically adjusting their capacitance value according to the following formula:

[0104] Where C(t) represents the capacitance value after real-time adjustment, C0 is the initial capacitance value (1nF), e(t) is the leakage current deviation value, and K p T represents the proportional coefficient, used to adjust the contribution weight of the current error value to the capacitor adjustment. iThe integration time constant controls the rate at which historical error accumulation affects the capacitance adjustment. t0 represents the initial time, the start of integration, typically taken as the system timestamp at algorithm startup. t represents the current time, the end of integration, dynamically updated to the latest time point during algorithm execution. It's important to understand that this formula ensures the capacitance adjustment response time of GC1 / GC21 is ≤10ms, guaranteeing rapid restoration of impedance matching after a surge event.

[0105] Furthermore, the system incorporates an NXP KTY82 series temperature sensor (accuracy ±0.5℃) to monitor the operating temperature of the GR3 / GR7 resistors in real time. When the temperature exceeds 85℃, the MCU compensates for the impedance shift caused by the temperature rise by reducing the resistance of GR3 / GR7 (22Ω→18Ω) and increasing the capacitance of GC3 / GC17 (10nF→22nF). Additionally, the MCU has built-in fault diagnosis logic: if the resistance deviation of GR3 / GR7 persists for more than ±5% for 100ms, it is determined that the resistor is aging, triggering an alarm signal and switching to the redundant impedance matching branch.

[0106] The advantages of this embodiment are: by combining programmable components with closed-loop control algorithms, dynamic optimization of filtering, impedance matching and surge protection parameters can be achieved; based on multi-sensor data fusion and PI algorithm, the signal transmission loss fluctuation of the system in the environment of -40℃~105℃ is ≤±0.2dB, and the lifespan of TVS devices is extended by ≥30%.

[0107] Although the present invention has been specifically described above with reference to preferred embodiments, it should be understood that the present invention is not limited to the embodiments described above. Rather, various modifications and variations can be made by those skilled in the art without departing from the essence of the present invention, and such modifications and variations should fall within the scope defined by the appended claims and their equivalents.

Claims

1. A protection circuit for gigabit and 2.5G Ethernet ports, characterized in that, The protection circuit includes: The PHY side module has its positive input signal terminal (GPHY_MDIAP_P0) connected to GE_AP_TSP0 via GC3 and GR3, and its negative input signal terminal (GPHY_MDIAN_P0) connected to GE_AN_TSP0 via GC17 and GR7. The first TVS device (GTVS1) is connected between GE_AP_TSP0 and GE_AN_TSP0; The signal processing module is connected to GE_AP_TMP0 via GC9, and GE_AN_TSP0 is connected to GE_AN_TMP0 via GC13; GE_AP_TMP0 is connected to GR4 and GC4 in parallel and grounded, and GE_AN_TMP0 is connected to GR8, GC18 and GC20 in parallel and grounded. The second TVS device (GTVS2) is connected between GE_AP_TMP0 and GE_AN_TMP0; RJ45 side module: GE_AP_TMP0 is connected to RJ45_AP_P0 via GC10, and RJ45_AP_P0 is connected to SGND via GR1 and GC1; GE_AN_TMP0 is connected to RJ45_AN_P0 via GC14, and RJ45_AN_P0 is connected to SGND via GR11 and GC21.

2. The gigabit and 2.5G Ethernet port protection circuit as described in claim 1, characterized in that, GTVS1 is a bidirectional TVS diode, GC3 and GC17 are high-frequency filter capacitors, GR3, GR7, GR4 and GR8 are impedance matching resistors, GC9, GC13, GC10 and GC14 are signal coupling capacitors, and GR1, GR11, GC1 and GC21 form a high-frequency grounding loop.

3. The gigabit and 2.5G Ethernet port protection circuit as described in claim 1, characterized in that, The positive path is connected sequentially as follows: GPHY_MDIAP_P0 through GC3 and GR3 to GE_AP_TSP0, then through GC9 to GE_AP_TMP0, and finally through GC10 to RJ45_AP_P0; The negative path is symmetrically connected as follows: GPHY_MDIAN_P0 goes through GC17 and GR7 to GE_AN_TSP0, then through GC13 to GE_AN_TMP0, and finally through GC14 to RJ45_AN_P0.

4. The gigabit and 2.5G Ethernet port protection circuit as described in claim 1, characterized in that, GR3 and GR7 have a resistance of 22Ω ±1%; GR4 and GR8 have a resistance of 56Ω ±1%; GC9, GC13, GC10, and GC14 have a capacitance of 1nF-10nF; GC3 and GC17 have a capacitance of 10nF-100nF; GR1 and GR11 have a resistance of 100Ω ±1%; and GC1 and GC21 have a capacitance of 1nF ±5%.

5. The gigabit and 2.5G Ethernet port protection circuit as described in claim 1, characterized in that, GTVS1 clamping voltage ≤ ±30V, peak power ≥ 400W, response time ≤ 1ns; GC9 and GC13 at 2.5GHz have dielectric loss ≤ 0.01, ESR ≤ 50mΩ, and transmission loss ≤ 3dB.

Images