Display device, driving chip, phase-locked loop circuit, and voltage-controlled oscillator

Abstract

This utility model discloses a display device, a driver chip, a phase-locked loop circuit, and a voltage-controlled oscillator, comprising: a voltage-to-current conversion circuit for converting a first control voltage into a control current; a ring oscillator having a first voltage terminal and a second voltage terminal, the first voltage terminal being connected to the output terminal of the control current, the ring oscillator being used to generate multiple clock signals of different phases based on the control current; and a voltage adjustment circuit connected to the second voltage terminal of the ring oscillator for adjusting the voltage of the first voltage terminal according to the operating frequency of the voltage-controlled oscillator, thereby increasing the swing of the multiple clock signals of different phases output by the ring oscillator.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, and in particular to a display device, a driver chip, a phase-locked loop circuit, and a voltage-controlled oscillator. Background Technology

[0002] The voltage-controlled oscillator (VCO) is a crucial component of the phase-locked loop (PLL) circuit, affecting the output signal quality, system operating speed, and loop phase margin of the PLL system. In display driver chips, the PLL typically requires multi-phase clock outputs for pulse width modulation (PWM) modules. Mismatches between different phase clocks can impact PWM module performance; therefore, it is necessary to reduce the phase difference between the multi-phase clocks.

[0003] Figure 1 A schematic diagram of a phase-locked loop circuit according to the prior art is shown. See also Figure 1 The phase-locked loop circuit 100 includes a phase-frequency discriminator 110, a charge pump circuit 120, a loop filter 130, a voltage-controlled oscillator 140, and a frequency divider 150. The frequency divider 150 receives the output clock CLK_OUT from the voltage-controlled oscillator 140 and divides it to obtain a feedback clock signal. This feedback clock signal is output to the input of the phase-frequency discriminator 110 and compared in phase with a reference clock CLK_REF. The comparison result is converted into a voltage signal by the charge pump circuit 120. This voltage signal is then filtered by the loop filter 130 to obtain a control voltage Vctrl, which is used to adjust the clock signal CLK_OUT output by the voltage-controlled oscillator 140.

[0004] Existing voltage-controlled oscillators (VCOs) 140 require a level shifter to convert the voltage domain of the VCO's output clock CLK_OUT to a range between the power supply voltage VDD and ground. However, this introduces additional mismatch and power consumption. Specifically, when the VCO operates at lower frequencies, the smaller swing of the output clock CLK_OUT leads to mismatch when passing through the level shifter. Conversely, at higher frequencies, the power consumption of the level shifter is significant. Therefore, a new VCO is needed to address these issues. Utility Model Content

[0005] In view of the above problems, the purpose of this utility model is to provide a display device, a driver chip, a phase-locked loop circuit, and a voltage-controlled oscillator, thereby improving the swing amplitude of multiple clock signals with different phases output by the ring oscillator.

[0006] According to one aspect of the present invention, a voltage-controlled oscillator is provided, comprising a voltage-to-current conversion circuit for converting a first control voltage into a control current; a ring oscillator having a first voltage terminal and a second voltage terminal, the first voltage terminal being connected to the output terminal of the control current, the ring oscillator being used to generate multiple clock signals of different phases based on the control current; and a voltage adjustment circuit connected to the second voltage terminal of the ring oscillator for adjusting the voltage of the first voltage terminal according to the operating frequency of the voltage-controlled oscillator.

[0007] Optionally, the voltage adjustment circuit includes a first transistor, with a first terminal connected to the second voltage terminal, a second terminal connected to the ground terminal, and a control terminal connected to the first voltage terminal.

[0008] Optionally, the voltage adjustment circuit includes a second transistor, with its first end connected to the second voltage terminal and its second end connected to the ground terminal; and a third transistor, with its first end connected to the voltage-to-current conversion circuit, its second end connected to the ground terminal, and its control terminal connected to its first end and the control terminal of the second transistor.

[0009] Optionally, the ring oscillator includes a plurality of first delay units cascaded in sequence. Each first delay unit has a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. The clock signals output by the positive output terminal and the negative output terminal of each first delay unit have different phases. Specifically, the positive input terminal of the next stage first delay unit is connected to the negative output terminal of the previous stage first delay unit, and the negative input terminal of the next stage first delay unit is connected to the positive output terminal of the previous stage first delay unit. The positive input terminal of the first stage first delay unit is connected to the positive output terminal of the last stage first delay unit, and the negative input terminal of the first stage first delay unit is connected to the negative output terminal of the last stage first delay unit.

[0010] Optionally, the voltage adjustment circuit includes at least one second delay unit, which is cascaded sequentially with the plurality of first delay units. The structure of the second delay unit is the same as that of the first delay unit. Specifically, the positive input terminal of the subsequent delay unit is connected to the negative output terminal of the preceding delay unit, and the negative input terminal of the subsequent delay unit is connected to the positive output terminal of the preceding delay unit. The positive input terminal of the first delay unit is connected to the positive output terminal of the last delay unit, and the negative input terminal of the first delay unit is connected to the negative output terminal of the last delay unit.

[0011] Optionally, the voltage-to-current conversion circuit includes a fourth transistor, a fifth transistor, and a first resistor, which are sequentially connected between the power supply voltage and the ground terminal. The control terminal of the fourth transistor is connected to its second terminal, and the control terminal of the fifth transistor receives the first control voltage. A sixth transistor has its first terminal connected to the power supply voltage, its second terminal connected to the first terminal of the third transistor, and its control terminal connected to the control terminal of the fourth transistor. A seventh transistor has its first terminal connected to the power supply voltage, its second terminal connected to the first voltage terminal, and its control terminal connected to the control terminal of the fourth transistor.

[0012] Optionally, the voltage-controlled oscillator further includes multiple level shifters, each level shifter being used to convert the voltage domain of one of the multiple clock signals of different phases from a first voltage domain to a second voltage domain. Each level shifter includes a first current branch for controlling the conduction and cutoff of its current path according to the clock signal output by the level shifter and a first input signal; a second current branch for controlling the conduction and cutoff of its current path according to a second input signal; an inverter with its input terminal connected to the second current branch and its output terminal serving as the output terminal of the level shifter to provide the clock signal after the voltage domain conversion is completed; and a pull-up circuit for selectively pulling up the input voltage of the inverter according to the clock signal output by the level shifter, wherein the second input signal is the clock signal that needs to be converted into a voltage domain, and the first input signal is inverted from the second input signal.

[0013] Optionally, the first current branch includes an eighth transistor, a ninth transistor, and a tenth transistor, connected sequentially between the power supply voltage and the ground voltage. The control terminal of the eighth transistor is connected to its second terminal, the control terminal of the ninth transistor receives the first input signal, and the control terminal of the tenth transistor is connected to the output terminal of the inverter. The second current branch includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor, connected sequentially between the power supply voltage and the ground voltage. The control terminal of the eleventh transistor is connected to the control terminal of the eighth transistor, the control terminal of the twelfth transistor receives the second input signal, and the control terminal of the thirteenth transistor receives a second control voltage. The intermediate node between the eleventh and twelfth transistors is connected to the input terminal of the inverter. The pull-up circuit includes a fourteenth transistor and a fifteenth transistor, connected sequentially between the power supply voltage and the intermediate node between the eleventh and twelfth transistors. The control terminal of the fifteenth transistor is connected to the output terminal of the inverter, and the control terminal of the fourteenth transistor receives a bias voltage. The fourteenth transistor is always in the on state during the operation of the level converter.

[0014] According to a second aspect of the present invention, a phase-locked loop circuit is provided, comprising a frequency and phase detector for receiving a reference clock signal and a feedback clock signal, and generating a pulse control signal based on a phase comparison of the reference clock signal and the feedback clock signal; a charge pump for outputting a corresponding voltage signal according to the pulse control signal; a loop filter for generating a corresponding control voltage according to the output voltage of the charge pump; a voltage-controlled oscillator as described above; and a frequency divider for performing frequency division processing on the clock signal output by the voltage-controlled oscillator to generate the feedback clock signal.

[0015] According to a third aspect of this utility model, a driver chip is provided, including the phase-locked loop circuit described above.

[0016] According to a fourth aspect of the present invention, a display device is provided, comprising the driving chip described above.

[0017] The display device, driver chip, phase-locked loop circuit, and voltage-controlled oscillator provided by this utility model have a voltage adjustment circuit that adjusts the voltage at the first voltage terminal of the ring oscillator according to the operating frequency of the voltage-controlled oscillator, thereby increasing the swing of multiple clock signals with different phases output by the ring oscillator and reducing the mismatch when each clock signal output by the ring oscillator passes through the level converter, thus reducing the mismatch between multiple clock signals with different phases output by the voltage-controlled oscillator.

[0018] Furthermore, the voltage-controlled oscillator also includes multiple level shifters. Each level shifter is used to convert the voltage domain of one of the multiple clock signals of different phases output by the ring oscillator. When the clock signal for which voltage domain conversion is required is low, each level shifter shuts off the current path of its first current branch, reducing the power consumption of the level shifter and thus reducing the overall power consumption of the voltage-controlled oscillator. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

[0020] Figure 1 A schematic diagram of a phase-locked loop circuit according to the prior art is shown;

[0021] Figure 2 A circuit diagram of a voltage-controlled oscillator is shown;

[0022] Figure 3 A circuit diagram of a level converter is shown;

[0023] Figure 4 A schematic diagram of the structure of a voltage-controlled oscillator according to an embodiment of the present invention is shown;

[0024] Figure 5 A circuit diagram of a voltage-controlled oscillator according to a first embodiment of the present invention is shown;

[0025] Figure 6 A circuit diagram of a voltage-controlled oscillator according to a second embodiment of the present invention is shown;

[0026] Figure 7 A circuit diagram of a voltage-controlled oscillator according to a third embodiment of the present invention is shown;

[0027] Figure 8 A circuit diagram of a level converter according to an embodiment of the present invention is shown. Detailed Implementation

[0028] Various embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0029] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0030] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0031] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0032] Figure 2 A circuit diagram of a voltage-controlled oscillator is shown. Figure 2 The voltage-controlled oscillator 140 includes transistors MP1 and MN1 and a resistor R2 connected sequentially between the power supply voltage VDD and the ground terminal, and transistor MP2 and a ring oscillator connected sequentially between the power supply voltage VDD and the ground terminal. The control terminal of transistor MP1 is connected to its second terminal and the control terminal of transistor MP2. The control terminal of transistor MN1 receives a control voltage Vctrl. The ring oscillator is implemented using four cascaded delay units 141_1-141_4 with differential input and differential output. In the four delay units 141_1-141_4, the positive input IN+ of the subsequent delay unit is connected to the negative output OUT- of the preceding delay unit, and the negative input IN- of the subsequent delay unit is connected to the positive output OUT+ of the preceding delay unit. The positive input IN+ of the first-stage delay unit 141_1 is connected to the positive output OUT+ of the last-stage delay unit 141_4, and the negative input IN- of the first-stage delay unit 141_1 is connected to the negative output OUT- of the last-stage delay unit 141_4.

[0033] Transistor MN1 converts the control voltage Vctrl into a linearly related bias current. This bias current is mirrored by transistor MP2 to obtain the control current Ic. The ring oscillator generates multiple clock signals with different phases based on the control current Ic. Resistor R2 is used to improve the linearity of the bias current following the changes in the control voltage Vctrl.

[0034] exist Figure 2 In the example, since the output swing of the ring oscillator follows the change of the drain voltage of transistor MP2, i.e., the voltage Vosc of the first voltage terminal of the ring oscillator, a level converter needs to be connected after the delay unit to convert the voltage domain of the clock signal output by the ring oscillator to between the power supply voltage VDD and the ground voltage.

[0035] Figure 3 A circuit diagram of a level shifter is shown. See also Figure 3 The level converter includes a first current branch, a second current branch, and an inverter INV. The first current branch includes transistors MP3, MN2, and MN4 connected sequentially between the power supply voltage VDD and the ground voltage GND. The second current branch includes transistors MP4, MN3, and MN5 connected sequentially between the power supply voltage VDD and the ground voltage GND. The input terminal of the inverter INV is connected to the intermediate node between transistors MP4 and MN3. The output terminal of the inverter INV provides a clock signal CKO. The control terminal of transistor MP3 is connected to its second terminal and the control terminal of transistor MP4. The control terminals of transistors MN2 and MN3 receive input signals INN and INP, respectively. The control terminals of transistors MN4 and MN5 receive a control voltage PDN, which is used to control the level converter to turn on and off.

[0036] exist Figure 3 In the level converter shown, when the input signal INP is high, transistor MN3 is turned on and transistor MN4 is turned off, so there is no extra power consumption in the circuit. When the input signal INN is high, the input signal INP does not need to be converted to the voltage domain, but the first current branch is always on, resulting in a large power consumption of the circuit.

[0037] exist Figure 2 In the voltage-controlled oscillator 140 shown, each delay unit outputs two clock signals of different phases, namely OUT+ and OUT-. When the voltage-controlled oscillator 140 needs to output eight-phase clock signals, the output terminal of each clock signal needs to be connected to a level converter. Therefore, a total of eight level converters are needed for voltage domain conversion. When the clock signal OUT+ output by any delay unit is level-converted, the input signal INP is the clock signal OUT+ of that delay unit, and the input signal INN is the clock signal OUT- of that delay unit. When the clock signal OUT- output by any delay unit is level-converted, the input signal INP is the clock signal OUT- of that delay unit, and the input signal INN is the clock signal OUT+ of that delay unit.

[0038] In passing Figure 3The level converter shown introduces mismatch and power consumption in the process of converting the voltage domain of the eight-phase clock signal from voltage Vosc to ground voltage GND and then from power supply voltage VDD to ground voltage GND. Specifically, when the voltage-controlled oscillator 140 operates at a lower frequency, the current flowing through transistor MP2 is smaller, and the voltage Vosc is lower. At this time, the swing of the multiple clock signals of different phases output by the ring oscillator is smaller, resulting in mismatch when the clock signal passes through the level converter. When the voltage-controlled oscillator 140 operates at a higher frequency, the voltage Vosc is higher, but the power consumption of the level converter is also larger.

[0039] To address the aforementioned issues, this application improves the voltage-controlled oscillator 140 to increase the output clock swing of the ring oscillator under low-frequency conditions, reduce the mismatch of multi-phase clocks, and lower the overall power consumption of the voltage-controlled oscillator under high-frequency conditions.

[0040] Figure 4 A circuit diagram of a voltage-controlled oscillator according to an embodiment of the present invention is shown.

[0041] See Figure 4 The voltage-controlled oscillator 200 provided in this embodiment includes a voltage-to-current conversion circuit 210, a ring oscillator 220, and a voltage adjustment circuit 230.

[0042] The voltage-to-current conversion circuit 210 is used to convert the control voltage Vctrl into a control current Ic, which is linearly related to the control voltage Vctrl.

[0043] The ring oscillator 220 has a first voltage terminal and a second voltage terminal. The first voltage terminal is connected to the output terminal of the control current Ic. The ring oscillator 220 is used to generate multiple clock signals with different phases based on the control current Ic. Furthermore, the voltage difference between the first voltage terminal and the second voltage terminal of the ring oscillator 220 is greater than zero.

[0044] The voltage adjustment circuit 230 is connected to the ring oscillator 220 and is used to adjust the voltage Vosc at the first voltage terminal of the ring oscillator 220 according to the operating frequency of the voltage-controlled oscillator 200, so as to increase the swing of the multiple clock signals with different phases output by the ring oscillator 220, so that the swing of the multiple clock signals with different phases output by the ring oscillator 220 is greater than the swing of the multiple clock signals with different phases output by the ring oscillator in the prior art.

[0045] Figure 5 A circuit diagram of a voltage-controlled oscillator according to a first embodiment of the present invention is shown.

[0046] See Figure 5In the first embodiment of this utility model, the voltage-to-current conversion circuit 210 includes transistors MP1 and MN1, and a resistor R2 connected sequentially between the power supply voltage VDD and the ground terminal, and transistor MP2 connected between the power supply voltage VDD and the first voltage terminal of the ring oscillator 220. The control terminal of transistor MN1 receives the control voltage Vctrl, and the control terminal of transistor MP1 is connected to its first terminal and the control terminal of transistor MP2. Transistor MN1 is used to convert the control voltage Vctrl into a bias current linearly related to it, and transistor MP2 mirrors this bias current to obtain the control current Ic. In other examples of this application, the voltage-to-current conversion circuit 210 may not include resistor R2, in which case the second terminal of transistor MN1 is directly grounded. In this application, the function of resistor R2 is to improve the linearity of the control current Ic following the change of control voltage Vctrl.

[0047] The ring oscillator 220 includes multiple cascaded first delay units. Each first delay unit has a positive input, a negative input, a positive output, and a negative output. The positive input receives the input signal IN+, the negative input receives the input signal IN-, the positive output provides the clock signal OUT+, and the negative output provides the clock signal OUT-. The clock signals OUT- and OUT+ have different phases. In the multiple first delay units, the positive input of the subsequent first delay unit is connected to the negative output of the preceding first delay unit, and the negative input of the subsequent first delay unit is connected to the positive output of the preceding first delay unit. The positive input of the first delay unit is connected to the positive output of the last first delay unit, and the negative input of the first delay unit is connected to the negative output of the last first delay unit. Figure 5 Taking the ring oscillator 220 in the example, which is implemented using four cascaded first delay units 221_1-221_4, it can output an eight-phase clock signal.

[0048] Understandably, although Figure 5 In the example, the ring oscillator 220 is implemented using four cascaded delay units 221_1-221_4. However, in practical applications, the number of delay units is not specifically limited and can be set as needed.

[0049] The voltage regulation circuit 230 includes a transistor MN6 connected between the second voltage terminal of the ring oscillator 220 and the ground terminal. The control terminal of the transistor MN6 is connected to the first voltage terminal of the ring oscillator 220. The transistor MN6 is used for negative feedback regulation of the voltage Vosc at the first voltage terminal of the ring oscillator 220.

[0050] In this embodiment, the voltage adjustment circuit 230 increases the voltage Vosc by Vds1 compared to the prior art, where Vds1 represents the voltage difference between the drain and source terminals of transistor MN6. When the operating frequency of the voltage-controlled oscillator 200 is low, the voltage value of Vosc is low, resulting in a smaller voltage difference Vgs between the gate and source terminals of transistor MN6 and a larger voltage difference Vds1 between the drain and source terminals, thus increasing the voltage Vosc by a larger margin compared to the prior art. When the operating frequency of the voltage-controlled oscillator 200 is high, the voltage value of Vosc is high, resulting in a larger voltage difference Vgs between the gate and source terminals of transistor MN6 and a smaller voltage difference Vds1 between the drain and source terminals. In this case, the increase in voltage Vosc by transistor MN6 is small and can be ignored. Therefore, compared to the prior art, the voltage Vosc variation range in this embodiment is larger, and correspondingly, the swing amplitude of the multiple clock signals with different phases output by the ring oscillator 220 is also larger.

[0051] Furthermore, the dimensions of transistor MN6 need to satisfy the following requirements: a sufficiently large current flows through it at higher operating frequencies of the voltage-controlled oscillator 200 to keep transistor MP2 in the saturation region; and a small current flows through it at lower operating frequencies of the voltage-controlled oscillator 200 to raise the voltage Vosc sufficiently so that the swing of the multiple clock signals with different phases output by the ring oscillator 200 meets the requirements of the subsequent level converter, even if the transistors in the subsequent level converter can operate in the saturation region. The voltage difference Vds1 between the drain and source terminals of transistor MN6 varies with the voltage Vosc depending on its dimensions.

[0052] Figure 6 A circuit diagram of a voltage-controlled oscillator according to a second embodiment of the present invention is shown.

[0053] See Figure 6In the second embodiment of this utility model, the structure of the ring oscillator 220 is the same as that in the first embodiment, and will not be described again here. The voltage-to-current conversion circuit 210 includes transistors MP1 and MN1 connected sequentially between the power supply voltage VDD and the ground terminal, a transistor MP5 connected between the power supply voltage VDD and the voltage adjustment circuit 230, and a transistor MP2 connected between the power supply voltage VDD and the first voltage terminal of the ring oscillator 220. The control terminal of transistor MN1 receives the control voltage Vctrl, and the control terminal of transistor MP1 is connected to its first terminal, the control terminal of transistor MP5, and the control terminal of transistor MP2. Transistor MN1 is used to convert the control voltage Vctrl into a bias current linearly related to it, and transistor MP2 mirrors this bias current to obtain the control current Ic. Resistor R2 can improve the linearity of the bias current following the change of the control voltage Vctrl. In other examples of this application, the voltage-to-current conversion circuit 210 may not include resistor R2; in this case, the second terminal of transistor MN1 is directly grounded.

[0054] The voltage adjustment circuit 230 is connected between the second voltage terminal and the ground terminal of the ring oscillator 220, and it is implemented using a current mirror. The voltage adjustment circuit 230 includes transistors MN7 and MN8. Transistor MN7 is connected between the second voltage terminal and the ground terminal of the ring oscillator 220, and transistor MN8 is connected between the second terminal of transistor MP5 and the ground terminal. The control terminal of transistor MN8 is connected to its first terminal and the control terminal of transistor MN7.

[0055] In this embodiment, the voltage adjustment circuit 230 increases the voltage Vosc by Vds2 compared to the prior art, where Vds2 represents the voltage difference between the drain and source terminals of transistor MN7. When the operating frequency of the voltage-controlled oscillator 200 is low, the voltage value of Vosc is low, and the control current Ic is also small, resulting in a larger voltage difference Vds2 between the drain and source terminals of transistor MN7, thus increasing the voltage Vosc by a larger margin compared to the prior art. When the operating frequency of the voltage-controlled oscillator 200 is high, the voltage value of Vosc is high, and the control current Ic is also large. At this time, the voltage difference Vds2 between the drain and source terminals of transistor MN7 is small, and the increase in voltage Vosc by a smaller margin compared to the prior art. Therefore, compared to the prior art, the voltage Vosc variation range in this embodiment is larger, and correspondingly, the swing amplitude of the multiple clock signals with different phases output by the ring oscillator 220 is also larger.

[0056] Figure 7 A circuit diagram of a voltage-controlled oscillator according to a third embodiment of the present invention is shown.

[0057] See Figure 7The structure of the voltage-to-current conversion circuit 210 in the third embodiment of this utility model is the same as that in the first embodiment, and will not be described again here. It is understood that the voltage-to-current conversion circuit 210 in the first and third embodiments of this application can also be implemented using any circuit of the prior art.

[0058] In this embodiment, the ring oscillator 220 includes multiple first delay units, and the voltage adjustment circuit 230 includes at least one second delay unit. The multiple first delay units and at least one second delay unit are cascaded, and the first and second delay units have identical structures. In the multiple delay units (including multiple first delay units and at least one second delay unit), the positive input terminal of the subsequent delay unit is connected to the negative output terminal of the preceding delay unit, and the negative input terminal of the subsequent delay unit is connected to the positive output terminal of the preceding delay unit. The positive input terminal of the first delay unit is connected to the positive output terminal of the last delay unit, and the negative input terminal of the first delay unit is connected to the negative output terminal of the last delay unit. Figure 7 In the example, the ring oscillator 220 includes four stages of first delay units 221_1-221_4, and the voltage adjustment circuit 230 includes four stages of second delay units 221_5-221_8.

[0059] In the third embodiment of this utility model, the number of second delay units in the voltage adjustment circuit 230 is related to the number of phases of the clock signal that the voltage-controlled oscillator 200 needs to output. Taking the requirement that the voltage-controlled oscillator 200 needs to output an N-phase clock signal as an example, if N is an even number, the number of second delay units in the voltage adjustment circuit 230 is N / 2; if N is an odd number, the number of second delay units in the voltage adjustment circuit 230 needs to be N.

[0060] In the third embodiment of this utility model, since the number of cascaded delay units has increased, a larger control current is required to increase the speed of each delay unit. Therefore, the voltage Vosc will increase accordingly, and the swing of the multiple clock signals with different phases output by the ring oscillator 220 will also increase accordingly.

[0061] In the above three embodiments, the increase in voltage Vosc will lead to an increase in the overall power consumption of voltage-controlled oscillator 200. In order to reduce the overall power consumption of voltage-controlled oscillator 220 when the operating frequency is high, this utility model also provides a new level converter.

[0062] Figure 8 A circuit diagram of a level converter according to an embodiment of the present invention is shown.

[0063] The voltage-controlled oscillator 200 of this application also includes multiple level shifters 222. The number of level shifters 222 is the same as the number of phases of the clock signal that the voltage-controlled oscillator 200 needs to output. Taking an eight-phase clock signal as an example, the voltage-controlled oscillator 200 needs eight level shifters 222 for voltage domain conversion. Each level shifter 222 is used to convert the voltage domain of one of the multiple clock signals of different phases output by the ring oscillator 220 from a first voltage domain to a second voltage domain. The first voltage domain is from voltage Vosc to ground voltage GND, and the second voltage domain is from power supply voltage VDD to ground voltage GND.

[0064] See Figure 8 The level converter 222 includes a first current branch 222a, a second current branch 222b, a pull-up circuit 222c, and an inverter INV.

[0065] The first current branch 222a is used to control the conduction and cutoff of its current path according to the clock signal CKO and the input signal INN. The second current branch 222b is used to control the conduction and cutoff of its current path according to the input signal INP. The input terminal of the inverter INV is connected to the second current branch 222b, and the output terminal provides the clock signal CKO. The pull-up circuit 222c is used to selectively pull up the voltage at the input terminal of the inverter INV according to the clock signal CKO, wherein the input signal INP is the clock signal that needs voltage domain conversion, and the input signal INN is the inverse of the input signal INP. The output terminal of the inverter INV serves as the output terminal of the level converter 222, providing the clock signal CKO, which is the final clock signal output by the voltage-controlled oscillator 200.

[0066] The first current branch 222a includes transistors MP3, MN2 and MN4 connected sequentially between the power supply voltage VDD and the ground terminal. The control terminal of transistor MN4 is connected to the output terminal of inverter INV. The control terminal of transistor MN2 receives the input signal INN. The control terminal of transistor MP3 is connected to its second terminal.

[0067] The second current branch 222b includes transistors MP4, MN3, and MN5 connected sequentially between the power supply voltage VDD and the ground terminal. The control terminal of transistor MP4 is connected to the control terminal of transistor MP3. The control terminal of transistor MN3 receives the input signal INP. The intermediate node between transistor MP4 and transistor MN3 is connected to the input terminal of inverter INV. The control terminal of transistor MN5 receives the control voltage PDN, which is used to control the level shifter to turn on and off.

[0068] Pull-up circuit 222c includes transistors MP6 and MP7 connected sequentially between the power supply voltage VDD and the intermediate node of transistors MP4 and MN3. The control terminal of transistor MP6 receives the bias voltage VB, and the control terminal of transistor MP7 is connected to the output terminal of inverter INV. Transistor MP6 acts as a current-limiting element and remains in the ON state during the operation of level converter 222. In other embodiments of this application, pull-up circuit 222c may also include only transistor MP7, in which case transistor MP7 is connected between the power supply voltage VDD and the intermediate node of transistors MP4 and MN3.

[0069] Specifically, when the input signal INP is high and the input signal INN is low, the clock signal CKO is high. At this time, transistor MP7 is off, transistor MN4 is on, the second current branch 222b works normally, and the current path of the first current branch 222a is turned off. When the input signal INP flips to low and the input signal INN flips to high, the current path of the second current branch 222b is turned off, the first current branch 222a is turned on first, and then the clock signal CKO flips to low, turning off the current path of the first current branch 222a. Transistor MP7 is turned on to provide a pull-up channel to prevent leakage from causing incorrect flips. In this way, during the time when the input signal INN is high, only the pull-up circuit 222c has current flowing through it, and the power consumption of the pull-up circuit 222c is much less than the power consumption of the first current branch 222a. Therefore, the overall power consumption of the voltage-controlled oscillator 200 can be reduced.

[0070] Furthermore, when the operating frequency of the voltage-controlled oscillator 200 is low and the voltage Vosc is small, the pull-down capability of transistor MN3 needs to be stronger than the pull-up capability of transistors MP6 and MP7; otherwise, the output of inverter INV cannot achieve level switching.

[0071] It is understood that in this application, the operating frequency of the voltage-controlled oscillator 200 is relative, and the range of the operating frequency of the voltage-controlled oscillator 200 is different, and the division of the operating frequency is also different.

[0072] The voltage-controlled oscillator 200 provided in this embodiment adjusts the voltage Vosc at the first voltage terminal of the ring oscillator 220 according to the operating frequency of the voltage-controlled oscillator 200. This results in a larger swing amplitude of the multiple clock signals with different phases output by the ring oscillator 220 compared to the prior art ring oscillators, reducing the mismatch when each clock signal passes through a level converter, thereby reducing the mismatch between the multiple clock signals with different phases output by the voltage-controlled oscillator 200. Furthermore, when the clock signal requiring voltage domain conversion is low, each level converter 222 shuts off the current path of its first current branch 222a, reducing the power consumption of the level converter 222 and thus reducing the overall power consumption of the voltage-controlled oscillator 200.

[0073] Furthermore, this application also provides a phase-locked loop circuit, comprising: a frequency and phase detector for receiving a reference clock signal and a feedback clock signal, and generating a pulse control signal based on a phase comparison of the reference clock signal and the feedback clock signal; a charge pump circuit for outputting a corresponding voltage signal according to the pulse control signal; a loop filter for generating a corresponding control voltage according to the output voltage of the charge pump; a voltage-controlled oscillator 200 as described above; and a frequency divider for performing frequency division processing on the clock signal output by the voltage-controlled oscillator 200 to generate the feedback clock signal.

[0074] Furthermore, this application also provides a driver chip, including the phase-locked loop circuit described above.

[0075] Furthermore, this application also provides a display device including the driver chip described above.

[0076] The embodiments of this utility model described above are examples of specific examples, and do not exhaustively describe all details, nor do they limit the utility model to only specific embodiments. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this utility model, thereby enabling those skilled in the art to make good use of this utility model and its modifications. The scope of protection of this utility model should be determined by the scope defined by the claims of this utility model and their equivalents.

Claims

1. A voltage controlled oscillator characterized by, include: A voltage-to-current conversion circuit is used to convert a first control voltage into a control current. A ring oscillator has a first voltage terminal and a second voltage terminal, the first voltage terminal being connected to the output terminal of the control current, and the ring oscillator is used to generate multiple clock signals with different phases based on the control current; A voltage adjustment circuit, connected to the second voltage terminal of the ring oscillator, is used to adjust the voltage of the first voltage terminal according to the operating frequency of the voltage-controlled oscillator.

2. The voltage controlled oscillator of claim 1, wherein, The voltage adjustment circuit includes: The first transistor has a first terminal connected to the second voltage terminal, a second terminal connected to the ground terminal, and a control terminal connected to the first voltage terminal.

3. The voltage controlled oscillator of claim 1, wherein, The voltage adjustment circuit includes: The second transistor has its first terminal connected to the second voltage terminal and its second terminal connected to the ground terminal. The third transistor has its first terminal connected to the voltage-to-current conversion circuit, its second terminal connected to the ground terminal, and its control terminal connected to its first terminal and the control terminal of the second transistor.

4. The voltage controlled oscillator of claim 1, wherein, The ring oscillator includes: Multiple first delay units are cascaded in sequence. Each first delay unit has a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. The clock signals output from the positive and negative output terminals of each first delay unit have different phases. In this configuration, the positive input terminal of the next stage first delay unit is connected to the negative output terminal of the previous stage first delay unit, the negative input terminal of the next stage first delay unit is connected to the positive output terminal of the previous stage first delay unit, the positive input terminal of the first stage first delay unit is connected to the positive output terminal of the last stage first delay unit, and the negative input terminal of the first stage first delay unit is connected to the negative output terminal of the last stage first delay unit.

5. The voltage controlled oscillator of claim 4, wherein, The voltage adjustment circuit includes: At least one second delay unit is cascaded sequentially with the plurality of first delay units, and the structure of the second delay unit is the same as that of the first delay unit. In this configuration, the positive input terminal of the next stage delay unit is connected to the negative output terminal of the previous stage delay unit, the negative input terminal of the next stage delay unit is connected to the positive output terminal of the previous stage delay unit, the positive input terminal of the first stage delay unit is connected to the positive output terminal of the last stage delay unit, and the negative input terminal of the first stage delay unit is connected to the negative output terminal of the last stage delay unit.

6. The voltage-controlled oscillator according to claim 3, characterized in that, The voltage-to-current conversion circuit includes: The fourth transistor, the fifth transistor, and the first resistor are connected sequentially between the power supply voltage and the ground terminal. The control terminal of the fourth transistor is connected to its second terminal, and the control terminal of the fifth transistor receives the first control voltage. The sixth transistor has its first terminal connected to the power supply voltage, its second terminal connected to the first terminal of the third transistor, and its control terminal connected to the control terminal of the fourth transistor. The seventh transistor has a first terminal connected to the power supply voltage, a second terminal connected to the first voltage terminal, and a control terminal connected to the control terminal of the fourth transistor.

7. The voltage-controlled oscillator according to claim 1, characterized in that, It also includes multiple level shifters, each level shifter being used to convert the voltage domain of one of the multiple clock signals of different phases from a first voltage domain to a second voltage domain, each level shifter including: The first current branch is used to control the conduction and cutoff of its current path according to the clock signal output by the level converter and the first input signal. The second current branch is used to control the conduction and cutoff of its current path according to the second input signal; The inverter has its input connected to the second current branch and its output serving as the output of the level converter, providing a clock signal after the voltage domain conversion is completed. A pull-up circuit is used to selectively pull up the input voltage of the inverter according to the clock signal output by the level converter. The second input signal is a clock signal that needs to be converted to voltage domain, and the first input signal is out of phase with the second input signal.

8. The voltage-controlled oscillator according to claim 7, characterized in that, The first current branch includes: The eighth, ninth, and tenth transistors are connected sequentially between the power supply voltage and the ground voltage. The control terminal of the eighth transistor is connected to its second terminal, the control terminal of the ninth transistor receives the first input signal, and the control terminal of the tenth transistor is connected to the output terminal of the inverter. The second current branch includes: The eleventh, twelfth, and thirteenth transistors are connected sequentially between the power supply voltage and the ground voltage. The control terminal of the eleventh transistor is connected to the control terminal of the eighth transistor. The control terminal of the twelfth transistor receives the second input signal. The control terminal of the thirteenth transistor receives the second control voltage. The intermediate node between the eleventh and twelfth transistors is connected to the input terminal of the inverter. The pull-up circuit includes: The fourteenth and fifteenth transistors are connected sequentially between the power supply voltage and the intermediate node between the eleventh and twelfth transistors. The control terminal of the fifteenth transistor is connected to the output terminal of the inverter, and the control terminal of the fourteenth transistor receives the bias voltage. The fourteenth transistor is always in the on state during the operation of the level converter.

9. A phase-locked loop circuit, characterized in that, include: A frequency and phase detector is used to receive a reference clock signal and a feedback clock signal, and generate a pulse control signal based on the phase comparison between the reference clock signal and the feedback clock signal. A charge pump circuit is used to output a corresponding voltage signal according to the pulse control signal; A loop filter is used to generate a corresponding control voltage based on the output voltage of the charge pump circuit. The voltage-controlled oscillator as described in any one of claims 1-8; as well as The frequency divider is used to divide the clock signal output by the voltage-controlled oscillator to generate the feedback clock signal.

10. A driver chip, characterized in that, Includes the phase-locked loop circuit as described in claim 9.

11. A display device, characterized in that, Includes the driver chip as described in claim 10.

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