FPGA-based multi-channel synchronous acquisition device
By employing digital signal delay alignment and analog signal decimation filtering in the FPGA, the problem of excessive resource consumption in multi-channel data acquisition is solved, synchronous acquisition of digital and analog signals is achieved, FPGA resource usage is reduced, and the scope of application is expanded.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANGHAI MOONS AUTOMATION CONTROL CO LTD
- Filing Date
- 2025-07-09
- Publication Date
- 2026-06-19
AI Technical Summary
Existing technologies for multi-channel data acquisition suffer from excessive resource consumption in the synchronous acquisition of digital and analog signals, especially when it is difficult to achieve synchronization characteristics across channels with different sampling rates.
A multi-channel synchronous acquisition device based on FPGA is adopted. By utilizing the block random access memory in the digital signal acquisition module and the DSP unit in the analog signal acquisition module, a first-level multi-channel decimator and a second-level multi-channel decimator are used in combination with different processing methods to achieve digital signal delay alignment and analog signal decimation filtering, thereby reducing the use of FPGA resources.
It achieves synchronous acquisition of digital and analog signals in multiple channels with different sampling rates, reduces the occupation of FPGA resources, expands the scope of application, and ensures the synchronization characteristics of all channels.
Smart Images
Figure CN224385500U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a multi-channel data acquisition device, and more particularly to a multi-channel synchronous acquisition device based on FPGA. Background Technology
[0002] The condition monitoring acquisition device collects analog and digital signal pulses, such as the second pulse of rotation speed. There may be many channels on site, and each channel achieves a different sampling rate according to the requirements of the measurement point.
[0003] Typically, sampled inputs are divided into digital signals and analog signals. Digital signals are equivalent to 1 bit, and analog signals are equivalent to N bits. As a typical implementation example, to implement an 8-channel analog input, the ADC uses a 24-bit and 8-channel ADC, such as an Sigma-Aldrich architecture ADC. The Sigma-Aldrich architecture ADC causes its output to have a delay, which is generally calculated based on the ADC's original sampling rate Fs: 1 / FS = (sample); then delayADC = N (sample).
[0004] The ADC uses the same sampling rate for all 8 channels. This example is not limited to 8 channels; a 100K sampling rate is used as an implementation example. For analog signals, the ADC output is FS = 100K, with a delay of N (samples). For digital signals, the output sampling clock is FD. As an implementation example, it is implemented as FS * 256, which is 25.6MHz.
[0005] To align digital and analog signals, the digital signal needs to be delayed by N (samples). In the example, the digital signal sampling rate is 256*Fs, which means the digital signal needs to be delayed by 256*N clk, where CLK = 25.6M.
[0006] Existing technologies typically store 256*N bits of information sequentially into a FIFO. Digital input is equivalent to 1 bit of information, and it is counted using CLK. When the count reaches 256*N, it is output sequentially from the FIFO. The drawback of the existing solution is that 1 bit of information is generally stored as discrete registers in an FPGA. Considering that 256*N is relatively large, it will consume a lot of resources. Utility Model Content
[0007] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a multi-channel synchronous acquisition device based on FPGA.
[0008] The objective of this utility model can be achieved through the following technical solutions:
[0009] According to one aspect of the present invention, a multi-channel synchronous acquisition device based on FPGA is provided, comprising a digital signal acquisition module and an analog signal acquisition module. The digital signal acquisition module includes a digital signal input terminal, a digital signal delay unit, and a digital signal output terminal connected in sequence. The analog signal acquisition module includes an analog signal input terminal, a first-level multi-channel decimator, a second-level multi-channel decimator, a selector, and an analog signal output terminal. The analog signal input terminal, the first-level multi-channel decimator, the selector, and the analog signal output terminal are connected in sequence, and the first-level multi-channel decimator, the second-level multi-channel decimator, and the selector are connected in sequence.
[0010] The digital signal delay unit uses the block random access memory in the FPGA, and both the first-level multi-channel decimator and the second-level multi-channel decimator use the DSP unit in the FPGA.
[0011] As a preferred technical solution, the primary multi-channel extractor and the secondary multi-channel extractor are multi-channel extractors with the same structure.
[0012] As a preferred technical solution, the multi-channel extractor includes a data buffer unit for each channel, a coefficient buffer unit for each channel, an arbitration unit, a multiply-accumulator unit, and an extraction result output unit. The input terminal of the arbitration unit is connected to the data buffer unit and the coefficient buffer unit for each channel, respectively. The output terminal of the arbitration unit is connected to the input terminal of the multiply-accumulator unit, and the output terminal of the multiply-accumulator unit is connected to the extraction result output unit.
[0013] As a preferred technical solution, the multi-channel extractor adopts a four-channel extractor, with each of the four channels sharing a single multiply-accumulator unit.
[0014] As a preferred technical solution, the channel data buffer unit is provided with four units, and the channel coefficient buffer unit is provided with four units, with each unit corresponding to the other.
[0015] As a preferred technical solution, each of the channel data buffer units is connected to the analog signal input terminal through a buffer write control unit.
[0016] As a preferred technical solution, the arbitration unit is a cyclic arbitrator, which buffers the requests from each channel.
[0017] As a preferred technical solution, the analog signal acquisition module has two modules, for a total of eight channels.
[0018] As a preferred technical solution, the digital signal acquisition module has two modules, with a total of two channels.
[0019] As a preferred technical solution, the coefficients of both the primary multichannel extractor and the secondary multichannel extractor are even numbers.
[0020] Compared with the prior art, the present invention has the following advantages:
[0021] 1) This utility model realizes synchronous acquisition and filtering of digital and analog signals in the case of multiple channels. Different processing methods are used for digital and analog signals. The digital signal adopts the delay alignment method, and the analog signal adopts the decimation filtering method. When the digital signal and the analog signal each channel adopt different sampling rate configurations, the synchronization characteristics of all channels of digital and analog signals can still be guaranteed.
[0022] 2) Each channel of this utility model can use an independent sampling rate and continuously process all channel data. Multi-level extraction can support the ratio coefficient from the highest to the lowest sampling rate, thus making the scope of application of this utility model wider.
[0023] 3) This utility model reduces the resource usage of FPGA by reusing DSP units;
[0024] 4) This utility model uses edge-time recording for digital signals and outputs them with analog signal delay alignment, thereby reducing FPGA resource usage. Attached Figure Description
[0025] Figure 1 This is a schematic diagram of the structure of this utility model;
[0026] Figure 2 This is a schematic diagram of the digital signal acquisition module of this utility model;
[0027] Figure 3 This is a schematic diagram of the analog signal acquisition module of this utility model;
[0028] Figure 4 This is a schematic diagram of the four-channel extractor of this utility model;
[0029] Figure 5 This is a schematic diagram of the extraction data of the first-stage multi-channel extractor and the second-stage multi-channel extractor of this utility model;
[0030] Figure 6 This is a schematic diagram of the analog signal output terminal of this utility model. Detailed Implementation
[0031] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of the present utility model. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present utility model.
[0032] like Figure 1As shown, the present invention relates to a multi-channel synchronous acquisition device based on FPGA, comprising a digital signal acquisition module 1 and an analog signal acquisition module 2. The digital signal acquisition module 1 includes a digital signal input terminal 11, a digital signal delay unit 12, and a digital signal output terminal 13 connected in sequence. The analog signal acquisition module 2 includes an analog signal input terminal 21, a first-level multi-channel decimator 22, a second-level multi-channel decimator 23, a selector 24, and an analog signal output terminal 25. The analog signal input terminal 21, the first-level multi-channel decimator 22, the selector 24, and the analog signal output terminal 25 are connected in sequence, and the first-level multi-channel decimator 22, the second-level multi-channel decimator 23, and the selector 24 are connected in sequence.
[0033] The digital signal delay unit 12 uses a block random access memory in the FPGA, and the first-level multi-channel decimator 22 and the second-level multi-channel decimator 23 both use DSP units in the FPGA; the delay time of the digital signal delay unit is configured to be the same as the decimation time of the multi-channel decimator, so as to synchronously acquire digital signals and analog signals.
[0034] This invention enables synchronous acquisition and filtering of digital and analog signals across multiple channels. It employs different processing methods for digital and analog signals, using a delay-aligned approach for digital signals and a decimation-filtered approach for analog signals. Even when different sampling rates are configured for each channel of digital and analog signals, the synchronization characteristics of all channels of digital and analog signals can still be guaranteed.
[0035] This embodiment uses 8 analog channels and 2 digital channels as an example for illustration.
[0036] This invention takes into account the sparsity of actual digital input pulses, such as rotational speed pulses, which are typically less than 1 kHz in frequency. For digital signals, it is only necessary to record the times of the rising and falling edges.
[0037] like Figure 2 As shown, the digital signal delay unit 12 of this utility model is specifically as follows: the left side is a multi-bit FIFO, such as 32-bit. The high 31 bits of t1 are used as the count value, and the low bits are used as rising or falling edge markers. If a rising edge or falling edge event occurs, t(n) is entered into the FIFO. The monitor checks the empty flag of the FIFO. If it is not empty, it reads out 32 bits, uses the high 32 bits as t, and then compares whether the counter T = t + (256 * N) is true. If it is true, the rising or falling edge of the signal is output. Such a FIFO can be easily implemented using FPGA blockram blocks, which saves FPGA resources. The depth of the FIFO can be determined according to the sparsity of the signal. Generally, 128 bits can meet the frequency of a 1K digital signal.
[0038] like Figure 3 As shown, the analog signal acquisition module of this utility model aims to achieve different sampling rates for 8 channels of analog signals. It performs decimation on the ADC with the original sampling rate of 100K. For example, to achieve a sampling frequency of 10K, a 10:1 decimation filter (FIR) can be used. Generally, the order of this FIR is around several hundred. As a convenient example, this utility model can achieve a filter with a maximum coefficient of 1000. This coefficient can achieve a decimation of approximately 20:1 or less. Considering that the actual sampling rate may be lower, this utility model uses a two-stage structure to perform multiple decimations to achieve a higher decimation factor.
[0039] The device has 8 channels of analog input, using 24-bit data and 24-bit filter coefficients as the multiply-accumulate unit for FIR. This invention designs a 24-bit * 24-bit accumulator unit that accumulates to 56 bits. In general, the DSP unit in an FPGA is 18-bit * 18-bit. This invention uses 4 FPGA DSP units to implement a 24-bit * 24-bit multiply-accumulate unit.
[0040] As a practical example of a high-bit multiply-accumulate (MAC), the MAC unit of this invention operates at 100MHz.
[0041] Given the scarcity of FPGA DSP resources, if each channel is equipped with two independent MAC units, 8*2*4=64 18*18 DSP units are needed. Considering the total computing power required, this invention adopts a method where every 4 channels share one MAC unit, thus requiring a total of 4 MAC units, or 16 18*18 DSP units.
[0042] The first and second stages of the 4-channel extractor use the same design. Figure 3 Some connections have been omitted; only channel 1 and channel 8 are connected.
[0043] The purpose of using a two-stage filter is mainly for feasibility considerations: to achieve a decimation ratio of, for example, 100:1, the coefficient order of a single-stage decimation FIR filter is very high, possibly reaching tens of thousands of orders. The storage of a large number of coefficients would put pressure on resources. With a two-stage filter, the coefficient order can be controlled to below 1,000 orders, so the maximum number of coefficients in both stages is only 2,000, reducing the pressure on coefficient storage resources.
[0044] The 8-channel output also uses the same design, and the output channels can be selected from either the first stage or the second stage.
[0045] The channel extractor and output device will be described in detail below:
[0046] like Figure 4The diagram shows a block diagram of a 4-channel decimator, which includes a four-channel data buffer unit, a four-channel coefficient buffer unit, an arbitration unit, a multiply-accumulate unit, and a decimation result output unit. The input of the arbitration unit is connected to the four-channel data buffer unit and the four-channel coefficient buffer unit, respectively. The output of the arbitration unit is connected to the input of the multiply-accumulate unit, and the output of the multiply-accumulate unit is connected to the decimation result output unit.
[0047] like Figure 5 As shown, if the channel output is selected from the first stage, for example, the coefficient length of the selected unit is recorded as M1. If the selected output stage is the second stage, the coefficient length of the selected unit is recorded as M2, and the decimation ratio of the selected second stage is D1.
[0048] As can be seen, the first-level extraction affects M1 sampling points before sampling point D, meaning these points participate in the filtering calculation;
[0049] The second-level extraction affects a total of M2*D1 before and after. Record M1 or M2*D1 as L, select the largest influence range Lmax among the 8 channels, and then the D of a sampling point on the original data axis must satisfy D>(Lmax / 2).
[0050] By selecting an appropriate D, the (D)th sampling point of the original ADC output was determined as the output starting point of the scheme.
[0051] To achieve the mapping of the first data output of the first stage to the original data at time D...
[0052] The first calculation needs to begin at time (D+(M1 / 2)).
[0053] Then, the second calculation begins at time (D+(M1 / 2))+D1, where D1 is the sampling rate of the selected first level. Then, the third calculation begins at time (D+(M1 / 2))+2*D1.
[0054] ...and so on.
[0055] The Nth calculation begins at time (D+(M1 / 2))+(N-1)*D1.
[0056] Figure 4 The block diagram needs to control the multiply-accumulator unit to complete the calculation.
[0057] X(N)*C0+X(N-1)*C1+....+X(N-M1)*C(M1)
[0058] Where X is the data buffer in the block diagram; C is the coefficient buffer; and the parentheses contain the corresponding address index. According to the FIR filter schematic, for example, to achieve a 2:1 decimation; assuming the sampling frequency is fs, the actual cutoff frequency is fc, and the normalized cutoff frequency is fcm, fcm = fc / (fs / 2); the channel frequency fpm = fp / (fs / 2), the FIR filter composed of coefficients C0...C(M1) needs to satisfy the normalized frequency fpm = 0.4 and fcm = 0.5; after the filter satisfies the above passband and cutoff frequencies, the sampling rate of the original data can be directly reduced from fs to fs / 2 without losing any effective information or causing aliasing.
[0059] The above describes the first level scenario. If the second level is not selected, the same calculation method should be used.
[0060] If the second level is selected, the feed of the second level needs to be considered, so the feed timing will be advanced. If the second level is selected, the first point of the second level also needs to correspond to the original data axis time D, so the feed timing will be advanced (M2*D1 / 2).
[0061] That is, the first feed calculation for the lower level begins at time (D+(M1 / 2))-(M2*D1) / 2.
[0062] Note that M2 and M1 must be even numbers to ensure that the feed time and the output time coincide on the discrete time axis extracted by D1.
[0063] The arbitration unit uses the right to use the arbitration unit according to the feed time and output time. In order to avoid all channels initiating req congestion at a certain time, the arbitration unit uses a cyclic arbitrator and buffers the req. Each channel has 8 levels of req buffer, which means that arbitration is initiated again before the req arbitration is completed.
[0064] like Figure 6 As shown, the analog signal output terminal of this utility model is specifically as follows:
[0065] For the analog channel, the first output data is at time D on the original data axis. To align the output time D+X, X must satisfy Lmax / 2. Select an appropriate time X to output the signal data.
[0066] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this utility model, and these modifications or substitutions should all be covered within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.
Claims
1. A multi-channel synchronous acquisition device based on FPGA, characterized in that, The system includes a digital signal acquisition module and an analog signal acquisition module. The digital signal acquisition module includes a digital signal input terminal, a digital signal delay unit, and a digital signal output terminal connected in sequence. The analog signal acquisition module includes an analog signal input terminal, a first-level multi-channel decimator, a second-level multi-channel decimator, a selector, and an analog signal output terminal. The analog signal input terminal, the first-level multi-channel decimator, the selector, and the analog signal output terminal are connected in sequence. The first-level multi-channel decimator, the second-level multi-channel decimator, and the selector are connected in sequence. The digital signal delay unit uses the block random access memory in the FPGA, and both the first-level multi-channel decimator and the second-level multi-channel decimator use the DSP unit in the FPGA.
2. The FPGA-based multi-channel synchronous acquisition device according to claim 1, characterized in that, The primary multichannel extractor and the secondary multichannel extractor are multichannel extractors with the same structure.
3. The FPGA-based multi-channel synchronous acquisition device according to claim 1, characterized in that, The multi-channel extractor includes a data buffer unit for each channel, a coefficient buffer unit for each channel, an arbitration unit, a multiply-accumulator unit, and an extraction result output unit. The input of the arbitration unit is connected to the data buffer unit and the coefficient buffer unit for each channel, respectively. The output of the arbitration unit is connected to the input of the multiply-accumulator unit, and the output of the multiply-accumulator unit is connected to the extraction result output unit.
4. The FPGA-based multi-channel synchronous acquisition device according to claim 3, characterized in that, The multi-channel extractor is a four-channel extractor, with each of the four channels sharing a single multiply-accumulator unit.
5. The FPGA-based multi-channel synchronous acquisition device according to claim 4, characterized in that, There are four channel data buffer units and four channel coefficient buffer units, which correspond one-to-one.
6. The FPGA-based multi-channel synchronous acquisition device according to claim 4, characterized in that, Each of the channel data buffer units is connected to the analog signal input terminal through a buffer write control unit.
7. The FPGA-based multi-channel synchronous acquisition device according to claim 4, characterized in that, The arbitration unit is a cyclic arbitrator that buffers requests from each channel.
8. The FPGA-based multi-channel synchronous acquisition device according to claim 1, characterized in that, The analog signal acquisition module has two modules, for a total of eight channels.
9. The FPGA-based multi-channel synchronous acquisition device according to claim 1, characterized in that, The digital signal acquisition module has two modules, with a total of two channels.
10. The FPGA-based multi-channel synchronous acquisition device according to claim 1, characterized in that, The coefficients of both the first-level multichannel extractor and the second-level multichannel extractor are even numbers.