A programmable frequency divider with dynamically adjustable frequency division ratio
By designing a programmable frequency divider with dynamically adjustable division ratio, and utilizing a combination of multi-division circuits and buffer circuits, the problem of the traditional frequency divider's single function is solved, enabling outputs with multiple division ratios, suitable for frequency synthesizers, clock management units, and communication systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HUNAN RAILWAY PROFESSIONAL TECH COLLEGE
- Filing Date
- 2025-06-27
- Publication Date
- 2026-06-23
AI Technical Summary
Traditional frequency dividers have a single function and a fixed division ratio, which cannot meet the needs of modern electronic systems for flexibility and programmability, especially in situations where dynamic adjustment of the division ratio is required.
A programmable frequency divider including multiple frequency divider circuits and buffer circuits was designed. By combining inverters, flip-flops and logic gates, dynamic adjustment of various frequency division ratios can be achieved. A dual-counter differential structure, clock phase separation technology and equal detection mechanism are adopted to eliminate accumulated errors and race conditions, ensuring high-quality clock signal distribution.
It achieves real-time programmability, can output multiple frequency division ratios, meets the various clock frequency requirements of complex digital systems, and can be applied to frequency synthesizers, clock management units, and communication systems.
Smart Images
Figure CN224401525U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electronic technology, specifically to a programmable frequency divider with dynamically adjustable division ratio. Background Technology
[0002] With the rapid development of modern electronic technology, frequency dividers, as an important electronic device, play an increasingly important role in electronic systems. The main function of a frequency divider is to reduce the frequency of the input signal to a lower frequency, enabling signal processing, conversion, and control. Especially in mobile communications, digital television, radar systems, scientific instruments, and various digital circuits, the demand for frequency dividers is growing rapidly.
[0003] However, traditional frequency dividers are mostly single-function and have a fixed division ratio, which cannot meet the requirements of modern electronic systems for the flexibility and programmability of frequency dividers. Especially in situations where the division ratio needs to be dynamically adjusted, traditional frequency dividers often struggle to adapt. Summary of the Invention
[0004] To overcome the aforementioned technical deficiencies, this utility model provides a programmable frequency divider with dynamically adjustable division ratio. To achieve the above objective, this utility model is implemented according to the following technical solution:
[0005] This utility model provides a programmable frequency divider with dynamically adjustable division ratio, comprising: a first frequency divider circuit, a second frequency divider circuit, a third frequency divider circuit, a fourth frequency divider circuit, and a buffer circuit, wherein the first frequency divider circuit, the second frequency divider circuit, the third frequency divider circuit, and the fourth frequency divider circuit are all connected to the input terminal of the buffer circuit.
[0006] Optionally, the first frequency divider circuit includes a first inverter, a second inverter, a third inverter, and a first T flip-flop connected in sequence, with the input terminal of the first inverter connected to the preset control terminal.
[0007] Optionally, the second frequency divider circuit includes a fourth inverter, a first D flip-flop, a fifth inverter, and a second T flip-flop connected in sequence, wherein the input terminal of the fourth inverter is also connected to the output terminal of the first D flip-flop.
[0008] Optionally, the third frequency divider circuit includes a first XOR gate, a second D flip-flop, a sixth inverter, and a third T flip-flop connected in sequence. The first input terminal of the first XOR gate is also connected to the output terminal of the second D flip-flop, and the second output terminal of the first XOR gate is also connected to the input terminal of the fourth inverter.
[0009] Optionally, the fourth frequency divider circuit includes a first NAND gate, a seventh inverter, a second XOR gate, a third D flip-flop, an eighth inverter, and a fourth T flip-flop connected in sequence; the first input terminal of the first NAND gate is also connected to the first input terminal of the first XOR gate; the second input terminal of the first NAND gate is also connected to the input terminal of the fourth inverter, and the input terminal of the second XOR gate is also connected to the output terminal of the third D flip-flop.
[0010] Optionally, the buffer circuit includes a ninth inverter and a first output buffer connected in sequence. The output terminals of the first T flip-flop, the second T flip-flop, the third T flip-flop, and the fourth T flip-flop are all connected to the input terminal of the ninth inverter. The output terminal of the ninth inverter is connected to the input terminal of the first output buffer, and the output terminal of the first output buffer is connected to the output signal terminal.
[0011] Optionally, the clock input terminals of the first D flip-flop, the second D flip-flop, and the third D flip-flop are all connected to the output terminal of the second inverter.
[0012] Optionally, the inverted output terminals of the first D flip-flop, the second D flip-flop, and the third D flip-flop are all connected to the power supply.
[0013] This utility model has the following beneficial effects:
[0014] This invention has real-time programmability and can output multiple different frequency division ratios simultaneously, meeting the needs of complex digital systems for multiple clock frequencies. It has broad application prospects in frequency synthesizers, clock management units, and communication systems.
[0015] In addition to the objectives, features, and advantages described above, this utility model has other objectives, features, and advantages. The present utility model will now be described in further detail with reference to the accompanying drawings. Attached Figure Description
[0016] The accompanying drawings, which form part of this utility model, are used to provide a further understanding of the utility model. The illustrative embodiments of the utility model and their descriptions are used to explain the utility model and do not constitute an undue limitation of the utility model. In the drawings:
[0017] Figure 1 This is a schematic diagram of the topology of a programmable frequency divider with dynamically adjustable division ratio provided in an embodiment of this utility model. Detailed Implementation
[0018] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention can be implemented in many different ways as defined and covered by the claims.
[0019] In order to solve the problems raised in the background art, such as Figure 1 As shown, this utility model provides a programmable frequency divider with dynamically adjustable division ratio, comprising:
[0020] The first frequency divider circuit, the second frequency divider circuit, the third frequency divider circuit, the fourth frequency divider circuit, and the buffer circuit are all connected to the input terminal of the buffer circuit.
[0021] The first frequency divider circuit includes a first inverter I1, a second inverter I2, a third inverter I3 and a first T flip-flop T0 connected in sequence. The input terminal of the first inverter I1 is connected to the preset control terminal RIN.
[0022] The second frequency divider circuit is connected in sequence to the fourth inverter I4, the first D flip-flop dff1, the fifth inverter I5, and the second T flip-flop T1. The input terminal of the fourth inverter I4 is also connected to the output terminal Q of the first D flip-flop dff1.
[0023] The third frequency divider circuit includes a first XOR gate X1, a second D flip-flop dff2, a sixth inverter I6, and a third T flip-flop T2 connected in sequence. The first input terminal of the first XOR gate X1 is also connected to the output terminal Q of the second D flip-flop dff2, and the second input terminal of the first XOR gate X1 is also connected to the input terminal of the fourth inverter I4.
[0024] The fourth frequency divider circuit includes a first NAND gate N1, a seventh inverter I7, a second XOR gate X2, a third D flip-flop dff3, an eighth inverter I8, and a fourth T flip-flop T3 connected in sequence; the first input terminal A of the first NAND gate N1 is also connected to the first input terminal of the first XOR gate X1; the second input terminal B of the first NAND gate N1 is also connected to the input terminal of the fourth inverter I4; and the input terminal of the second XOR gate X2 is also connected to the output terminal Q of the third D flip-flop dff3.
[0025] The buffer circuit includes a ninth inverter I9 and a first output buffer B1 connected in sequence. The outputs of the first T flip-flop T0, the second T flip-flop T1, the third T flip-flop T2, and the fourth T flip-flop T3 are all connected to the input of the ninth inverter I9. The output of the ninth inverter I9 is connected to the input of the first output buffer B1. The output of the first output buffer B1 is connected to the output signal terminal ROUT.
[0026] The clock inputs of the first D flip-flop dff1, the second D flip-flop dff2, and the third D flip-flop dff3 are all connected to the output of the second inverter I2.
[0027] The inverted output terminals of the first D flip-flop dff1, the second D flip-flop dff1, and the third D flip-flop dff1 are all connected to the power supply terminal VDD.
[0028] To facilitate a better understanding of the working principle of this utility model, its working process is explained as follows:
[0029] This circuit is mainly used to divide the input signal RIN by different ratios, and finally output the signal ROUT. The following is a detailed analysis of the circuit's working principle:
[0030] 1. Input Signals and Initial Processing
[0031] The input signal RIN serves as the starting signal for the entire circuit and is the foundation for all subsequent processing. When RIN = 1, the flip-flops and corresponding logic gates work together to achieve counting and frequency division functions. The input signal RIN first passes through the first inverter I1 and the second inverter I2 in sequence. The main function of the inverters is to invert the logic level of the input signal. After two inversions, although the logic level of the signal is formally restored to its original state, this process enhances the signal's driving capability, ensuring that the signal can be stably transmitted to subsequent circuit modules.
[0032] 2. Frequency divider module DFFAR
[0033] The circuit includes a first D flip-flop dff1, a second D flip-flop dff2, and a third D flip-flop dff3. These D flip-flops all have asynchronous reset (RN) and clock enable (SK) functions. The D flip-flops latch the value of the input D to the output Q on the rising edge of the clock signal.
[0034] dff1: Its output fd1 is transmitted to subsequent circuits after passing through the third inverter I3. The clock signal of dff1 comes from the RIN signal processed by the second inverter I2.
[0035] dff2: Its output fd2 passes through the fifth inverter I5 and is then connected to subsequent circuitry. The clock signal for dff2 is provided by the output fd1 of dff1.
[0036] dff3: Driven by the output fd2 of dff2. Simultaneously, the output fd2 of dff2 also drives the first NAND gate N1, the first XOR gate X1, and dff2 itself. The circuit achieves frequency division through cascading different flip-flops and logic gate control.
[0037] 3. Logic gate processing
[0038] The first NAND gate N1 receives fd2 and the inverted signal as input signals, and its output signal is used to control the reset (RN) of dff3 or other logic functions.
[0039] XOR gate I7: Performs an XOR operation on fd2 and the signal after inversion and equality processing, and the output signal is used to control the reset (RN) of dff3 or other logic.
[0040] 4. Frequency division output
[0041] 1 / 1 frequency division: The input signal fd1 is directly output through the transmission gate T0 and the inverter, that is, the output signal has the same frequency as the input signal.
[0042] 1 / 2 frequency division: dff2 is driven by the output fd1 of dff1, and the output fd2 of dff2 is output through an inverter and transmission gate T1 to achieve 1 / 2 frequency division.
[0043] 1 / 4 frequency division: The output fd2 of dff2 further drives the subsequent D flip-flops (such as dff3 through cascading, etc.). After two stages of flip-flops, the frequency is divided by 1 / 4. The output passes through the transmission gate T2 and the inverter I6.
[0044] 1 / 8 frequency division: 1 / 8 frequency division is achieved by cascading multiple flip-flops. The output signal fd8 is processed by relevant logic and then output through a transmission gate, etc.
[0045] 5. Final output ROUT
[0046] Multiple frequency-divided signals pass through transmission gates T0-T3 and logic gates such as inverters, and the final output signal ROUT is achieved through complex combinations of logic gates and transmission gates. Transmission gates T0-T3 are used to select different frequency-divided signals or to combine signals.
[0047] In summary, the dual-counter differential structure of this invention fundamentally eliminates the cumulative error problem that may exist in traditional counters. Secondly, the clock phase separation technology ensures that the two counters never change state simultaneously, effectively avoiding the race conditions common in digital circuits. Thirdly, the careful configuration of nine inverters guarantees high-quality clock signal distribution. Finally, the equality detection mechanism replaces the traditional overflow detection method, providing higher frequency division accuracy and lower output jitter. The entire circuit supports continuous frequency division ratio settings from 1 to 15, has real-time programmability, and can simultaneously output multiple different frequency division ratios, meeting the needs of complex digital systems for multiple clock frequencies. It has broad application prospects in frequency synthesizers, clock management units, and communication systems.
[0048] The above description is merely a preferred embodiment of this utility model and is not intended to limit the scope of this utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this utility model should be included within the protection scope of this utility model.
Claims
1. A dynamically adjustable divide ratio programmable frequency divider, characterized by, include: A first frequency divider circuit, a second frequency divider circuit, a third frequency divider circuit, a fourth frequency divider circuit, and a buffer circuit are all connected to the input terminal of the buffer circuit.
2. The programming frequency divider of claim 1, wherein, The first frequency divider circuit includes a first inverter, a second inverter, a third inverter, and a first T flip-flop connected in sequence, with the input terminal of the first inverter connected to the preset control terminal.
3. The programming frequency divider of claim 2, wherein, The second frequency divider circuit includes a fourth inverter, a first D flip-flop, a fifth inverter, and a second T flip-flop connected in sequence. The input terminal of the fourth inverter is also connected to the output terminal of the first D flip-flop.
4. The programming frequency divider of claim 3, wherein, The third frequency divider circuit includes a first XOR gate, a second D flip-flop, a sixth inverter, and a third T flip-flop connected in sequence. The first input terminal of the first XOR gate is also connected to the output terminal of the second D flip-flop, and the second input terminal of the first XOR gate is also connected to the input terminal of the fourth inverter.
5. The programming frequency divider of claim 4, wherein, The fourth frequency divider circuit includes a first NAND gate, a seventh inverter, a second XOR gate, a third D flip-flop, an eighth inverter, and a fourth T flip-flop connected in sequence; the first input terminal of the first NAND gate is also connected to the first input terminal of the first XOR gate; the second input terminal of the first NAND gate is also connected to the input terminal of the fourth inverter, and the input terminal of the second XOR gate is also connected to the output terminal of the third D flip-flop.
6. The programmable frequency divider according to claim 5, characterized in that, The buffer circuit includes a ninth inverter and a first output buffer connected in sequence. The output terminals of the first T flip-flop, the second T flip-flop, the third T flip-flop, and the fourth T flip-flop are all connected to the input terminal of the ninth inverter. The output terminal of the ninth inverter is connected to the input terminal of the first output buffer, and the output terminal of the first output buffer is connected to the output signal terminal.
7. The programmable frequency divider according to claim 6, characterized in that, The clock input terminals of the first D flip-flop, the second D flip-flop, and the third D flip-flop are all connected to the output terminal of the second inverter.
8. The programmable frequency divider according to claim 7, characterized in that, The inverted output terminals of the first D flip-flop, the second D flip-flop, and the third D flip-flop are all connected to the power supply.