An energy meter with a fault self-diagnosis function circuit

Abstract

This utility model discloses an energy meter with a fault self-diagnosis function circuit, comprising: a main control module, a metering module, a communication module group, a multi-level interlocking protection circuit, a diagnostic bus matrix, a fault tracing memory, and a power supply module. The main control module is connected to the metering module, the communication module group, the multi-level interlocking protection circuit, the diagnostic bus matrix, and the fault tracing memory. The diagnostic bus matrix is ​​connected to the metering module and the communication module group. The fault tracing memory is connected to the multi-level interlocking protection circuit. The power supply module is connected to the main control module, the metering module, the communication module group, the multi-level interlocking protection circuit, the diagnostic bus matrix, and the fault tracing memory. This technical solution enables comprehensive fault self-diagnosis of the energy meter, increasing the detection coverage to 12 key nodes, improving response speed, supporting fault prediction and reliable data storage, ensuring operational safety, and improving the level of intelligent power grid management.

Description

Technical Field

[0001] This utility model belongs to the field of electricity meter technology and relates to an electricity meter with a fault self-diagnosis function circuit. Background Technology

[0002] Currently, electricity meters, as core devices for power metering and data interaction, are widely used in smart grids. Traditional electricity meters have relatively simple circuit structures and weak fault detection capabilities, often relying on manual inspections and offline testing, which is insufficient to meet the real-time and intelligent operation requirements of the power grid. Although some electricity meters possess basic fault diagnosis functions, they can only detect a few key nodes, resulting in low fault detection coverage, slow response speed, and a lack of fault prediction and data protection mechanisms, making it impossible to promptly locate the root cause of faults and store effective fault information. With the expansion of the power grid and the increasing complexity of electricity demand, higher requirements are placed on the reliability, stability, and self-diagnostic capabilities of electricity meters. There is a need to develop an electricity meter circuit with high-coverage fault detection, rapid response, fault prediction, and reliable data storage functions to ensure the safe and stable operation of the power system, reduce operation and maintenance costs, and improve the management level of the smart grid. Summary of the Invention

[0003] To address the problems existing in the background technology, this utility model proposes an energy meter with a fault self-diagnosis function circuit.

[0004] To achieve the above objectives, the technical solution adopted by this utility model is as follows: an energy meter with a fault self-diagnosis function circuit, comprising: a main control module, a metering module, a communication module group, a multi-level interlocking protection circuit, a diagnostic bus matrix, a fault tracing memory, and a power supply module;

[0005] The main control module is connected to the metering module, the communication module group, the multi-level interlocking protection circuit, the diagnostic bus matrix, and the fault tracing memory. The diagnostic bus matrix is ​​connected to the metering module and the communication module group. The fault tracing memory is connected to the multi-level interlocking protection circuit. The power supply module is connected to the main control module, the metering module, the communication module group, the multi-level interlocking protection circuit, the diagnostic bus matrix, and the fault tracing memory.

[0006] The metering module includes: metering chip, capacitor C1, capacitor C2, isolator, Schmitt trigger, resistor R1, temperature sensor, resistor R2, current sampling circuit, resistor R4, resistor R3, and self-diagnostic current source.

[0007] Capacitors C1 and C2 are connected in parallel between the power supply pin and the ground pin of the metering chip. The voltage sampling terminal of the metering chip is connected to the SPI bus of the main control module through an isolator. The phase line fault detection terminal of the metering chip is connected to the diagnostic bus matrix through a Schmitt trigger. The calibration pulse output terminal of the metering chip is connected to the diagnostic bus matrix through resistor R1. The ADC terminal of the metering chip is connected to the temperature sensor. The output terminal of the temperature sensor is connected to the diagnostic bus matrix through a series resistor R2. The self-diagnostic current source is connected to the GPIO8 pin of the main control module. The output terminal of the self-diagnostic current source is connected to the current sampling circuit through series resistors R3 and R4.

[0008] The communication module group includes: carrier unit, capacitor C3, capacitor C4, peak detection circuit, capacitor C5, switching switch, analog switch, VSWR detector, 4G unit, capacitor C6, and capacitor C7;

[0009] Capacitors C3 and C4 are connected in parallel between the power supply pin and the ground pin of the carrier unit. The RXD / TXD terminal of the carrier unit is connected to the UART0 port of the main control module through a switching switch. The RSSI pin of the carrier unit is connected to the diagnostic bus matrix. The power line coupling terminal of the carrier unit is connected to the analog switch through capacitor C5. The ground pin of the analog switch is grounded. The control terminal of the analog switch is connected to the GPIO9 pin of the main control module. The carrier unit is connected to the diagnostic bus matrix through a peak detection circuit.

[0010] Capacitors C6 and C7 are connected in parallel between the power supply pin and the ground pin of the 4G unit. The RXD / TXD terminal of the 4G unit is connected to the UART0 port of the main control module through a switch. The SIM card presence signal of the 4G unit is connected to the diagnostic bus matrix. The antenna terminal of the 4G unit is connected to the VSWR detector. The output terminal of the VSWR detector is connected to the diagnostic bus matrix.

[0011] The diagnostic bus matrix includes: current transformer, comparator 1, multiplexer, ADC driver, and resistor R5;

[0012] The CH0 terminal of the multiplexer is connected to the temperature sensor of the metering module via resistor R2. The CH1 terminal of the multiplexer is connected to the current transformer via comparator 1. The CH2 terminal of the multiplexer is connected to the carrier unit via the peak detection circuit. The CH3 terminal of the multiplexer is connected to the SIM card presence signal of the 4G unit. The CH4 terminal of the multiplexer is connected to the output terminal of the VSWR detector. The address lines of the multiplexer are connected to the main control module. The output terminal of the multiplexer is connected to the ADC driver. The ADC driver is connected to the ADC0 pin of the main control module via resistor R5.

[0013] The multi-level interlocking protection circuit includes: pulse generator, diode D1, trip controller, diode D2, resistor R6, resistor R7, transistor Q1, resistor R8, current mirror sampling resistor, resistor R9, programmable reference source, voltage window comparator 2, capacitor C8, capacitor C9, fault tracing memory, latch, resistor R10, and watchdog chip.

[0014] The enable pin of the pulse generator is connected to GPIO4 of the main control module via diode D1. The enable pin of the trip controller is connected to GPIO4 of the main control module via diode D2. The trip controller is connected to one end of resistor R6, the other end of which is connected to the base of transistor Q1, one end of resistor R7, and the other end of resistor R7 is connected to ground. The collector of transistor Q1 is connected to the VCC power supply via resistor R8. The emitter of transistor Q1 is connected to one end of resistor R9 via the current mirror sampling resistor, and the other end of resistor R9 is connected to voltage window comparator 2. The programmable reference source is connected to I / O pin of the main control module. 2 The programmable reference source is connected to the reference terminal of voltage window comparator 2 via C. Capacitors C8 and C9 are connected in parallel between the power supply pin and the ground pin of voltage window comparator 2. Voltage window comparator 2 is connected to the latch via resistor R10. The watchdog chip is connected to the RESET pin of the latch. The output of the latch is connected to the WP write protection terminal of the fault tracing memory. The fault tracing memory is connected to the trip controller.

[0015] The fault tracing memory includes resistor R11, resistor R12, capacitor C10, and capacitor C11;

[0016] The fault tracing memory is a ferroelectric memory of model FM24C04. The SDA pin of the fault tracing memory is connected to the I pin of the main control module via resistor R11. 2 The C bus is connected, and the SCL pin of the fault tracing memory is connected to the I pin of the main control module via resistor R12. 2 The C bus is connected, and capacitors C10 and C11 are connected in parallel between the power supply pin and the ground pin of the fault tracing memory.

[0017] The storage area uses hexadecimal address encoding, with a total capacity of 256 bytes and addresses from 00H to FFH. It is divided into three functionally independent segments: timestamp segment, fault code segment, and environmental parameter segment. The timestamp segment address is 00-3F, the fault code segment is 40-7F, and the environmental parameter segment is 80-FF.

[0018] Compared with existing technologies, this utility model has the following advantages: This technical solution achieves multi-channel key signal polling detection through a diagnostic bus matrix, coupled with a fault injection mechanism, improving fault detection coverage and enabling comprehensive capture of anomalies in modules such as metering, communication, and power supply. The multi-level interlocking protection circuit, combined with a hardware comparator and a programmable reference source, achieves a diagnostic response speed of less than 10ms, triggering mandatory protection in critical situations such as voltage over-limits and abnormal tripping currents, ensuring electrical safety. The fault tracing memory is linked to the tripping action, ensuring that fault data is tamper-proof, and is stored in segments using timestamps, fault codes, and environmental parameters, facilitating accurate fault location. Simultaneously, it supports real-time self-checking of metering circuits and antenna status, enabling fault prediction and effectively improving the reliability of electricity meter operation and the level of intelligent grid management. Attached Figure Description

[0019] Figure 1 This is the main block diagram of the circuit structure of an energy meter with a fault self-diagnosis function according to this utility model.

[0020] Figure 2 This is the circuit connection diagram of the metering module of this utility model;

[0021] Figure 3 This is a circuit connection diagram of the communication module group of this utility model;

[0022] Figure 4 This is the connection diagram of the diagnostic bus matrix circuit of this utility model;

[0023] Figure 5 This is a connection diagram of the multi-level interlocking protection circuit of this utility model;

[0024] Figure 6 This is a connection diagram of the fault tracing memory of this utility model. Detailed Implementation

[0025] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0026] like Figures 1-6 As shown, the technical solution adopted by this utility model is as follows: an energy meter with a fault self-diagnosis function circuit, including: a main control module, a metering module, a communication module group, a multi-level interlocking protection circuit, a diagnostic bus matrix, a fault tracing memory, and a power supply module.

[0027] The main control module is connected to the metering module, the communication module group, the multi-level interlocking protection circuit, the diagnostic bus matrix, and the fault tracing memory. The diagnostic bus matrix is ​​connected to the metering module and the communication module group. The fault tracing memory is connected to the multi-level interlocking protection circuit. The power supply module is connected to the main control module, the metering module, the communication module group, the multi-level interlocking protection circuit, the diagnostic bus matrix, and the fault tracing memory.

[0028] The main control chip in the main control module is an STM32F407, which serves as the core of the circuit and is responsible for coordinating the operation of each module, data processing, and logic control.

[0029] The power supply module provides operating power to the electronic components of each module of the energy meter by outputting a stable 3.3V voltage and grounding: it is connected to the main control chip of the main control module; it powers the metering chip, self-diagnostic current source, isolator, Schmitt trigger, and temperature sensor of the metering module; it powers the carrier unit, 4G unit, VSWR detector, switching switch, and analog switch of the communication module group; and it powers the pulse generator, trip controller, transistor Q1, programmable reference source, voltage window comparator 2, fault tracing memory, latch, and watchdog chip in the multi-level interlocking protection circuit. The power supply pins of each module component are connected to the power supply module's VCC, and the grounding pin is connected to the power supply module's grounding terminal, thus constructing a complete and stable power supply system.

[0030] The metering module includes: metering chip, capacitor C1, capacitor C2, isolator, Schmitt trigger, resistor R1, temperature sensor, resistor R2, current sampling circuit, resistor R4, resistor R3, and self-diagnostic current source.

[0031] Capacitors C1 and C2 are connected in parallel between the power supply pin and the ground pin of the metering chip. The voltage sampling terminal of the metering chip is connected to the SPI bus of the main control module through an isolator. The phase line fault detection terminal of the metering chip is connected to the diagnostic bus matrix through a Schmitt trigger. The calibration pulse output terminal of the metering chip is connected to the diagnostic bus matrix through resistor R1. The ADC terminal of the metering chip is connected to the temperature sensor. The output terminal of the temperature sensor is connected to the diagnostic bus matrix through a series resistor R2. The self-diagnostic current source is connected to the GPIO8 pin of the main control module. The output terminal of the self-diagnostic current source is connected to the current sampling circuit through series resistors R3 and R4.

[0032] The metering chip uses ATT7035AU to realize energy metering and acquisition of parameters such as voltage and current; the Schmitt trigger uses SN74LVC1G17 to shape the phase line fault detection signal; the self-diagnostic current source uses REF200 to inject detection current under the control of the main control chip for self-testing of the metering circuit.

[0033] The metering module in the electricity meter performs core metering and basic fault detection functions. The metering chip, via its V1P / V1N / V2P / V2N / V3P / V3N voltage sampling terminals and an isolator, connects to the main control module's SPI bus to accurately acquire three-phase voltage and current signals, completing the electricity metering operation. The signals output from the metering chip's phase line fault detection terminals (LOSS_A / LOSS_B / LOSS_C) are shaped by a Schmitt trigger and then connected to the diagnostic bus matrix to monitor for faults such as phase loss or voltage drop. The metering chip's calibration pulse output is connected to the diagnostic bus matrix via resistor R_cal, providing metering calibration data for the main control module. A temperature sensor monitors the metering chip's operating temperature in real time; its output signal is transmitted via resistor R2 to the CH0 terminal of the multiplexer in the diagnostic bus matrix for abnormal temperature monitoring. In addition, under the control of the GPIO8 pin of the main control module, the self-diagnostic current source injects detection current into the current sampling circuit through resistors R3 and R4, which can detect whether the metering circuit is normal online, thereby fully ensuring the accuracy and reliability of power metering and providing rich data support for fault diagnosis.

[0034] The communication module group includes: carrier unit, capacitor C3, capacitor C4, peak detection circuit, capacitor C5, switching switch, analog switch, VSWR detector, 4G unit, capacitor C6, and capacitor C7.

[0035] Capacitors C3 and C4 are connected in parallel between the power supply pin and the ground pin of the carrier unit. The RXD / TXD terminal of the carrier unit is connected to the UART0 port of the main control module through a switching switch. The RSSI pin of the carrier unit is connected to the diagnostic bus matrix. The power line coupling terminal of the carrier unit is connected to the analog switch through capacitor C5. The ground pin of the analog switch is grounded. The control terminal of the analog switch is connected to the GPIO9 pin of the main control module. The carrier unit is connected to the diagnostic bus matrix through a peak detection circuit.

[0036] Capacitors C6 and C7 are connected in parallel between the power supply pin and the ground pin of the 4G unit. The RXD / TXD terminal of the 4G unit is connected to the UART0 port of the main control module through a switch. The SIM card presence signal of the 4G unit is connected to the diagnostic bus matrix. The antenna terminal of the 4G unit is connected to the VSWR detector. The output terminal of the VSWR detector is connected to the diagnostic bus matrix.

[0037] The carrier unit uses the HPLC-PLC200 model, which adopts high-speed power line carrier communication technology to realize data transmission through power lines. It supports communication rates of over 1Mbps, and has automatic routing and multi-level relay functions, making it suitable for complex power grid environments.

[0038] The 4G unit uses the SIM7600CE model, which supports 4G full network communication, has a built-in TCP / IP protocol stack, supports GPRS and GPS positioning functions, and has an operating temperature range of -40℃ to +85℃, meeting the needs of complex outdoor environments.

[0039] The switching switch uses TS5A3157 to switch the communication interface; the analog switch uses DG411 to control the connection of fault injection capacitor 5; and the VSWR detector uses AD8302 to monitor the 4G antenna status.

[0040] The communication module group is responsible for remote data transmission and communication link status monitoring within the energy meter, ensuring information exchange between the energy meter and external systems. The carrier unit and 4G unit, as core communication units, have their RXD / TXD terminals connected to the UART0 port of the main control module via a switch. Under the control of the main control module, they can flexibly switch between power line carrier communication and 4G wireless communication to meet data transmission requirements in different application scenarios. The RSSI pin of the carrier unit is connected to the diagnostic bus matrix to provide feedback on the carrier signal strength, facilitating the main control module's assessment of carrier communication quality. The fault injection capacitor C5, connected in parallel at the power line coupling terminal, can be connected to the circuit under the control of the analog switch to simulate communication faults and test the stability and fault detection capability of the carrier communication link. Simultaneously, the carrier coupling voltage, after being processed by the peak detection circuit, is input to the diagnostic bus matrix to provide data for carrier communication status analysis. The SIM card presence signal of the 4G unit is connected to the diagnostic bus matrix, which can monitor the SIM card status in real time. The antenna end is connected to the VSWR detector, and its output is connected to the CH4 channel of the diagnostic bus matrix to detect the working status of the 4G antenna and ensure the normal operation of the 4G communication link. In addition, decoupling capacitors C3, C4, C6, and C7 are connected in parallel between the power supply pin and the ground pin of the carrier unit and the 4G unit, respectively, to effectively filter out power supply noise, ensure the stable operation of the communication unit, and jointly realize the reliable transmission of electricity meter data and comprehensive monitoring of the communication link.

[0041] The diagnostic bus matrix includes: current transformer, comparator 1, multiplexer, ADC driver, and resistor R5.

[0042] The CH0 terminal of the multiplexer is connected to the temperature sensor of the metering module via resistor R2. The CH1 terminal of the multiplexer is connected to the current transformer via comparator 1. The CH2 terminal of the multiplexer is connected to the carrier unit via the peak detection circuit. The CH3 terminal of the multiplexer is connected to the SIM card presence signal of the 4G unit. The CH4 terminal of the multiplexer is connected to the output terminal of the VSWR detector. The address lines of the multiplexer are connected to the main control module. The output terminal of the multiplexer is connected to the ADC driver. The ADC driver is connected to the ADC0 pin of the main control module via resistor R5.

[0043] The multiplexer uses CD4051 to achieve polling and selection of 8 signals; the ADC driver uses OPA333 to enhance signal driving capability; the current transformer uses LEM LA 55-P model, which achieves isolated sampling of primary and secondary current through toroidal iron core structure. The secondary output is processed by LM393 comparator 1 to generate a zero-crossing detection signal, which is connected to the CH1 channel of the multiplexer.

[0044] The diagnostic bus matrix is ​​the core hub of the energy meter fault self-diagnosis system, responsible for collecting, integrating, and transmitting key monitoring signals. The multiplexer connects to the temperature sensor, the secondary zero-crossing detection point of the current transformer CT1, the carrier coupling voltage, the 4G unit SIM card presence signal, and the antenna VSWR detector output via eight input channels CH0-CH4. The main control module controls the address lines A0-A2 of the multiplexer through GPIO5-GPIO7 to achieve time-division multiplexing sampling of the eight signals. The ADC driver converts the analog signal output from the multiplexer into a high-impedance signal, which is then transmitted to the ADC0 pin of the main control module via a current-limiting resistor R5, ensuring signal stability and reliability.

[0045] The multi-level interlocking protection circuit includes: pulse generator, diode D1, trip controller, diode D2, resistor R6, resistor R7, transistor Q1, resistor R8, current mirror sampling resistor, resistor R9, main control module, programmable reference source, voltage window comparator 2, capacitor C8, capacitor C9, fault tracing memory, latch, resistor R10, and watchdog chip.

[0046] The enable pin of the pulse generator is connected to GPIO4 of the main control module via diode D1. The enable pin of the trip controller is connected to GPIO4 of the main control module via diode D2. The trip controller is connected to one end of resistor R6, the other end of which is connected to the base of transistor Q1, one end of resistor R7, and the other end of resistor R7 is connected to ground. The collector of transistor Q1 is connected to the VCC power supply via resistor R8. The emitter of transistor Q1 is connected to one end of resistor R9 via the current mirror sampling resistor, and the other end of resistor R9 is connected to voltage window comparator 2. The programmable reference source is connected to I / O pin of the main control module. 2 The programmable reference source is connected to the reference terminal of voltage window comparator 2 via C. Capacitors C8 and C9 are connected in parallel between the power supply pin and the ground pin of voltage window comparator 2. Voltage window comparator 2 is connected to the latch via resistor R10. The watchdog chip is connected to the RESET pin of the latch. The output of the latch is connected to the WP write protection terminal of the fault tracing memory. The fault tracing memory is connected to the trip controller.

[0047] The pulse generator uses the SN74HC123, a dual retriggable monostable multivibrator, to generate standard energy metering pulses for calibration and verification of metering accuracy.

[0048] The trip controller uses the HT7150, a relay driver chip with a locking function, which receives signals from the main control module or protection circuit and controls the relay to cut off the circuit.

[0049] The current mirror sampling resistor is a CSR2512-0.1Ω-1%, a precision current sensing resistor, which accurately samples the trip current and provides feedback signals for the protection circuit.

[0050] The voltage window comparator 2 uses a TLV3202 to monitor voltage and current anomalies; the programmable reference source uses a MAX6126 to dynamically set the protection threshold; the latch uses an SN74LVC1G373 to lock fault signals; and the watchdog chip uses a TPS3823 to prevent the program from running away.

[0051] Multi-level interlocking protection circuits construct a robust safety protection system within the energy meter, ensuring the safe and stable operation of the energy meter and the power consumption system through a multi-level linkage mechanism. Voltage window comparator 2, as a front-end monitoring element, has its reference terminal connected to a programmable reference source, which can be controlled by the main control module via I / O. 2 The C-bus allows for flexible setting of high and low thresholds, enabling real-time monitoring of signals such as the +3.3V output voltage from the power module and the current fed back from the emitter of transistor Q1 driven by the trip controller via the current mirror sampling resistor. When the monitored signal exceeds the set threshold, the voltage window comparator 2 outputs a signal, which is transmitted to the latch via the current-limiting resistor R10. This triggers the latch to lock the fault signal, thereby driving the trip controller to execute a forced trip, quickly disconnecting the circuit. Simultaneously, the latch's reset terminal is connected to the RESET output of the watchdog chip. If the main control module experiences a program abnormality, the watchdog chip outputs a reset signal to reset the latch, preventing false triggering. Furthermore, the latch's Q output terminal is connected to the WP write protection terminal of the fault tracing memory. When a trip occurs, the write protection of the fault tracing memory is released, ensuring that the main control module can reliably store fault information, providing complete data for subsequent fault analysis.

[0052] The fault tracing memory includes resistor R11, resistor R12, capacitor C10, and capacitor C11;

[0053] The fault tracing memory is a ferroelectric memory of model FM24C04. The SDA pin of the fault tracing memory is connected to the I pin of the main control module via resistor R11. 2 The C bus is connected, and the SCL pin of the fault tracing memory is connected to the I pin of the main control module via resistor R12. 2 The C bus is connected, and capacitors C10 and C11 are connected in parallel between the power supply pin and the ground pin of the fault tracing memory.

[0054] The storage area uses hexadecimal address encoding, with a total capacity of 256 bytes and addresses from 00H to FFH. It is divided into three functionally independent segments: timestamp segment, fault code segment, and environmental parameter segment. The timestamp segment address is 00-3F, the fault code segment is 40-7F, and the environmental parameter segment is 80-FF.

[0055] When the latch output signal in the multi-level interlocking protection circuit triggers a trip, its Q output will release the WP write protection lock state of the fault tracing memory. At this time, the main control module can immediately write the precise time of the fault occurrence into the timestamp segment, the specific fault type code into the fault code segment, and environmental parameters such as voltage and temperature at the time of the fault into the environmental parameter segment. This design not only ensures the integrity and immutability of the fault data, but also provides detailed and reliable data support for subsequent fault cause analysis and system optimization, enabling accurate tracing and in-depth analysis of electricity meter faults.

[0056] This technical solution constructs a complete and efficient self-diagnosis and protection system for electricity meter faults. The main control module, as the core hub, coordinates the metering module to collect voltage, current, and other data in real time to complete electricity metering, and transmits this data to the main control module via the SPI bus. Under the main control command, the communication module group flexibly selects carrier or 4G communication via a switch to achieve remote data interaction. Simultaneously, its fault injection capacitor and VSWR detector monitor the communication link status in real time. The diagnostic bus matrix uses a multiplexer to collect eight key signals, including metering temperature and communication signal strength, in a time-division manner. These signals are processed by an ADC driver and then analyzed by the main control module. The multi-level interlocking protection circuit monitors voltage and current in real time through a voltage window comparator 2. Once a threshold is exceeded, a latch triggers the trip controller to cut off power and activates the fault tracing memory to release write protection. At this time, the main control module quickly stores the fault time, code, and environmental parameters in the fault tracing memory, achieving accurate fault location and reliable information recording. The entire system significantly improves fault detection coverage and response speed, ensuring stable operation of the electricity meter.

[0057] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An energy meter with a fault self-diagnosis function circuit, characterized in that, It includes: main control module, metering module, communication module group, multi-level interlocking protection circuit, diagnostic bus matrix, fault tracing memory, and power supply module; The main control module is connected to the metering module, the communication module group, the multi-level interlocking protection circuit, the diagnostic bus matrix, and the fault tracing memory. The diagnostic bus matrix is ​​connected to the metering module and the communication module group. The fault tracing memory is connected to the multi-level interlocking protection circuit. The power supply module is connected to the main control module, the metering module, the communication module group, the multi-level interlocking protection circuit, the diagnostic bus matrix, and the fault tracing memory.

2. The energy meter with a fault self-diagnosis function circuit according to claim 1, characterized in that, The metering module includes: metering chip, capacitor C1, capacitor C2, isolator, Schmitt trigger, resistor R1, temperature sensor, resistor R2, current sampling circuit, resistor R4, resistor R3, and self-diagnostic current source. Capacitors C1 and C2 are connected in parallel between the power supply pin and the ground pin of the metering chip. The voltage sampling terminal of the metering chip is connected to the SPI bus of the main control module through an isolator. The phase line fault detection terminal of the metering chip is connected to the diagnostic bus matrix through a Schmitt trigger. The calibration pulse output terminal of the metering chip is connected to the diagnostic bus matrix through resistor R1. The ADC terminal of the metering chip is connected to the temperature sensor. The output terminal of the temperature sensor is connected to the diagnostic bus matrix through a series resistor R2. The self-diagnostic current source is connected to the GPIO8 pin of the main control module. The output terminal of the self-diagnostic current source is connected to the current sampling circuit through series resistors R3 and R4.

3. The energy meter with a fault self-diagnosis function circuit according to claim 1, characterized in that, The communication module group includes: carrier unit, capacitor C3, capacitor C4, peak detection circuit, capacitor C5, switching switch, analog switch, VSWR detector, 4G unit, capacitor C6, and capacitor C7; Capacitors C3 and C4 are connected in parallel between the power supply pin and the ground pin of the carrier unit. The RXD / TXD terminal of the carrier unit is connected to the UART0 port of the main control module through a switching switch. The RSSI pin of the carrier unit is connected to the diagnostic bus matrix. The power line coupling terminal of the carrier unit is connected to the analog switch through capacitor C5. The ground pin of the analog switch is grounded. The control terminal of the analog switch is connected to the GPIO9 pin of the main control module. The carrier unit is connected to the diagnostic bus matrix through a peak detection circuit. Capacitors C6 and C7 are connected in parallel between the power supply pin and the ground pin of the 4G unit. The RXD / TXD terminal of the 4G unit is connected to the UART0 port of the main control module through a switch. The SIM card presence signal of the 4G unit is connected to the diagnostic bus matrix. The antenna terminal of the 4G unit is connected to the VSWR detector. The output terminal of the VSWR detector is connected to the diagnostic bus matrix.

4. An energy meter with a fault self-diagnosis function circuit according to claim 1, characterized in that, The diagnostic bus matrix includes: current transformer, comparator 1, multiplexer, ADC driver, and resistor R5; The CH0 terminal of the multiplexer is connected to the temperature sensor of the metering module via resistor R2. The CH1 terminal of the multiplexer is connected to the current transformer via comparator 1. The CH2 terminal of the multiplexer is connected to the carrier unit via the peak detection circuit. The CH3 terminal of the multiplexer is connected to the SIM card presence signal of the 4G unit. The CH4 terminal of the multiplexer is connected to the output terminal of the VSWR detector. The address lines of the multiplexer are connected to the main control module. The output terminal of the multiplexer is connected to the ADC driver. The ADC driver is connected to the ADC0 pin of the main control module via resistor R5.

5. An energy meter with a fault self-diagnosis function circuit according to claim 1, characterized in that, The multi-level interlocking protection circuit includes: pulse generator, diode D1, trip controller, diode D2, resistor R6, resistor R7, transistor Q1, resistor R8, current mirror sampling resistor, resistor R9, programmable reference source, voltage window comparator 2, capacitor C8, capacitor C9, fault tracing memory, latch, resistor R10, and watchdog chip. The enable pin of the pulse generator is connected to GPIO4 of the main control module via diode D1. The enable pin of the trip controller is connected to GPIO4 of the main control module via diode D2. The trip controller is connected to one end of resistor R6, the other end of which is connected to the base of transistor Q1, one end of resistor R7, and the other end of resistor R7 is connected to ground. The collector of transistor Q1 is connected to the VCC power supply via resistor R8. The emitter of transistor Q1 is connected to one end of resistor R9 via the current mirror sampling resistor, and the other end of resistor R9 is connected to voltage window comparator 2. The programmable reference source is connected to I / O pin of the main control module. 2 The programmable reference source is connected to the reference terminal of voltage window comparator 2 via C. Capacitors C8 and C9 are connected in parallel between the power supply pin and the ground pin of voltage window comparator 2. Voltage window comparator 2 is connected to the latch via resistor R10. The watchdog chip is connected to the RESET pin of the latch. The output of the latch is connected to the WP write protection terminal of the fault tracing memory. The fault tracing memory is connected to the trip controller.

6. An energy meter with a fault self-diagnosis function circuit according to claim 5, characterized in that, The fault tracing memory includes resistor R11, resistor R12, capacitor C10, and capacitor C11; The fault tracing memory is a ferroelectric memory of model FM24C04. The SDA pin of the fault tracing memory is connected to the I pin of the main control module via resistor R11. 2 The C bus is connected, and the SCL pin of the fault tracing memory is connected to the I pin of the main control module via resistor R12. 2 The C bus is connected, and capacitors C10 and C11 are connected in parallel between the power supply pin and the ground pin of the fault tracing memory.

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