A multi-device model compatible electronic module data synchronization circuit
By combining the main control chip and various circuit modules, automatic identification and dynamic adjustment between multiple device models were achieved, solving the compatibility and stability issues of data synchronization and improving signal quality and system security.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- YIZHANG RENCHUANG ELECTRONIC TECHNOLOGY CO LTD
- Filing Date
- 2025-08-26
- Publication Date
- 2026-06-30
AI Technical Summary
Existing technologies make it difficult to automatically identify and dynamically adjust interface protocols, power performance, signal paths, and clock timings among multiple device models, resulting in poor signal quality and inconsistent timing during data synchronization, especially in high-speed data synchronization or harsh electromagnetic environments.
It adopts a combination of main control chip, signal conditioning circuit, clock matching circuit, signal distribution circuit, interface conversion module, timing control module, performance adjustment circuit and power protection module. The device parameters are pre-stored in EEPROM memory, and the main control chip dynamically adjusts the interface protocol, power performance and clock timing to achieve data synchronization with compatible device models.
It achieves compatibility across multiple device models, reliable data synchronization, and stable system operation, suppresses signal noise and electromagnetic interference, ensures the reliability and stability of interface switching, and balances efficiency and performance.
Smart Images
Figure CN224436890U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of electronic module data synchronization circuit technology, specifically an electronic module data synchronization circuit compatible with multiple device models. Background Technology
[0002] In modern electronic systems, data synchronization is frequently required between electronic devices of different models and brands. These devices typically have different interface protocols, electrical characteristics, and timing requirements. For example, in industrial control, medical equipment, and consumer electronics, various devices may use different communication protocols such as USB, UART, SPI, and I2C, and their requirements for operating voltage, current, and clock signals also differ.
[0003] Currently, there are two main traditional solutions for achieving multi-device data synchronization: one is to design customized interface modules for different models of devices, which leads to high R&D and production costs and lacks flexibility; the other is to use simple general-purpose interface converters, supplemented by software configuration, but this solution usually cannot adaptively adjust hardware parameters, making it difficult to guarantee signal quality and timing consistency. Especially when facing high-speed data synchronization or harsh electromagnetic environments, problems such as data errors, timing mismatches, or power supply mismatches are likely to occur.
[0004] Therefore, there is a lack of hardware circuitry that can automatically identify device type and dynamically adjust interface protocol, power performance, signal path and clock timing accordingly to achieve data synchronization compatible with multiple device models. Utility Model Content
[0005] To address the above problems, this utility model provides an electronic module data synchronization circuit that is compatible with multiple device models, which solves the problem of hardware circuits that cannot automatically identify device types and dynamically adjust interface protocols, power performance, signal paths and clock timing accordingly.
[0006] To achieve the above objectives, the technical solution adopted by this utility model is as follows:
[0007] A multi-device model compatible electronic module data synchronization circuit, comprising:
[0008] The main control chip 100, signal conditioning circuit 200, clock matching circuit 300, signal distribution circuit 400, multiple interface conversion module 600, timing control module 700, performance adjustment circuit 800, power protection module 900, and EEPROM memory 1000 are included.
[0009] The input terminal of the power protection module 900 is used to connect to an external power source, and its output terminal is connected to the input terminal of the performance adjustment circuit 800.
[0010] The output of the performance adjustment circuit 800 supplies power to the main control chip 100, signal conditioning circuit 200, clock matching circuit 300, signal distribution circuit 400 and interface conversion module 600.
[0011] The data output terminal of the main control chip 100 is connected to the input terminal of the signal conditioning circuit 200, and the clock signal terminal of the main control chip 100 is connected to the input terminal of the clock matching circuit 300.
[0012] The output terminal of the signal conditioning circuit 200 is connected to the input terminal of the signal distribution circuit 400;
[0013] The multiple output terminals of the signal distribution circuit 400 are respectively connected to the input terminals of each of the interface conversion modules 600;
[0014] Each interface conversion module 600 is provided with a device-side interface 601 and a device-side interface 602; the device-side interface 602 is provided with a detection pin, which is connected to the general-purpose input / output pin of the main control chip 100;
[0015] The output of the clock matching circuit 300 is connected to the input of the timing control module 700, and the output of the timing control module 700 is fed back to the interrupt or clock input pin of the main control chip 100.
[0016] The EEPROM memory 1000 is connected to the main control chip 100 via an I²C or SPI bus.
[0017] The main control chip 100 is configured to: query the device parameters pre-stored in the EEPROM memory 1000 according to the level signal obtained from the detection pin, and control the working mode of the signal distribution circuit 400, the interface conversion module 600 and the performance adjustment circuit 800 accordingly.
[0018] The beneficial effects of this solution are: through the coordinated connection of various modules, it achieves overall compatibility with multiple models of equipment, reliable data synchronization, and stable and secure system operation.
[0019] As a further improvement to the above technical solution: the signal distribution circuit 400 includes a multiplexer or analog switch array, which is controlled by the main control chip 100 and is used to selectively connect the signal output by the signal conditioning circuit 200 to a certain target interface conversion module 600.
[0020] The beneficial effects of this solution are: it avoids signal conflicts, bus contention, and data leakage problems that may occur when multiple output ports work simultaneously.
[0021] As a further improvement to the above technical solution: the signal conditioning circuit 200 includes an LC filter bank and a differential signal buffer; the input terminal of the LC filter bank serves as the input terminal of the signal conditioning circuit 200, its output terminal is connected to the input terminal of the differential signal buffer, and the output terminal of the differential signal buffer serves as the output terminal of the signal conditioning circuit 200; the power input terminal of the signal conditioning circuit 200 is also connected in parallel with a first decoupling capacitor bank 201.
[0022] The beneficial effects of this solution are: suppression of high-frequency noise and electromagnetic interference (EMI) in the signal; and provision of good impedance matching and signal driving capability.
[0023] As a further improvement to the above technical solution: the clock matching circuit 300 includes a voltage-controlled crystal oscillator (VCXO) and a programmable clock driver; the output terminal of the VCXO is connected to the input terminal of the programmable clock driver, and the output terminal of the programmable clock driver serves as the output terminal of the clock matching circuit 300.
[0024] The beneficial effect of this solution is that it adapts to the specific requirements of different external devices for clock frequency and timing.
[0025] As a further improvement to the above technical solution: the interface conversion module 600 includes a solid-state relay and multiple interface circuits, the interface circuits including USB 2.0, UART, SPI and I2C interface circuits; the solid-state relay is controlled by the main control chip 100 and is used to switch the connection path between the output of the signal distribution circuit 400 and the target interface circuit.
[0026] The beneficial effects of this solution are: solid-state relays have the advantages of fast switching speed, no mechanical contacts, long life and strong anti-interference ability, which ensures the reliability and stability of the interface switching process.
[0027] As a further improvement to the above technical solution: the power protection module 900 includes a TVS diode and a resettable fuse. One end of the TVS diode is connected to the positive input terminal of the power protection module 900, and the other end is connected to the input ground terminal. The resettable fuse is connected in series in the positive input terminal line of the power protection module 900.
[0028] The beneficial effects of this solution are: TVS diodes can quickly clamp transient high-voltage pulses (such as surges and static electricity) from the outside, protecting the precision circuits of the downstream stage from damage; resettable fuses can automatically disconnect when a continuous overcurrent or short circuit occurs in the circuit, and can automatically reset after the fault is cleared, without the need for replacement.
[0029] As a further improvement to the above technical solution: the performance adjustment circuit 800 includes an LDO linear regulator and a DC-DC buck converter. The main control chip 100 is configured to control a load switch to select the output of the LDO linear regulator or the DC-DC buck converter as the output of the performance adjustment circuit 800 according to the required output voltage and current parameters.
[0030] The beneficial effect of this solution is that it balances efficiency and performance by intelligently selecting between LDO or DC-DC power supply.
[0031] As a further improvement to the above technical solution: the device-side interface 602 is provided with a detection pin, which is connected to the general-purpose input / output pin of the main control chip 100.
[0032] The beneficial effect of this solution is that the detection pin can convert the physical characteristics of the connected device (such as specific level and resistance identification) into an electrical signal and transmit it to the main control chip.
[0033] As a further improvement to the above technical solution: the device-side interface 602 also integrates an EMI shielding layer, which is electrically grounded.
[0034] The beneficial effects of this solution are: the EMI shielding layer can effectively block high-frequency electromagnetic interference from the external environment from radiating to the interface connector and cable, and at the same time prevent electromagnetic noise generated inside the interface from radiating outward, significantly reducing the risk of signal interference during transmission.
[0035] As a further improvement to the above technical solution: the EEPROM memory 1000 pre-stores device model identifier, protocol code and voltage parameters; the main control chip 100 is configured to query the EEPROM memory 1000 and control the working mode of the signal distribution circuit 400, interface conversion module 600 and performance adjustment circuit 800 accordingly based on the level signal obtained from the detection pin of the device interface 602.
[0036] The beneficial effect of this solution is that it combines hardware detection, data storage and software control to achieve intelligent configuration of the entire circuit. Attached Figure Description
[0037] Figure 1 This is a block diagram of a data synchronization circuit for an electronic module that is compatible with multiple device models. Detailed Implementation
[0038] To enable those skilled in the art to better understand the technical solution, the present invention will be described in detail below with reference to the embodiments. The description in this part is only exemplary and explanatory, and should not be used to limit the scope of protection of the present invention in any way.
[0039] Example 1: This example provides a basic configuration for a multi-device model compatible electronic module data synchronization circuit. The circuit structure includes a main control chip 100, a signal conditioning circuit 200, a clock matching circuit 300, a signal distribution circuit 400, four interface conversion modules 600, a timing control module 700, a performance adjustment circuit 800, a power protection module 900, and an EEPROM memory 1000.
[0040] The input terminal of the power protection module 900 is connected to an external 12V DC power supply. The cathode of the TVS diode SMBJ12CA is connected to the positive input terminal of the power protection module 900, and the anode is connected to the input ground terminal, used to suppress surge voltage. A resettable fuse MF-R025 with a rated current of 0.25A is connected in series in the positive input circuit of the power protection module 900. The output terminal of the power protection module 900 is connected to the input terminal of the performance adjustment circuit 800.
[0041] The performance adjustment circuit 800 includes an AMS1117-3.3 LDO linear regulator and an LM2676-3.3 DC-DC buck converter. The input and enable terminals of the LDO linear regulator are connected to the input terminals of the performance adjustment circuit 800, and its output is connected to the output terminal of the performance adjustment circuit 800 via the first channel of the load switch TPS22965. The input and enable terminals of the DC-DC buck converter are connected to the input terminals of the performance adjustment circuit 800, and its output is connected to the output terminal of the performance adjustment circuit 800 via the second channel of the load switch TPS22965. The control terminal SEL of the load switch TPS22965 is connected to the PA0 pin of the main control chip 100. The output of the performance adjustment circuit 800 provides a 3.3V system voltage, powering the main control chip 100, signal conditioning circuit 200, clock matching circuit 300, signal distribution circuit 400, and interface conversion module 600.
[0042] The main control chip 100 uses an STM32F407VGT6 microcontroller. The data output pin PA7 of the main control chip 100 is connected to the input of the signal conditioning circuit 200. The clock signal pin PA8 of the main control chip 100 is connected to the input of the clock matching circuit 300.
[0043] The signal conditioning circuit 200 includes an LC filter bank and a differential signal buffer AD8132. The LC filter bank is a π-type filter, composed of a first inductor L1 (10μH), a second inductor L2 (10μH), a first capacitor C1 (100nF), a second capacitor C2 (100nF), and a third capacitor C3 (100nF). One end of the first inductor L1 serves as the input terminal of the signal conditioning circuit 200, and the other end is connected to one end of the second inductor L2. The first capacitor C1 is connected between the input terminal of the signal conditioning circuit 200 and ground. The second capacitor C2 is connected between the junction of the first inductor L1 and the second inductor L2 and ground. The third capacitor C3 is connected between the output terminal of the second inductor L2 and ground. The output terminal of the second inductor L2 is connected to the input terminal of the differential signal buffer AD8132. The output terminal of the differential signal buffer AD8132 serves as the output terminal of the signal conditioning circuit 200. The power input terminal of the signal conditioning circuit 200 is connected in parallel with the first decoupling capacitor bank 201, which consists of a 10μF electrolytic capacitor and a 100nF ceramic capacitor connected in parallel.
[0044] The signal distribution circuit 400 uses a multiplexer ADG704. The input terminal of the multiplexer ADG704 serves as the input terminal of the signal distribution circuit 400 and is connected to the output terminal of the signal conditioning circuit 200. The four output terminals of the multiplexer ADG704 serve as the four output terminals of the signal distribution circuit 400. The two channel selection control terminals S0 and S1 of the multiplexer ADG704 are connected to the PA1 and PA2 pins of the main control chip 100.
[0045] The four outputs of the multiplexer ADG704 are respectively connected to the inputs of the four interface conversion modules 600.
[0046] Each interface conversion module 600 is provided with a device-side interface 601 and a device-side interface 602. The device-side interface 601 is connected to one output terminal of the signal distribution circuit 400. The device-side interface 602 is a USB Type-C interface. The detection pins CC1 and CC2 of the device-side interface 602 are connected to the PC0 and PC1 general-purpose input / output pins of the main control chip 100, respectively.
[0047] The clock matching circuit 300 includes a voltage-controlled crystal oscillator (ECS-2520MVQ) and a programmable clock driver (CY2305). The output of the ECS-2520MVQ is connected to the input of the programmable clock driver (CY2305). The output of the programmable clock driver (CY2305) serves as the output of the clock matching circuit 300, providing four clock signals.
[0048] The output of the clock matching circuit 300 is connected to the input of the timing control module 700. The timing control module 700 uses a programmable clock buffer NB3N551. The input of the programmable clock buffer NB3N551 is connected to the output of the clock matching circuit 300, and its output is fed back to the PB0 interrupt pin of the main control chip 100. The main control chip 100 dynamically adjusts the output parameters of the programmable clock driver CY2305 by running a phase detection algorithm to achieve clock synchronization.
[0049] The EEPROM memory 1000 uses the AT24C256. The SDA pin of the EEPROM memory 1000 is connected to the PB7 pin of the main control chip 100 via the I²C bus, and the SCL pin is connected to the PB6 pin of the main control chip 100. The device parameters pre-stored in the EEPROM memory 1000 include the device model identifier, protocol code, voltage parameters, and current parameters.
[0050] The main control chip 100 is configured to: query the device parameters pre-stored in the EEPROM memory 1000 based on the combination of level signals obtained from the detection pins PC0 and PC1, and control the channel selection of the signal distribution circuit 400, the protocol switching of the interface conversion module 600, and the working mode of the performance adjustment circuit 800.
[0051] Example 2: This example describes a specific implementation of the signal conditioning circuit 200 and the clock matching circuit 300.
[0052] The LC filter bank of the signal conditioning circuit 200 adopts a second-order Butterworth low-pass filter structure with a cutoff frequency set to 10MHz. The first inductor L1 and the second inductor L2 are 10μH wire-wound inductors with a tolerance of 5%. The first capacitor C1, the second capacitor C2, and the third capacitor C3 are 100nF NPO ceramic capacitors with a tolerance of 5%. The gain of the differential signal buffer AD8132 is set to 2 through its external feedback resistor, with a bandwidth of 50MHz. In the first decoupling capacitor bank 201, the 10μF electrolytic capacitor has a voltage rating of 16V, and the 100nF ceramic capacitor has a voltage rating of 50V.
[0053] In the clock matching circuit 300, the frequency stability of the voltage-controlled crystal oscillator ECS-2520MVQ is ±25ppm, and the operating voltage is 3.3V. The programmable clock driver CY2305 provides four outputs, and the drive capability of each output can be independently programmed and set by the main control chip 100 via the I²C bus, with an output frequency range between 1MHz and 200MHz.
[0054] The timing control module 700's programmable clock buffer NB3N551 has a digitally programmable delay function with a delay step of 25 picoseconds and a maximum delay range of 2 nanoseconds. The main control chip 100 configures the delay parameters of the NB3N551 via the I²C bus and forms a closed-loop control by monitoring the clock phase on its PB0 pin, keeping the clock synchronization error within 100 picoseconds.
[0055] Example 3: This example describes a specific implementation of power management, interface conversion, and electromagnetic compatibility.
[0056] In the performance adjustment circuit 800, the LDO linear regulator AMS1117-3.3 has a maximum output current of 1A and a voltage drop of 1.2V. The DC-DC buck converter LM2676-3.3 has a switching frequency of 260kHz, a maximum output current of 3A, and an efficiency of 92%. The load switch TPS22965 has an on-resistance of 20 milliohms and a maximum continuous current of 3A. The main control chip 100 determines the required current of the device based on the pre-stored device current parameters in the EEPROM memory 1000: when the required operating current of the device is less than 300mA, it controls the PA0 pin to output a low level, selecting the output of the LDO linear regulator; when the required operating current of the device is greater than or equal to 300mA, it controls the PA0 pin to output a high level, selecting the output of the DC-DC buck converter.
[0057] The interface conversion module 600 includes a solid-state relay TLP176AM and various interface circuits. The control terminal of the solid-state relay TLP176AM is connected to the PA3 pin of the main control chip 100 to switch the operating mode of the interface circuits. The interface circuits include USB 2.0 interface circuits, UART interface circuits, SPI interface circuits, and I2C interface circuits. The USB 2.0 interface circuit uses a USB3320 transceiver and supports a data transfer rate of 480Mbps. The UART interface circuit uses a MAX3232 level converter and supports a baud rate of up to 1Mbps. The SPI interface circuit is directly connected to the SPI1 peripheral pin of the main control chip 100 and supports a clock frequency of up to 42Mbps. The I2C interface circuit is directly connected to the I2C1 peripheral pin of the main control chip 100 and supports standard mode (100kHz), fast mode (400kHz), and high-speed mode (3.4MHz).
[0058] The device-side interface 602 integrates an EMI shielding layer. The EMI shielding layer uses 0.1 mm thick copper foil material and achieves 360-degree electrical connection with the system ground plane through two grounding solder points, with a shielding effectiveness of over 40 dB.
[0059] In the power protection module 900, the TVS diode SMBJ12CA has a breakdown voltage of 13.3V, a maximum clamping voltage of 19.9V, and can withstand a peak pulse power of 600W. The resettable fuse MF-R025 has a holding current of 0.25A and a trigger current of 0.5A, and can automatically recover within 60 seconds after overcurrent is eliminated.
[0060] The main control chip 100, based on the device identifier obtained from the detection pin, queries the pre-stored required current parameters for the corresponding device in the EEPROM memory 1000, and makes a judgment based on these parameters: when PC0 is high and PC1 is low, the connected device is identified as model A; when PC0 is low and PC1 is high, the connected device is identified as model B; when both PC0 and PC1 are high, the connected device is identified as model C. Based on the identification result, the main control chip 100 reads the corresponding device parameters from the EEPROM memory 1000 and configures the operating mode of the entire system.
[0061] It should be noted that, in this document, the terms "comprising," "including," and any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Specific examples have been used in this document to illustrate the principles and implementation methods of the present invention. These examples are merely for the purpose of helping to understand the method and core ideas of the present invention. The above descriptions are only preferred embodiments of the present invention. It should be pointed out that, due to the limitations of written expression and the objective existence of infinite specific structures, those skilled in the art can make several improvements, modifications, or variations without departing from the principles of the present invention, and can also combine the above technical features in an appropriate manner. These improvements, modifications, variations, or combinations, or the direct application of the concept and technical solution of the present invention to other situations without modification, should all be considered within the scope of protection of the present invention.
Claims
1. A multi-device model compatible electronic module data synchronization circuit, characterized in that, include: The main control chip (100), signal conditioning circuit (200), clock matching circuit (300), signal distribution circuit (400), multiple interface conversion module (600), timing control module (700), performance adjustment circuit (800), power protection module (900) and EEPROM memory (1000); The input terminal of the power protection module (900) is used to connect to an external power source, and its output terminal is connected to the input terminal of the performance adjustment circuit (800). The output of the performance adjustment circuit (800) supplies power to the main control chip (100), signal conditioning circuit (200), clock matching circuit (300), signal distribution circuit (400) and interface conversion module (600); The data output terminal of the main control chip (100) is connected to the input terminal of the signal conditioning circuit (200), and the clock signal terminal of the main control chip (100) is connected to the input terminal of the clock matching circuit (300). The output terminal of the signal conditioning circuit (200) is connected to the input terminal of the signal distribution circuit (400); The multiple output terminals of the signal distribution circuit (400) are respectively connected to the input terminals of each of the interface conversion modules (600); Each interface conversion module (600) is provided with a device-side interface (601) and a device-side interface (602); the device-side interface (602) is provided with a detection pin, which is connected to the general-purpose input / output pin of the main control chip (100); The output of the clock matching circuit (300) is connected to the input of the timing control module (700), and the output of the timing control module (700) is fed back to the interrupt or clock input pin of the main control chip (100). The EEPROM memory (1000) is connected to the main control chip (100) via an I²C or SPI bus; The main control chip (100) is configured to: query the device parameters pre-stored in the EEPROM memory (1000) according to the level signal obtained from the detection pin, and control the working mode of the signal distribution circuit (400), interface conversion module (600) and performance adjustment circuit (800).
2. The multi-device model compatible electronic module data synchronization circuit according to claim 1, characterized in that, The signal distribution circuit (400) includes a multiplexer or analog switch array, which is controlled by the main control chip (100) and is used to selectively connect the signal output by the signal conditioning circuit (200) to the target interface conversion module (600).
3. The multi-device model compatible electronic module data synchronization circuit according to claim 1, characterized in that, The signal conditioning circuit (200) includes an LC filter bank and a differential signal buffer; the input terminal of the LC filter bank serves as the input terminal of the signal conditioning circuit (200), and its output terminal is connected to the input terminal of the differential signal buffer, and the output terminal of the differential signal buffer serves as the output terminal of the signal conditioning circuit (200); the power input terminal of the signal conditioning circuit (200) is also connected in parallel with a first decoupling capacitor bank (201).
4. The multi-device model compatible electronic module data synchronization circuit according to claim 1, characterized in that, The clock matching circuit (300) includes a voltage-controlled crystal oscillator and a programmable clock driver; the output terminal of the voltage-controlled crystal oscillator is connected to the input terminal of the programmable clock driver, and the output terminal of the programmable clock driver serves as the output terminal of the clock matching circuit (300).
5. The multi-device model compatible electronic module data synchronization circuit according to claim 1, characterized in that, The interface conversion module (600) includes a solid-state relay and multiple interface circuits, including USB 2.0, UART, SPI and I2C interface circuits; the solid-state relay is controlled by the main control chip (100).
6. The multi-device model compatible electronic module data synchronization circuit according to claim 1, characterized in that, The power protection module (900) includes a TVS diode and a resettable fuse. One end of the TVS diode is connected to the positive input terminal of the power protection module (900), and the other end is connected to the input ground terminal. The resettable fuse is connected in series in the positive input terminal line of the power protection module (900).
7. The multi-device model compatible electronic module data synchronization circuit according to claim 1, characterized in that, The performance adjustment circuit (800) includes an LDO linear regulator and a DC-DC buck converter. The main control chip (100) is configured to control a load switch to select the output of the LDO linear regulator or the DC-DC buck converter as the output of the performance adjustment circuit (800) according to the required output voltage and current parameters.
8. The multi-device model compatible electronic module data synchronization circuit according to claim 1, characterized in that, The detection pin is used to receive pull-up or pull-down level signals from the connected device.
9. The multi-device model compatible electronic module data synchronization circuit according to claim 1, characterized in that, The device-side interface (602) also integrates an EMI shielding layer, which is electrically grounded.
10. The multi-device model compatible electronic module data synchronization circuit according to claim 1, characterized in that, The device parameters pre-stored in the EEPROM memory (1000) include device model identifier, protocol code, and voltage parameters.