An LCD port mapping circuit

Abstract

This utility model relates to the field of LCD port mapping technology, and discloses an LCD port mapping circuit, including a first counting circuit, a second counting circuit, a reset circuit, a counting stop circuit, a D flip-flop DFF10, and a second decoding circuit. In practical use, this utility model selects the corresponding COM port by inputting a COM enable signal to the counting stop circuit, and simultaneously allows the counting stop circuit to input a counting stop signal to the second counting circuit, so that the count value of the second counting circuit can be maintained at the corresponding COM port. Finally, the corresponding COM port is selected by outputting a relevant selection signal through the second decoding circuit. In addition, the count value of the second counting circuit can be reset by the first counting circuit and the reset circuit, thereby satisfying the cyclic scanning of the COM port, and finally realizing the COM port selection when the MCU performs LCD display.

Description

Technical Field

[0001] This utility model relates to the field of LCD port mapping technology, and specifically to an LCD port mapping circuit. Background Technology

[0002] In MCU applications, LCDs are used to display information. Specifically, the MCU connects to the LCD through its own data port and COM port, and displays information by controlling the level changes of the data port and COM port.

[0003] As the integration level of general-purpose MCUs increases, port functions become more complex. Typically, a single port may have multiple function mappings, such as integrating serial port, LCD, and PWM functions. It is important to note that a port can only use one function at a time.

[0004] For existing MCUs, the selection of COM ports for LCD display is controlled by duty cycle. The duty cycle represents the proportion of scanning time of a COM port within one frame. Therefore, 1 / N duty cycle means there are N COM ports.

[0005] by Figure 1 Taking the MCU shown as an example, there are four COM ports. When a half duty cycle is selected, COM0 and COM1 ports will be enabled, and COM0 and COM1 ports will be scanned cyclically in each frame. When a one-third duty cycle is selected, COM0, COM1, and COM2 ports will be enabled, and COM0 to COM2 ports will be scanned cyclically in each frame. When a one-quarter duty cycle is selected, COM0, COM1, COM2, and COM3 ports will be enabled, and COM0 to COM3 ports will be scanned cyclically in each frame.

[0006] When selecting a quarter duty cycle, the corresponding LCD clock and COM port level changes are as follows: Figure 2 As shown, in Figure 2 In the process, all four COM ports were scanned.

[0007] In the existing LCD port mapping method, the COM ports used for LCD display are fixed and cannot be flexibly applied, failing to meet real-world usage requirements. For example, when COM1 and COM2 ports are needed for LCD display and COM0 port is needed for PWM port driving, the half-duty cycle control method cannot be used. Utility Model Content

[0008] In view of the shortcomings of the background technology, the present invention provides an LCD port mapping circuit. The technical problem to be solved is that the COM ports required by the existing LCD for display are fixed in advance, and the required COM ports cannot be selected according to actual needs.

[0009] To solve the above technical problems, this utility model provides the following technical solution: an LCD port mapping circuit, including a first counting circuit, a second counting circuit, a reset circuit, a counting stop circuit, a D flip-flop DFF10, and a second decoding circuit;

[0010] The first counting circuit counts the input clock signal CLK2N. The reset circuit generates a reset signal input to the first and second counting circuits based on the input duty cycle control signal and the count value of the first counting circuit. The reset signal is used to reset the count values ​​of the first and second counting circuits to zero.

[0011] The counting stop circuit inputs a counting stop signal to the second counting circuit based on the input COM enable signal and the count value of the second counting circuit. The counting stop signal is used to pause the counting of the second counting circuit.

[0012] The D input terminal of the D flip-flop DFF10 is electrically connected to the counting output terminal of the second counting circuit. The clock input terminal of the D flip-flop DFF10 is used to input the clock signal CLK2. The Q output terminal of the D flip-flop DFF10 is electrically connected to the second decoding circuit. The second decoding circuit decodes the signal at the Q output terminal of the D flip-flop DFF10 and outputs a COM selection signal. The COM selection signal is used to select the COM port of the MCU for LCD display.

[0013] In one implementation, the clock signal CLK2N and the clock signal CLK2 are two opposite clock signals.

[0014] In one embodiment, the present invention further includes a clock signal generation circuit, which includes a frequency divider and an inverter INV1. The input terminal of the frequency divider is used to input the system clock CLK1, and the output terminal of the frequency divider is used to output the clock signal CLK2. The input terminal of the inverter INV1 is electrically connected to the output terminal of the frequency divider, and the output terminal of the inverter INV1 is used to output the clock signal CLK2N.

[0015] In one embodiment, the first counting circuit includes T flip-flops TFF1, TFF2, and TFF3; the clock input terminal of TFF1 is used to input the clock signal CLK2N, the QN output terminal of TFF1 is electrically connected to the clock input terminal of TFF2, and the QN output terminal of TFF2 is electrically connected to the clock input terminal of TFF3; the Q output terminals of TFF1, TFF2, and TFF3 are the counting terminals of the first counting circuit.

[0016] In one embodiment, the reset circuit includes AND gates AND1-AND4 and NOR gate NOR1. One input of AND gate AND1 is electrically connected to the Q output of T flip-flop TFF3, and the other input of AND gate AND1 is used to input a quarter-duty cycle control signal 1P4. Two of the three inputs of AND gate AND2 are electrically connected to the Q outputs of T flip-flop TFF2 and T flip-flop TFF1, respectively. The remaining input of AND gate AND2 is used to input a one-third-duty cycle control signal 1P3. One input of AND gate AND3 is electrically connected to the Q output of T flip-flop TFF2, and the other input is used to input a half-duty cycle control signal 1P2.

[0017] The outputs of AND1, AND2, and AND3 are electrically connected to the three inputs of NOR1. The output of NOR1 is electrically connected to one input of AND4. The other input of AND4 is used to input the enable signal EN. The output of AND4 is electrically connected to the reset terminals of TFF1, TFF2, and TFF3, respectively.

[0018] In one embodiment, the second counting circuit includes a T flip-flop TFF10, a T flip-flop TFF11, an AND gate AND11, and an AND gate AND12;

[0019] The two input terminals of the AND gate AND11 are used to input the counting stop signal and the system clock CLK1, respectively. The output terminal of the AND gate AND11 is electrically connected to the clock terminal of the TFF flip-flop TFF10, and the QN output terminal of the TFF flip-flop TFF10 is electrically connected to the clock terminal of the TFF flip-flop TFF11.

[0020] The two input terminals of the AND gate AND12 are used to input the enable signal EN and the reset signal, respectively, and the output terminal of the AND gate AND11 is electrically connected to the reset terminal of the T flip-flop TFF10 and the reset terminal of the T flip-flop TFF11, respectively.

[0021] The Q output terminals of the TFF flip-flop TFF10 and TFF flip-flop TFF11 are the counting terminals of the second counting circuit.

[0022] In one embodiment, the counting stop circuit includes a first decoding circuit, NAND gates NAND10 to NAND gates NAND14, an inverter INV10, a D flip-flop DFF11, a pulse generation circuit, and an AND gate AND10;

[0023] The first decoding circuit decodes the count value of the second counting circuit and outputs decoding signals COM0S to COM3S; one input terminal of NAND gate NAND10, one input terminal of NAND gate NAND11, one input terminal of NAND gate NAND12, and one input terminal of NAND gate NAND13 are respectively used to input decoding signals COM0S, COM1S, COM2S, and COM3S; the other input terminal of NAND gate NAND10, the other input terminal of NAND gate NAND11, the other input terminal of NAND gate NAND12, and the other input terminal of NAND gate NAND13 are respectively used to input enable signals COM0EN, COM1EN, COM2EN, and COM3EN; the NAND gate NAND... The outputs of NAND gates 10, 11, 12, 13, and 14 are electrically connected to the four inputs of NAND gate 14. The output of NAND gate 14 is electrically connected to the D input of D flip-flop DFF11. The clock input of D flip-flop DFF11 is electrically connected to the output of inverter INV10. The input of inverter INV10 is used to input the system clock CLK1. The QN output of D flip-flop DFF11 outputs the counting stop signal. The reset input of D flip-flop DFF11 is electrically connected to the output of AND gate AND10. One input of AND gate AND10 is used to input the enable signal EN. The other input of AND gate AND10 is electrically connected to the output of the pulse generator circuit. The input of the pulse generator circuit is used to input the clock signal CLK2N.

[0024] In one implementation, the first decoding circuit is a 2-to-4 decoding circuit.

[0025] In one embodiment, the second decoding circuit is a 2-to-4 decoding circuit.

[0026] In one implementation, the frequency of the clock signal CLK2 output by the frequency divider is one-quarter of the frequency of the system clock CLK1.

[0027] The advantages of this invention compared to existing technologies are as follows: In practical use, this invention selects the corresponding COM port by inputting a COM enable signal to the counting stop circuit, and simultaneously inputs a counting stop signal to the second counting circuit. This allows the count value of the second counting circuit to remain at the corresponding COM port. Finally, the second decoding circuit outputs a relevant selection signal to select the corresponding COM port. In addition, the count value of the second counting circuit can be reset by the first counting circuit and the reset circuit, thereby satisfying the cyclic scanning of the COM port and ultimately realizing the COM port selection when the MCU performs LCD display. Attached Figure Description

[0028] Figure 1 This is a pin diagram of an existing MCU;

[0029] Figure 2 Figure 1 Timing diagram of the MCU when setting a quarter duty cycle for LCD display;

[0030] Figure 3 This is a schematic diagram of the structure of the present invention in the embodiments;

[0031] Figure 4 This is a circuit diagram of the clock signal generation circuit, the first counting circuit, and the reset circuit in the embodiment.

[0032] Figure 5 The circuit diagram shows the second counting circuit, the counting stop circuit, the D flip-flop DFF10, and the second decoding circuit in the embodiment.

[0033] Figure 6 This is a timing diagram showing the relevant timing information when the circuit is used in the embodiment;

[0034] Figure 7 This is a timing diagram showing the relevant usage of the circuit in the embodiment. Detailed Implementation

[0035] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the present invention, and therefore only show the components relevant to the present invention.

[0036] like Figure 3 As shown, an LCD port mapping circuit includes a first counting circuit 1, a second counting circuit 2, a reset circuit 3, a counting stop circuit 4, a D flip-flop DFF10, and a second decoding circuit 5.

[0037] The first counting circuit 1 counts the input clock signal CLK2N. The reset circuit generates a reset signal RST, which is input to the first counting circuit 1 and the second counting circuit 2, based on the input duty cycle control signal and the count value of the first counting circuit. The reset signal RST is used to reset the count values ​​of the first counting circuit 1 and the second counting circuit 2 to zero.

[0038] The counting stop circuit 4 inputs a counting stop signal STOP to the second counting circuit 2 based on the input COM enable signal and the count value of the second counting circuit 2. The counting stop signal STOP is used to stop the counting of the second counting circuit 2.

[0039] The D input terminal of the D flip-flop DFF10 is electrically connected to the counting output terminal of the second counting circuit 2. The clock input terminal of the D flip-flop DFF10 is used to input the clock signal CLK2. The Q output terminal of the D flip-flop DFF10 is electrically connected to the second decoding circuit 5. The second decoding circuit 5 decodes the signal at the Q output terminal of the D flip-flop DFF10 and outputs a COM selection signal. The COM selection signal is used to select the COM port of the MCU for LCD display.

[0040] In practical use, this invention selects the corresponding COM port by inputting a COM enable signal to the counting stop circuit 4, and simultaneously inputs a counting stop signal STOP to the second counting circuit 2. This allows the counting value of the second counting circuit 3 to remain at the corresponding COM port. Finally, the second decoding circuit 5 outputs a relevant selection signal to select the corresponding COM port. In addition, the counting value of the second counting circuit 2 can be reset by the first counting circuit 1 and the reset circuit 3, thereby satisfying the cyclic scanning of the COM port and ultimately realizing the COM port selection when the MCU performs LCD display.

[0041] In this embodiment, clock signal CLK2N and clock signal CLK2 are two opposite clock signals, and these two clock signals are generated by... Figure 4 The clock signal is generated by the clock signal generation circuit 6 shown.

[0042] exist Figure 4 The clock signal generation circuit 6 includes a frequency divider and an inverter INV1. The input of the frequency divider is used to input the system clock CLK1, and the output of the frequency divider is used to output the clock signal CLK2. The input of the inverter INV1 is electrically connected to the output of the frequency divider, and the output of the inverter INV1 is used to output the clock signal CLK2N.

[0043] Specifically, in this implementation, the frequency divider ratio is one-quarter, that is, the frequency of the clock signal CLK2 output by the frequency divider is one-quarter of the frequency of the system clock CLK1.

[0044] exist Figure 4 In the first counting circuit 1, there are T flip-flops TFF1, TFF2, and TFF3. The clock input terminal of TFF1 is used to input the clock signal CLK2N. The QN output terminal of TFF1 is electrically connected to the clock input terminal of TFF2, and the QN output terminal of TFF2 is electrically connected to the clock input terminal of TFF3. The Q output terminals of TFF1, TFF2, and TFF3 are the counting terminals of the first counting circuit.

[0045] exist Figure 4 In the reset circuit 3, AND gates AND1-AND4 and NOR gate NOR1 are included. One input of AND gate AND1 is electrically connected to the Q output of T flip-flop TFF3, and the other input of AND gate AND1 is used to input the quarter-duty cycle control signal 1P4. Two of the three inputs of AND gate AND2 are electrically connected to the Q outputs of T flip-flop TFF2 and T flip-flop TFF1, respectively. The remaining input of AND gate AND2 is used to input the third-third-duty cycle control signal 1P3. One input of AND gate AND3 is electrically connected to the Q output of T flip-flop TFF2, and the other input is used to input the half-duty cycle control signal 1P2.

[0046] The outputs of AND1, AND2, and AND3 are electrically connected to the three inputs of NOR1. The output of NOR1 is electrically connected to one input of AND4. The other input of AND4 is used to input the enable signal EN. The output of AND4 is electrically connected to the reset terminals of TFF1, TFF2, and TFF3, respectively.

[0047] In actual use, the half-duty cycle control signal 1P2, the one-third duty cycle control signal 1P3, and the one-quarter duty cycle control signal 1P4 are all active high. Assuming that the input one-quarter duty cycle control signal 1P4 is high, when the first counting circuit counts to 3, the reset circuit 3 outputs a reset signal RST to reset the first counting circuit to count 1, and the count value is 0.

[0048] Specifically, in this embodiment, as Figure 5 As shown, the second counting circuit includes T flip-flop TFF10, T flip-flop TFF11, AND gate AND11, and AND gate AND12;

[0049] The two input terminals of AND gate AND11 are used to input the counting stop signal STOP and the system clock CLK1, respectively. The output terminal of AND gate AND11 is electrically connected to the clock terminal of TFF flip-flop TFF10, and the QN output terminal of TFF10 is electrically connected to the clock terminal of TFF11.

[0050] The two input terminals of AND gate AND12 are used to input the enable signal EN and the reset signal RST, respectively. The output terminal of AND gate AND11 is electrically connected to the reset terminal of T flip-flop TFF10 and the reset terminal of T flip-flop TFF11, respectively.

[0051] The Q output of TFF10 and the Q output of TFF11 are the counting terminals of the second counting circuit.

[0052] Specifically, in this embodiment, as Figure 5 As shown, the counting stop circuit 4 includes a first decoding circuit, NAND gates NAND10 to NAND14, an inverter INV10, a D flip-flop DFF11, a pulse generation circuit, and an AND gate AND10;

[0053] The first decoding circuit decodes the count value of the second counting circuit 2 and outputs decoding signals COM0S to COM3S; one input terminal of NAND gate NAND10, one input terminal of NAND gate NAND11, one input terminal of NAND gate NAND12 and one input terminal of NAND gate NAND13 are respectively used to input decoding signals COM0S, COM1S, COM2S and COM3S;

[0054] The other input terminals of NAND gate NAND10, NAND gate NAND11, NAND gate NAND12, and NAND gate NAND13 are used to input enable signals COM0EN, COM1EN, COM2EN, and COM3EN, respectively.

[0055] The outputs of NAND gates NAND10, NAND gates NAND11, NAND gates NAND12, and NAND gates NAND13 are electrically connected to the four inputs of NAND gate NAND14. The output of NAND gate NAND14 is electrically connected to the D input of D flip-flop DFF11. The clock input of D flip-flop DFF11 is electrically connected to the output of inverter INV10. The input of inverter INV10 is used to input the system clock CLK1. The QN output of D flip-flop DFF11 outputs the count stop signal STOP. The reset input of D flip-flop DFF11 is electrically connected to the output of AND gate AND10. One input of AND gate AND10 is used to input the enable signal EN. The other input of AND gate AND10 is electrically connected to the output of the pulse generation circuit. The input of the pulse generation circuit is used to input the clock signal CLK2N. In this embodiment, the pulse generation circuit is used to generate a low-level pulse when the clock signal CLK2N changes from low to high.

[0056] In this embodiment, the first decoding circuit is an existing 2-to-4 decoding circuit; the second decoding circuit 5 is an existing 2-to-4 decoding circuit.

[0057] To select half duty cycle control, and to select Figure 1 Taking COM1 and COM3 ports as an example, the enable signal COM0EN is set to 0 (level state), the enable signal COM1EN is set to 1 (high level state), the enable signal COM2EN is set to 0, and the enable signal COM3EN is set to 1; then... Figure 5 The circuit shown selects the enabled COM port. The waveforms of the count values ​​of the first counting circuit 1, the second counting circuit 2, and related signals are as follows: Figure 6 and 7 As shown, from Figure 6 and Figure 7 From this, we can see that when the count value of the second counting circuit 2 is decoded by the first decoding circuit and processed by four NAND gates and the corresponding enable signal COMXEN to be 1, after the falling edge of the system clock CLK1, the counting stop signal STOP is low, and the second counting circuit 2 stops counting, so that the count value of the second counting circuit 2 stops at the label of the corresponding enabled COM port; after the rising edge of the clock signal CLK2, the output signal SEL<1:0> of the D flip-flop DFF10 is updated to the current count value of the second counting circuit 2, and after being decoded by the second decoding circuit 5, the selection signal of the corresponding COM port is generated; Figure 7 In the process, when the count value of the second counting circuit 2 is 1, the COM selection signal COM1_SEL is high, and when the count value of the second counting circuit 2 is 3, the COM selection signal COM3_SEL is high, thus realizing the selection of the corresponding COM port.

[0058] Based on the above description and inspired by this utility model, those skilled in the art can make various changes and modifications without departing from the technical concept of this utility model. The technical scope of this utility model is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. An LCD port mapping circuit, characterized in that, It includes a first counting circuit, a second counting circuit, a reset circuit, a counting stop circuit, a D flip-flop DFF10, and a second decoding circuit; The first counting circuit counts the input clock signal CLK2N. The reset circuit generates a reset signal input to the first and second counting circuits based on the input duty cycle control signal and the count value of the first counting circuit. The reset signal is used to reset the count values ​​of the first and second counting circuits to zero. The counting stop circuit inputs a counting stop signal to the second counting circuit based on the input COM enable signal and the count value of the second counting circuit. The counting stop signal is used to pause the counting of the second counting circuit. The D input terminal of the D flip-flop DFF10 is electrically connected to the counting output terminal of the second counting circuit. The clock input terminal of the D flip-flop DFF10 is used to input the clock signal CLK2. The Q output terminal of the D flip-flop DFF10 is electrically connected to the second decoding circuit. The second decoding circuit decodes the signal at the Q output terminal of the D flip-flop DFF10 and outputs a COM selection signal. The COM selection signal is used to select the COM port of the MCU for LCD display.

2. The LCD port mapping circuit according to claim 1, characterized in that, The clock signals CLK2N and CLK2 are two opposite clock signals.

3. The LCD port mapping circuit according to claim 2, characterized in that, It also includes a clock signal generation circuit, which includes a frequency divider and an inverter INV1. The input terminal of the frequency divider is used to input the system clock CLK1, and the output terminal of the frequency divider is used to output the clock signal CLK2. The input terminal of the inverter INV1 is electrically connected to the output terminal of the frequency divider, and the output terminal of the inverter INV1 is used to output the clock signal CLK2N.

4. The LCD port mapping circuit according to claim 3, characterized in that, The first counting circuit includes T flip-flops TFF1, T flip-flops TFF2 and T flip-flops TFF3; the clock input terminal of T flip-flops TFF1 is used to input the clock signal CLK2N, the QN output terminal of T flip-flops TFF1 is electrically connected to the clock input terminal of T flip-flops TFF2, and the QN output terminal of T flip-flops TFF2 is electrically connected to the clock input terminal of T flip-flops TFF3. The Q outputs of TFF1, TFF2, and TFF3 are the counting terminals of the first counting circuit.

5. An LCD port mapping circuit according to claim 4, characterized in that, The reset circuit includes AND gates AND1-AND4 and NOR gate NOR1. One input of AND gate AND1 is electrically connected to the Q output of T flip-flop TFF3, and the other input of AND gate AND1 is used to input the quarter-duty cycle control signal 1P4. Two of the three inputs of AND gate AND2 are electrically connected to the Q outputs of T flip-flop TFF2 and T flip-flop TFF1, respectively. The remaining input of AND gate AND2 is used to input the one-third-duty cycle control signal 1P3. One input of AND gate AND3 is electrically connected to the Q output of T flip-flop TFF2, and the other input is used to input the half-duty cycle control signal 1P2. The outputs of AND1, AND2, and AND3 are electrically connected to the three inputs of NOR1. The output of NOR1 is electrically connected to one input of AND4. The other input of AND4 is used to input the enable signal EN. The output of AND4 is electrically connected to the reset terminals of TFF1, TFF2, and TFF3, respectively.

6. An LCD port mapping circuit according to claim 5, characterized in that, The second counting circuit includes T flip-flop TFF10, T flip-flop TFF11, AND gate AND11, and AND gate AND12; The two input terminals of the AND gate AND11 are used to input the counting stop signal and the system clock CLK1, respectively. The output terminal of the AND gate AND11 is electrically connected to the clock terminal of the TFF flip-flop TFF10, and the QN output terminal of the TFF flip-flop TFF10 is electrically connected to the clock terminal of the TFF flip-flop TFF11. The two input terminals of the AND gate AND12 are used to input the enable signal EN and the reset signal, respectively, and the output terminal of the AND gate AND11 is electrically connected to the reset terminal of the T flip-flop TFF10 and the reset terminal of the T flip-flop TFF11, respectively. The Q output terminals of the TFF flip-flop TFF10 and TFF flip-flop TFF11 are the counting terminals of the second counting circuit.

7. An LCD port mapping circuit according to claim 6, characterized in that, The counting stop circuit includes a first decoding circuit, NAND gates NAND10 to NAND14, an inverter INV10, a D flip-flop DFF11, a pulse generation circuit, and an AND gate AND10; The first decoding circuit decodes the count value of the second counting circuit and outputs decoding signals COM0S to COM3S; one input terminal of NAND gate NAND10, one input terminal of NAND gate NAND11, one input terminal of NAND gate NAND12, and one input terminal of NAND gate NAND13 are respectively used to input decoding signals COM0S, COM1S, COM2S, and COM3S; the other input terminal of NAND gate NAND10, the other input terminal of NAND gate NAND11, the other input terminal of NAND gate NAND12, and the other input terminal of NAND gate NAND13 are respectively used to input enable signals COM0EN, COM1EN, COM2EN, and COM3EN; the output ... the other input terminal of NAND gate NAND13, the other input terminal of NAND gate NAND14, the other input terminal of NAND gate NAND15, the other input terminal of NAND gate NAND16, the other input terminal of NAND gate NAND17, the other input terminal of NAND gate NAND18, the other input terminal of NAND gate NAND19, the other input terminal of NAND gate NAND10, the other input terminal of NAND gate NAND19, the other input terminal of NAND gate NAND19, The output of NAND gate 1, the output of NAND gate 12, the output of NAND gate 13, and the four inputs of NAND gate 14 are electrically connected. The output of NAND gate 14 is electrically connected to the D input of D flip-flop DFF11. The clock input of D flip-flop DFF11 is electrically connected to the output of inverter INV10. The input of inverter INV10 is used to input the system clock CLK1. The QN output of D flip-flop DFF11 outputs the counting stop signal. The reset input of D flip-flop DFF11 is electrically connected to the output of AND gate AND10. One input of AND gate AND10 is used to input the enable signal EN. The other input of AND gate AND10 is electrically connected to the output of the pulse generator circuit. The input of the pulse generator circuit is used to input the clock signal CLK2N. A low-level pulse is generated when the clock signal CLK2N changes from low to high.

8. An LCD port mapping circuit according to claim 7, characterized in that, The first decoding circuit is a 2-to-4 decoding circuit.

9. An LCD port mapping circuit according to claim 7, characterized in that, The second decoding circuit is a 2-to-4 decoding circuit.

10. An LCD port mapping circuit according to claim 3, characterized in that, The frequency of the clock signal CLK2 output by the frequency divider is one-quarter of the frequency of the system clock CLK1.

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