Chip placement detection module and chip testing device

Abstract

This application discloses a chip placement position detection module and a chip testing device. The chip placement position detection module is disposed within the chip testing device and is used to detect the placement status of the chip under test (DUT) on the test mounting base within the chip testing device. The test mounting base includes multiple first pins, and the DUT includes second pins corresponding to each of the first pins. The chip placement position detection module includes an indicator module and a signal detection circuit with multiple input terminals. The signal detection circuit is used to identify the placement status of the DUT on the test mounting base based on the electrical signals corresponding to each first pin and outputs an identification signal. The indicator module is used to output indicator information characterizing the placement status based on the identification signal. This application can perform real-time detection of the placement status of the DUT on the test mounting base. The corresponding detection structure and process are relatively simple, which can reduce the corresponding detection cost and also help improve the testing efficiency and reliability of the subsequent DUT testing.

Description

Technical Field

[0001] This application relates to the field of memory chip testing technology, specifically to a chip placement detection module and a chip testing device. Background Technology

[0002] In the semiconductor memory manufacturing process, embedded memory chips such as UFS (Universal Flash Storage) and eMMC (embedded Multimedia Card) often require rigorous electrical performance and burn-in tests before leaving the factory. During testing, the sample under test must be precisely inserted into the corresponding socket on the test board, and a stable electrical connection must be established by the socket's pogo pins contacting the sample's pins to achieve chip testing. However, in actual testing, poor contact often leads to test failures due to sample misalignment, tilting, or uneven contact pressure. Therefore, there is an urgent need for a testing device capable of detecting the placement position of the memory chip on the socket. Utility Model Content

[0003] In view of this, this application provides a chip placement detection module and a chip testing device to detect the placement status of memory chips on a socket.

[0004] This application provides a chip placement position detection module, which is disposed in a chip testing device and is used to detect the placement status of the chip under test in the test mounting bracket of the chip testing device; the test mounting bracket includes a plurality of first pins, and the chip under test includes second pins corresponding to each of the first pins respectively;

[0005] The chip placement detection module includes an indicator module and a signal detection circuit with multiple input terminals; each input terminal of the signal detection circuit is connected to a first pin, and the output terminal is connected to the indicator module.

[0006] The signal detection circuit is used to identify the placement status of the chip under test in the test mounting bracket based on the electrical signals corresponding to each of the first pins, and output an identification signal.

[0007] The indicator module is used to output indicator information characterizing the placement status based on the identification signal.

[0008] Optionally, the signal detection circuit includes an OR operation circuit with multiple OR operation input terminals and resistors corresponding to each OR operation input terminal; each OR operation input terminal of the OR operation circuit serves as an input terminal of the signal detection circuit, connected to a first terminal of a resistor and a first pin respectively, and its output terminal serves as an output terminal of the signal detection circuit, connected to the indicator module; the second terminals of each resistor are respectively used to connect to the preset voltage; the OR operation circuit is used to output a first identification signal when each first pin is in good contact with its corresponding second pin, and to output a second identification signal when at least one first pin is in abnormal contact with its corresponding second pin; the first identification signal is used to instruct the indicator module to output first indication information indicating that the chip under test is placed accurately, and the second identification signal is used to instruct the indicator module to output second indication information indicating that the chip under test is placed abnormally.

[0009] Optionally, the OR operation circuit includes a first OR gate; each input terminal of the first OR gate serves as an OR operation input terminal, and the output terminal serves as the output terminal of the OR operation circuit.

[0010] Optionally, the test mounting base includes five first pins; the OR operation circuit includes five first pins corresponding to OR operation input terminals respectively.

[0011] Optionally, the OR operation circuit includes a second OR gate and a plurality of third OR gates; the input terminal of each of the third OR gates serves as an OR operation input terminal, and the output terminal is connected to one input terminal of the second OR gate; the output terminal of the second OR gate serves as the output terminal of the OR operation circuit.

[0012] Optionally, the indicating module includes at least one of an indicator light, a buzzer, and an alarm.

[0013] Optionally, the chip under test further includes a third pin connected to all the second pins; the test mounting bracket includes a fourth pin corresponding to the third pin, and the fourth pin is connected to ground.

[0014] Optionally, the indicator module includes a first indicator light; the first identification signal is used to illuminate the first indicator light; and the second identification signal is used to extinguish the first indicator light.

[0015] Optionally, the OR operation circuit includes a plurality of fourth OR gates, each of which includes at least two input terminals; the indicator module includes a plurality of second indicator lights, each of the fourth OR gates corresponding to one of the second indicator lights; the input terminal of each of the fourth OR gates serves as an OR operation input terminal, and the output terminal is connected to the output terminal of the corresponding second indicator light; the input terminal of each of the second indicator lights is connected to a preset voltage.

[0016] This application also provides a chip testing device, which includes a test mounting base and any of the above-mentioned chip placement position detection modules.

[0017] In the chip placement detection module and chip testing device described in this application, the signal detection circuit can identify the placement status of the chip under test in the test mounting bracket based on the electrical signals corresponding to each first pin, and output an identification signal. The indicator module can output indicator information to characterize the placement status based on the identification signal, so as to detect the placement status of the chip under test in the test mounting bracket in real time. The corresponding detection structure and detection process are relatively simple, which can reduce the corresponding detection cost and also help improve the testing efficiency and reliability of the chip under test. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a chip placement position detection module structure according to an embodiment of this application;

[0020] Figure 2 This is a schematic diagram of a chip placement position detection module structure according to an embodiment of this application;

[0021] Figure 3 This is a schematic diagram of a chip placement position detection module structure according to an embodiment of this application;

[0022] Figure 4 This is a schematic diagram of a chip placement position detection module structure according to an embodiment of this application;

[0023] Figure 5 This is a schematic diagram illustrating the application of a chip placement position detection module in one embodiment of this application;

[0024] Figure 6 This is a schematic representation of the truth value of the first OR gate in one embodiment of this application;

[0025] Figure 7 This is a schematic diagram of a chip placement position detection module structure according to an embodiment of this application;

[0026] Figure 8 This is a schematic diagram of a chip placement position detection module structure according to an embodiment of this application. Detailed Implementation

[0027] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0028] This application provides a chip placement position detection module, which is disposed within a chip testing device and is used to detect the placement status of a chip under test (DUT) on a test mounting base within the chip testing device. The test mounting base includes a plurality of first pins, and the DUT includes second pins corresponding to each of the first pins. When the DUT is placed on the test mounting base, if each first pin makes good contact with its corresponding second pin, it indicates that the DUT is accurately placed on the test mounting base; if at least one first pin makes abnormal contact with its corresponding second pin, it indicates that the DUT is improperly or incorrectly placed on the test mounting base.

[0029] refer to Figure 1 As shown, the chip placement detection module includes an indicator module 100 and a signal detection circuit 200 with multiple input terminals; each input terminal of the signal detection circuit is connected to a first pin, and the output terminal is connected to the indicator module.

[0030] The signal detection circuit 200 is used to identify the placement status of the chip under test in the test mounting bracket based on the electrical signals corresponding to each of the first pins, and outputs an identification signal. Optionally, the electrical signals corresponding to the first pins may include relatively simple signals such as high-level signals and / or low-level signals; various signals can characterize a contact state of the corresponding first and second pins. For example, a low-level signal corresponding to the first pin can indicate good contact between the corresponding first and second pins, while a low-level signal corresponding to the first pin can indicate abnormal contact between the corresponding first and second pins, and so on. Optionally, the signal detection circuit 200 can be implemented using components such as a signal detection chip and / or related logic operation devices.

[0031] The indicator module 100 is used to output indicator information to characterize the placement status according to the identification signal; wherein the indicator information includes at least information to characterize the placement abnormality of the chip under test, so that when the identification signal indicates that the chip under test is placed abnormally on the test mounting bracket, the indicator module 100 outputs information to characterize the placement abnormality of the chip under test and provides timely abnormality prompts.

[0032] Optionally, the indicator module 100 includes at least one of an indicator light, a buzzer, and an alarm. Each of the above indicator modules 100 can output corresponding indication information to indicate the corresponding placement status; for example, an indicator light can indicate that the chip under test is placed correctly when it is lit, and that the chip under test is placed incorrectly when it is off; a buzzer can indicate that the chip under test is placed incorrectly through a beeping sound; and an alarm can indicate that the chip under test is placed incorrectly through an alarm message.

[0033] In the chip placement detection module described above, the signal detection circuit 200 can identify the placement status of the chip under test in the test mounting bracket based on the electrical signals corresponding to each first pin, and output an identification signal. The indicator module 100 can output indicator information to characterize the placement status based on the identification signal, so as to detect the placement status of the chip under test in the test mounting bracket in real time. The detection structure and process are relatively simple, which can reduce the corresponding detection cost and also help improve the testing efficiency and reliability of the chip under test in the future.

[0034] In some embodiments, reference Figure 2 As shown, the signal detection circuit 200 includes an OR operation circuit 210 with multiple OR operation input terminals and resistors 220 corresponding to each of the OR operation input terminals. Each OR operation input terminal of the OR operation circuit 210 serves as an input terminal of the signal detection circuit 200, connected to a first terminal and a first pin of a resistor 220, respectively. The output terminal serves as the output terminal of the signal detection circuit 200, connected to the indicator module 100. The second terminal of each resistor 220 is used to connect a preset voltage.

[0035] The arithmetic circuit 210 is configured to output a first identification signal when all first pins are in good contact with their corresponding second pins, and to output a second identification signal when at least one first pin is in abnormal contact with its corresponding second pin. The first identification signal is used to instruct the corresponding instruction module 100 to output first indication information indicating that the chip under test is placed accurately; the second identification signal is used to instruct the corresponding instruction module 100 to output second indication information indicating that the chip under test is placed abnormally.

[0036] This embodiment uses an OR operation circuit 210 to implement the detection function of the signal detection circuit 200, which simplifies the circuit structure and detection process of the signal detection circuit 200, thereby reducing implementation costs and improving detection efficiency.

[0037] In some examples, the chip under test (DUT) also includes a third pin connected to all the second pins; the test mount includes a fourth pin corresponding to the third pin, which is connected to ground. Here, the first pin on the test mount is not connected to the fourth pin. Therefore, only when the DUT is correctly positioned on the test mount will each of the second pins from the DUT be connected to the fourth pin on the test mount, i.e., ground. At this time, the first pin on the test mount will have a ground signal (such as a low-level signal). Thus, it can be concluded that when all electrical signals corresponding to the first pin are ground signals, the DUT is correctly positioned on the test mount; when at least one electrical signal corresponding to the first pin is not a ground signal, the DUT is improperly positioned on the test mount.

[0038] Optionally, refer to Figure 3 As shown, the indicator module 100 includes a first indicator light 110. Optionally, the first indicator light 110 can be implemented using a light-emitting structure such as an LED.

[0039] Specifically, the first identification signal is used to illuminate the first indicator light 110, indicating that the chip under test (DUT) is correctly placed on the test mount; the second identification signal is used to extinguish the first indicator light 110, indicating that the DUT is improperly placed on the test mount. Figure 3 As shown, the input terminal of the first indicator light 110 can be connected to a preset voltage, and the output terminal is connected to the output terminal of the OR operation circuit 210. When the chip under test is placed accurately on the test mounting base, the electrical signals corresponding to the first pin are all low-level signals (i.e., ground signals), or all OR operation input terminals of the operation circuit 210 are connected to low-level signals, and the output is a low-level signal. At this time, the output terminal of the first indicator light 110 is a low-level signal, the input terminal is a preset voltage, and there is a voltage difference between the input terminal and the output terminal of the first indicator light 110, which is lit up. When the chip under test is placed abnormally on the test mounting base, the electrical signal corresponding to at least one first pin is not a low-level signal (i.e., a high-level signal), or the output of the operation circuit 210 is a high-level signal. At this time, both the input terminal and the output terminal of the first indicator light 110 are high-level signals, and the first indicator light 110 is turned off.

[0040] In some examples, reference Figure 4 As shown, the OR operation circuit 210 includes a first OR gate 211; each input terminal of the first OR gate 211 serves as an OR operation input terminal, and is simultaneously connected to the first terminal of a resistor 220 and a first pin. The output terminal serves as the output terminal of the OR operation circuit 210 and is connected to the output terminal of the first indicator light 110. This embodiment uses the first OR gate 211 to implement the OR operation function, which can further simplify the corresponding circuit structure.

[0041] Optionally, the test mounting bracket includes five first pins; correspondingly, the chip under test includes second pins corresponding to the five first pins, for example, referencing... Figure 5 As shown, the chip under test is rectangular, with five second pins distributed in the four corners and the middle area of ​​the chip under test, so that the contact condition between the second pins and the corresponding first pins can accurately characterize the placement of the chip under test on the test mount.

[0042] Furthermore, the OR operation circuit includes five OR operation input terminals corresponding to five first pins, so that each of the five OR operation input terminals is connected to an electrical signal corresponding to a first pin. Specifically, the first indicator light 110 includes an LED. Figure 5 The truth table of the first OR gate 211 shown can be referenced. Figure 6 As shown, Figure 6 In the diagram, A, B, C, D, and E represent the five OR operation inputs of the OR operation circuit, and F represents the output of the OR operation circuit. The output is 0 only when all the OR operation inputs are 0. Therefore, only when the five second pins of the chip under test are in good contact with their corresponding first pins will all the OR operation inputs be pulled low, the first OR gate 211 output a low-level signal, and a voltage difference will be formed across the LED, causing it to light up. When any second pin is not in good contact with its corresponding first pin, the corresponding OR operation input remains high, the first OR gate 211 outputs a high-level signal, the voltage difference across the LED is insufficient, and the LED turns off.

[0043] In some examples, reference Figure 7 As shown, the OR operation circuit 210 includes a second OR gate 212 and a third OR gate 213. Each input terminal of the third OR gate 213 serves as an OR operation input terminal, connected to the first terminal and a first pin of a resistor 220. The output terminal is connected to one input terminal of the second OR gate 212. The output terminal of the second OR gate 212 serves as the output terminal of the OR operation circuit 210 and is connected to the output terminal of the first indicator light 110. This example uses two levels of OR gates to implement the OR operation function, where multiple third OR gates 213 serve as the first-level OR gates, and the second OR gate 212 serves as the second-level OR gates, allowing for more flexible configuration of features such as the number of OR operation input terminals of the OR operation circuit 210.

[0044] In some examples, reference Figure 8As shown, the OR operation circuit 210 includes multiple fourth OR gates 214, and the indicator module 100 includes second indicator lights 120 corresponding to each fourth OR gate 214. Each fourth OR gate 214 has an input terminal serving as an OR operation input terminal, connected to the first terminal of a resistor 220 and a first pin (i.e., each fourth OR gate 214 corresponds to a set of first pins). Its output terminal is connected to the output terminal of a second indicator light 120. Each second indicator light 120 has an input terminal connected to a preset voltage. If all the first pins connected to a certain fourth OR gate 214 have good contact with their corresponding second pins, the corresponding second indicator light 120 illuminates. If at least one of the first pins connected to a certain fourth OR gate 214 has abnormal contact with its corresponding second pin, the corresponding second indicator light 120 turns off. This example uses multiple second indicator lights 120 to detect the contact status of a corresponding set of first pins. In addition to real-time detection of the placement of the chip under test on the test mount, it can also locate pins with abnormal contact.

[0045] In the chip placement detection module described above, the signal detection circuit 200 can identify the placement status of the chip under test in the test mounting bracket based on the electrical signals corresponding to each first pin, and output an identification signal. The indicator module 100 can output indicator information to characterize the placement status based on the identification signal, so as to detect the placement status of the chip under test in the test mounting bracket in real time. The corresponding detection structure and detection process are relatively simple, which can reduce the corresponding detection cost and also help improve the testing efficiency and reliability of the chip under test in the future.

[0046] A second aspect of this application provides a chip testing apparatus, which includes a test mounting base and a chip placement position detection module as described in any of the above embodiments.

[0047] Optionally, such as Figure 5 As shown, the test mounting base includes 5 first pins.

[0048] Optionally, multiple first pins are distributed in the central area and four corner areas of the test mount, so that the contact condition between the first pin and the corresponding second pin can accurately characterize the placement of the chip under test on the test mount.

[0049] The chip testing apparatus described above includes the chip placement position detection module described in any of the above embodiments, and has all the beneficial effects of the chip placement position detection module described in any of the above embodiments, which will not be repeated here.

[0050] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0051] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0052] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0053] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A chip placement position detection module, characterized in that, The chip placement detection module is located inside the chip testing device and is used to detect the placement status of the chip under test in the test mounting bracket of the chip testing device; the test mounting bracket includes multiple first pins, and the chip under test includes second pins corresponding to each of the first pins; The chip placement detection module includes an indicator module and a signal detection circuit with multiple input terminals; each input terminal of the signal detection circuit is connected to a first pin, and the output terminal is connected to the indicator module. The signal detection circuit is used to identify the placement status of the chip under test in the test mounting bracket based on the electrical signals corresponding to each of the first pins, and output an identification signal. The indicator module is used to output indicator information characterizing the placement status based on the identification signal.

2. The chip placement position detection module according to claim 1, characterized in that, The signal detection circuit includes an OR operation circuit with multiple OR operation input terminals and resistors corresponding to each of the OR operation input terminals; Each input terminal of the OR operation circuit serves as an input terminal of the signal detection circuit, and is respectively connected to the first terminal of a resistor and the first pin. The output terminal serves as the output terminal of the signal detection circuit and is connected to the indicator module. The second terminal of each resistor is respectively used to connect to a preset voltage. The OR operation circuit is used to output a first identification signal when each of the first pins is in good contact with the corresponding second pin, and to output a second identification signal when at least one of the first pins is in abnormal contact with the corresponding second pin; the first identification signal is used to instruct the indication module to output a first indication information to characterize the accurate placement of the chip under test, and the second identification signal is used to instruct the indication module to output a second indication information to characterize the abnormal placement of the chip under test.

3. The chip placement position detection module according to claim 2, characterized in that, The OR operation circuit includes a first OR gate; each input terminal of the first OR gate serves as an OR operation input terminal, and the output terminal serves as the output terminal of the OR operation circuit.

4. The chip placement position detection module according to claim 2, characterized in that, The test mounting bracket includes 5 first pins; The OR operation circuit includes five first pins, each corresponding to an OR operation input terminal.

5. The chip placement position detection module according to claim 2, characterized in that, The OR operation circuit includes a second OR gate and multiple third OR gates; Each of the input terminals of the third OR gate serves as an OR operation input terminal, and its output terminal is connected to one input terminal of the second OR gate; the output terminal of the second OR gate serves as the output terminal of the OR operation circuit.

6. The chip placement position detection module according to claim 1, characterized in that, The indicator module includes at least one of an indicator light, a buzzer, and an alarm.

7. The chip placement position detection module according to claim 2, characterized in that, The chip under test also includes a third pin connected to all the second pins; the test mounting base includes a fourth pin corresponding to the third pin, and the fourth pin is connected to ground.

8. The chip placement position detection module according to claim 7, characterized in that, The indicator module includes a first indicator light; The first identification signal is used to turn on the first indicator light; the second identification signal is used to turn off the first indicator light.

9. The chip placement position detection module according to claim 2, characterized in that, The OR operation circuit includes a plurality of fourth OR gates, each of which includes at least two input terminals; the indicator module includes a plurality of second indicator lights, each of which corresponds to one second indicator light. Each of the fourth OR gates has an input terminal as an OR operation input terminal, and its output terminal is connected to the output terminal of the corresponding second indicator light; the input terminals of each of the second indicator lights are connected to a preset voltage.

10. A chip testing device, characterized in that, The chip testing device includes a test mounting base and a chip placement position detection module as described in any one of claims 1 to 9.

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