A synchronous rectification control device and a flyback power charging system

Abstract

This utility model relates to a synchronous rectification control device and a flyback power supply charging system, including a drive module and a conduction control module connected to the drive module. The conduction control module can control the secondary-side MOSFET to ensure conduction in the freewheeling state and deconduct it in the resonant state. This utility model determines whether the secondary-side MOSFET is in the freewheeling or resonant state by detecting fluctuations in the MOSFET. In the freewheeling state, the secondary-side MOSFET is turned on when its drain voltage is lower than the conduction threshold voltage. In the resonant state, the secondary-side MOSFET is not turned on even if its drain voltage is lower than the conduction threshold voltage, thus avoiding system failure due to incorrect conduction in the freewheeling state or system failure due to incorrect conduction in the resonant state.

Description

Technical Field

[0001] This utility model relates to the field of flyback power supply technology, and in particular to a synchronous rectification control device and a flyback power supply charging system. Background Technology

[0002] Flyback power supply topology, as a common AC-DC power supply solution, is widely used in charging solutions for various electronic products. For example... Figure 1 As shown, in a traditional flyback power supply system, the primary-side controller controls the switching of the primary-side MOSFET (Metal Oxide Semiconductor Field Effect Transistor), while the secondary side uses a Schottky diode for freewheeling output. When the primary-side MOSFET is turned on, the transformer stores energy; when the primary-side MOSFET is turned off, the secondary-side Schottky diode conducts to freewheel, transferring the energy stored in the transformer to the load.

[0003] With the widespread adoption of fast charging technology and the increasing power consumption demands of electronic devices, the power ratings of flyback power supplies are constantly rising. This means that the current drawn by flyback power supplies is increasing. Because Schottky diodes have a relatively large forward voltage drop (>0.4V), as the current increases, the losses during freewheeling become increasingly significant, leading to lower system efficiency. Therefore, more and more flyback power supplies are using secondary-side MOSFETs to replace traditional Schottky diodes. MOSFETs have a significantly lower forward voltage (typically around 0.1V) than Schottky diodes, resulting in significantly reduced conduction losses and a substantial improvement in efficiency.

[0004] A flyback power supply using a secondary-side MOSFET is employed, with the switching on and off of the secondary-side MOSFET controlled by a synchronous rectifier controller. The corresponding system diagram is shown below. Figure 2 As shown in the diagram. A traditional synchronous rectifier controller structure diagram is shown below. Figure 8 As shown.

[0005] The flyback power supply system based on the synchronous rectifier controller has three main operating modes: CCM mode (Continuous Conduction Mode), QR mode (QuasiResonant Mode), and DCM mode (Discontinuous Conduction Mode). Figures 3 to 5 These are schematic diagrams of key system waveforms under three operating modes.

[0006] In a flyback system, the primary-side controller chip and the secondary-side synchronous rectifier controller chip need to alternately turn their respective MOSFETs on and off to transfer energy. However, due to transformer isolation, direct signal transmission between them is impossible. The secondary-side synchronous rectifier controller typically determines the switching of the secondary MOSFET by detecting its own secondary MOSFET drain voltage VD_SR signal. A common method is to set a turn-on threshold voltage; when VD_SR falls below this threshold voltage, the synchronous rectifier controller will turn on the secondary MOSFET. This turn-on threshold voltage is typically set between -0.1V and -0.5V.

[0007] In CCM mode, such as Figure 3 As shown, when the primary MOSFET is turned on, the drain voltage VD_SR of the secondary MOSFET is high. After the primary MOSFET is turned off, according to the working principle of the transformer, the secondary side will freewheel. At this time, the secondary current Id_SR flows through the body diode of the secondary MOSFET, and the VD_SR voltage is approximately -0.7V, which is lower than the turn-on threshold voltage. The synchronous rectifier controller will then turn on the secondary MOSFET.

[0008] In QR mode and DCM mode, such as Figure 4 and Figure 5 As shown, when the system is in resonance (both primary and secondary sides are off), VD_SR is a sinusoidal waveform, and the valley voltage of the oscillation is higher than the turn-on threshold voltage. Therefore, the secondary MOSFET will not turn on. When the system enters the primary MOSFET turn-on state, VD_SR is high, and the secondary MOSFET will not turn on. When the primary MOSFET is turned off, the secondary side will freewheel. At this time, the secondary current Id_SR flows through the body diode of the secondary MOSFET, and the VD_SR voltage is approximately -0.7V, which is lower than the turn-on threshold voltage. The synchronous rectifier controller will then turn on the secondary MOSFET.

[0009] However, in actual flyback power supply systems, due to the influence of external components, the waveform of VD_SR will not be consistent with the ideal waveform mentioned above during the resonance period.

[0010] like Figure 6 As shown, the VD_SR voltage in the actual system can reach a negative voltage, even below the turn-on threshold voltage, during the resonance phase. At this time, the synchronous rectifier controller will incorrectly turn on the secondary MOSFET. This will result in a loss of system efficiency. More seriously, due to the incorrect turn-on of the secondary MOSFET during resonance, the resonant waveform will be further deteriorated, such as... Figure 7As shown, the amplitude of the resonant waveform increases due to the erroneous conduction of the secondary MOSFET. The synchronous rectifier controller will continuously detect that the VD_SR voltage is lower than the conduction threshold voltage. The repeated erroneous conduction of the secondary MOSFET causes the primary and secondary MOSFETs to conduct simultaneously, resulting in excessive instantaneous energy and causing the machine to explode.

[0011] Therefore, there is an urgent need to design a synchronous rectification control device and flyback power charging system that can detect the drain voltage fluctuation state of the secondary MOSFET in real time to prevent it from failing to conduct in freewheeling state and conducting incorrectly in resonant state. Utility Model Content

[0012] The technical problem to be solved by this utility model is to provide a synchronous rectification control device and a flyback power charging system, which can ensure the conduction of the secondary side field-effect transistor when the system is in freewheeling state.

[0013] To solve the above-mentioned technical problems, this utility model provides a synchronous rectification control device, including a drive module and a conduction control module connected to the drive module;

[0014] The drive module receives the conduction signal output by the conduction control module and generates a conduction drive signal that can control the conduction of the secondary-side field-effect transistor of the flyback power charging system.

[0015] The conduction control module includes a state judgment circuit and a conduction determination circuit;

[0016] The state determination circuit detects the rise time Tr of the drain voltage of the secondary-side field-effect transistor when it changes from a preset first reference voltage VR1 to a preset second reference voltage VR2, and the fall time Tf when it changes from a preset second reference voltage VR2 to a preset first reference voltage VR1. When the drain voltage of the secondary-side field-effect transistor drops to less than the first reference voltage VR1, it determines that the current fall time Tf is less than N times the rise time Tr, and then outputs a freewheeling state signal; and / or, it determines that the current fall time Tf is greater than or equal to N times the rise time Tr, and then outputs a resonance state signal; the first reference voltage VR1 is less than the second reference voltage VR2; N is any positive integer or any positive fraction; the rise time Tr is equivalent to the rise voltage Vtr of the drain voltage of the secondary-side field-effect transistor during the period from greater than the first reference voltage VR1 to greater than the second reference voltage VR2; the fall time Tf is equivalent to the drop voltage Vtf of the drain voltage of the secondary-side field-effect transistor during the period from less than the second reference voltage VR2 to less than the first reference voltage VR1.

[0017] The conduction determination circuit generates and outputs the conduction signal when it detects that the drain voltage of the secondary-side field-effect transistor is lower than a preset conduction threshold voltage and the freewheeling state signal; and / or generates and outputs the anti-conduction signal when it detects a resonance state signal.

[0018] Furthermore, the state determination circuit includes a comparison unit, a rising period detection circuit, a falling period detection circuit, and an output unit;

[0019] The comparison unit compares the current drain voltage of the secondary-side field-effect transistor with a preset first reference voltage VR1 and a second reference voltage VR2. If the current drain voltage of the secondary-side field-effect transistor is greater than the first reference voltage VR1, a first voltage rise signal is output; otherwise, a first voltage fall signal is output. If the current drain voltage of the secondary-side field-effect transistor is greater than the second reference voltage VR2, a second voltage rise signal is output; otherwise, a second voltage fall signal is output.

[0020] The rise-period detection circuit generates a rise voltage Vtr for detecting the rise time Tr based on the first voltage rise signal, the first voltage fall signal, the second voltage rise signal, and the second voltage fall signal.

[0021] The detection circuit during the descent period generates a reduced voltage Vtf for detecting the descent time Tf based on the first voltage rise signal, the first voltage fall signal, the second voltage rise signal, and the second voltage fall signal.

[0022] When the first voltage rise signal changes to the first voltage fall signal, the output unit outputs the freewheeling state signal if the depreciation voltage Vtf is less than the rise voltage Vtr; and / or, if the depreciation voltage Vtf is greater than the rise voltage Vtr, the output unit outputs the resonance state signal.

[0023] Furthermore, the rise-period detection circuit includes a rise state latch trigger unit and a rise voltage generation unit;

[0024] The rising state latch trigger unit outputs a first trigger signal when it detects the first voltage rise signal in sequence; outputs a first hold signal when it detects the second voltage rise signal; and outputs a second trigger signal when it detects the first voltage fall signal.

[0025] The voltage boosting generation unit generates a voltage boosting voltage Vtr that gradually increases in value according to the first trigger signal; stops increasing the voltage boosting voltage Vtr and holds it at the highest value according to the first hold signal; and generates a voltage boosting voltage Vtr that gradually decreases from the highest value according to the second trigger signal.

[0026] The descent detection circuit includes a descent state latch trigger unit and a decrement voltage generation unit;

[0027] The falling state latch trigger unit outputs a third trigger signal when it detects the second voltage drop signal in sequence; outputs a second hold signal when it detects the first voltage drop signal; and outputs a fourth trigger signal when it detects the second voltage rise signal.

[0028] The degraded voltage generation unit generates a gradually increasing degraded voltage Vtf according to the third trigger signal; stops increasing the degraded voltage Vtf and maintains it at the highest value according to the second hold signal; and generates a gradually decreasing degraded voltage Vtf from the highest value according to the fourth trigger signal.

[0029] Furthermore, the comparison unit includes a first comparator CMP1 and a second comparator CMP2;

[0030] The first comparator CMP1 detects whether the drain voltage of the current side field-effect transistor is greater than the first reference voltage VR1. If it is, it outputs the first voltage rise signal; otherwise, it outputs the first voltage fall signal.

[0031] The second comparator CMP2 detects whether the drain voltage of the current secondary-side field-effect transistor is greater than the second reference voltage VR2. If it is, it outputs the second voltage rise signal; otherwise, it outputs the second voltage fall signal.

[0032] The voltage value of the first reference voltage VR1 is less than the voltage value of the second reference voltage VR2.

[0033] Furthermore, the rising state latch trigger unit includes a first latch LAT1 connected to the outputs of the first comparator CMP1 and the second comparator CMP2, and a NOT gate NOT1 connected to the output of the first comparator CMP1.

[0034] The voltage boosting unit includes a current source Ibr connected to the power supply VDD, a first switch S1 connected in series with the current source Ibr and controlled by the first latch LAT1, and a capacitor Cr connected in series with the first switch S1 and grounded at the other end, and a second switch S2 connected in parallel with the capacitor Cr and controlled by the NOT gate NOT1.

[0035] The Clk terminal of the first latch LAT1 is connected to the output terminal of the first comparator CMP1, and the Reset terminal is connected to the output terminal of the second comparator CMP2;

[0036] The falling state latch triggering unit includes NOT2 connected to the output of the second comparator CMP2 and LAT2 connected to the output of NOT1 and NOT2.

[0037] The Clk terminal of the second latch LAT2 is connected to the output terminal of the NOT gate NOT2, and the Reset terminal is connected to the output terminal of the NOT gate NOT1;

[0038] The degraded voltage generation unit includes a current source Ibf connected to the power supply VDD, a third switch S3 connected in series with the current source Ibf and controlled by the second latch LAT2, a capacitor Cf connected in series with the third switch S3 and grounded at the other end, and a fourth switch S4 connected in parallel with the capacitor Cf and controlled by the second comparator CMP2.

[0039] Furthermore, the output unit includes a third comparator CMP3 connected to the capacitor Cr and the capacitor Cf, a third latch LAT3 connected to the output of the third comparator CMP3, and a delay unit BUF connected to the third latch LAT3.

[0040] The non-inverting input of the third comparator CMP3 is connected to the capacitor Cr, the first inverting input is connected to the capacitor Cf, the second inverting input is connected to the reference voltage Vref, and the output is connected to the third latch LAT3.

[0041] The Clk terminal of the third latch LAT3 is connected to the output terminal of the NOT gate NOT1, the D terminal is connected to the output terminal of the third comparator CMP3, the Reset terminal is connected to the output terminal of the delay unit BUF, and the output terminal outputs the freewheeling state signal and / or the resonant state signal.

[0042] The input of the delay unit BUF is connected to the conduction signal, and the output is connected to the Reset terminal of the third latch LAT3.

[0043] Furthermore, the conduction determination circuit includes a comparator CMP connected to the drain of the secondary-side field-effect transistor and an AND gate connected to the output of the comparator CMP and the output of the state determination circuit;

[0044] The comparator CMP determines whether the drain voltage of the current secondary-side field-effect transistor is lower than the conduction threshold voltage Von. If so, it outputs a quasi-conduction signal.

[0045] The AND gate outputs the conduction signal after receiving the quasi-conductivity signal and the freewheeling state signal; and / or outputs the anti-conductivity signal after receiving the resonant state signal.

[0046] Furthermore, the first latch LAT1 and the second latch LAT2 are edge-triggered latches;

[0047] After receiving a rising edge signal indicating that the first voltage rise signal has been detected, the Clk terminal of the first latch LAT1 outputs the first trigger signal to control the first switch S1 to open, so that the capacitor Cr is charged through the current source Ibr, and the rise voltage Vtr begins to rise.

[0048] When the Reset terminal of the first latch LAT1 receives a high-level signal indicating that the second voltage rise signal has been detected, it is triggered to a reset state, outputs the first holding signal, controls the first switch S1 to open, so that the capacitor Cr stops charging and keeps the rise voltage Vtr at its highest value.

[0049] After receiving a rising edge signal indicating that the second voltage drop signal has been detected at the Clk terminal of the second latch LAT2, the third trigger signal is output to control the third switch S3 to open, so that the capacitor Cf is charged through the current source Ibf, and the drop voltage Vtf begins to rise.

[0050] When the Reset terminal of the second latch LAT2 receives a high-level signal indicating that the first voltage drop signal has been detected, it is triggered to a reset state and outputs the second holding signal to control the third switch S3 to open, so that the capacitor Cf stops charging and the dropped voltage Vtf is kept at its maximum value.

[0051] Furthermore, the third latch LAT3 is an edge-triggered latch trigger;

[0052] The third comparator CMP3 outputs a quasi-freewheeling state signal when it determines that Vtr is greater than Vtf or greater than the reference voltage Vref; otherwise, it outputs a quasi-resonant state signal.

[0053] The third latch LAT3 is triggered after receiving a rising edge pulse signal at the Clk terminal, and outputs the quasi-freewheeling state signal received at the D terminal as the freewheeling state signal, or outputs the quasi-resonant state signal received at the D terminal as the resonant state signal.

[0054] To solve the above-mentioned technical problems, this utility model also provides a flyback power charging system, including a transformer that receives input voltage and generates output voltage, wherein the primary winding of the transformer is connected to a primary field-effect transistor, and the secondary winding of the transformer is connected to a secondary field-effect transistor and a load module; the secondary field-effect transistor is connected to the aforementioned synchronous rectification control device.

[0055] The synchronous rectification control device detects fluctuations in the drain voltage of the secondary-side field-effect transistor (FET). When it determines that the drain voltage of the secondary-side FET reaches a preset turn-off threshold voltage, it generates a turn-off drive signal to control the secondary-side FET to turn off. When it determines that the secondary-side FET is in a freewheeling state and the drain voltage is lower than the turn-on threshold voltage, it generates a turn-on drive signal to control the secondary-side FET to turn on. And / or when it determines that the secondary-side FET is in a resonant state, it does not generate the turn-on drive signal.

[0056] Compared with existing technologies, this invention has the following advantages: By detecting the fluctuations of the secondary-side MOSFET, this invention determines whether it is in a freewheeling state or a resonant state. When in a freewheeling state, and the drain voltage of the secondary-side MOSFET is lower than the turn-on threshold voltage, the secondary-side MOSFET is turned on. When in a resonant state, even if the drain voltage of the secondary-side MOSFET is lower than the turn-on threshold voltage, the secondary-side MOSFET is not turned on. This avoids system failure due to incorrect turn-on in the freewheeling state or system failure due to incorrect turn-on in the resonant state. Attached Figure Description

[0057] To further reveal the specific technical content of this case, please first refer to the accompanying drawings, in which:

[0058] Figure 1 This is a schematic diagram of a flyback power charging system using Schottky diodes in the prior art;

[0059] Figure 2 This is a schematic diagram of a flyback power charging system using a secondary-side MOSFET in the prior art.

[0060] Figure 3 This is a schematic diagram of the system waveforms under ideal conditions in CCM mode;

[0061] Figure 4 This is a schematic diagram of the system waveform under ideal conditions in QR mode;

[0062] Figure 5 This is a schematic diagram of the system waveforms under ideal conditions in DCM mode;

[0063] Figure 6 This is a waveform diagram of the secondary MOSFET being erroneously turned on during the resonant phase in an actual system.

[0064] Figure 7 This is a waveform diagram of the actual system when the secondary and primary sides are simultaneously erroneously turned on during the resonance stage.

[0065] Figure 8 This is a circuit structure diagram of a synchronous rectifier controller using existing technology;

[0066] Figure 9 This is a circuit diagram of the synchronous rectification control device according to an embodiment of the present invention;

[0067] Figure 10 yes Figure 9 A waveform diagram of a synchronous rectification control device;

[0068] Figure 11 yes Figure 9 Block diagram of the state determination circuit;

[0069] Figure 12 yes Figure 11 A circuit implementation diagram of a state determination circuit;

[0070] Figure 13 yes Figure 12 The waveform diagram corresponding to the circuit. Detailed Implementation

[0071] The technical solutions in the embodiments of this utility model will now be described with reference to the accompanying drawings.

[0072] The flyback power charging system provided in this embodiment includes a transformer that receives input voltage and generates output voltage. The primary winding of the transformer is connected to a primary field-effect transistor (FET), and the secondary winding of the transformer is connected to a secondary FET and a load module. The secondary FET is connected to a synchronous rectification control device.

[0073] The synchronous rectification control device detects fluctuations in the drain voltage of the secondary-side field-effect transistor. When it determines that the secondary-side field-effect transistor is in freewheeling mode and the drain voltage is lower than the conduction threshold voltage, it generates a conduction drive signal to control the secondary-side field-effect transistor to conduct; and / or when it determines that the secondary-side field-effect transistor is in resonance mode, it does not generate a conduction drive signal.

[0074] like Figure 9 As shown, the synchronous rectification control device of this utility model embodiment includes a drive module, and a turn-on control module and a turn-off control module connected to the drive module.

[0075] Specifically, the drive module receives the turn-on signal output by the turn-on control module and generates a turn-on drive signal that can control the conduction of the secondary-side field-effect transistor FET2 of the flyback power charging system; and receives the turn-off signal output by the turn-off control module and generates a turn-off drive signal that can control the turn-off of the secondary-side field-effect transistor FET2 of the flyback power charging system.

[0076] The shutdown control module outputs a shutdown signal when it determines that the drain voltage VD_SR of the secondary-side field-effect transistor FET2 reaches the preset shutdown threshold voltage.

[0077] The conduction control module includes a status judgment circuit and a conduction determination circuit.

[0078] The state determination circuit detects the rise time Tr of the drain voltage of the secondary-side field-effect transistor (FET2) when it changes from a first reference voltage VR1 greater than or equal to a preset second reference voltage VR2, and the fall time Tf when it changes from a second reference voltage VR2 less than or equal to a preset first reference voltage VR1. When the drain voltage VD_SR of the secondary-side FET2 drops to less than the first reference voltage VR1, it determines that the current fall time Tf is less than N times the rise time Tr, and then outputs a freewheeling state signal. And / or, it determines that the current fall time Tf is greater than or equal to N times the rise time Tr, and then outputs a resonance state signal. The first reference voltage VR1 is less than the second reference voltage VR2. Wherein, N is any positive integer or any positive fraction.

[0079] The turn-on determination circuit generates and outputs a turn-on signal when it detects that the drain voltage VD_SR of the secondary-side field-effect transistor FET2 is lower than the preset turn-on threshold voltage and the freewheeling state signal; and / or generates and outputs an anti-turn-on signal when it detects the resonant state signal.

[0080] Specifically, in this embodiment, the conduction determination circuit includes a comparator CMP connected to the drain of the secondary-side field-effect transistor FET2 and an AND gate connected to the output of the comparator CMP and the output of the state determination circuit.

[0081] The comparator CMP determines whether the drain voltage VD_SR of the current secondary-side field-effect transistor FET2 is lower than the turn-on threshold voltage Von. If so, it outputs a quasi-turn-on signal.

[0082] The AND gate outputs a conduction signal after receiving a quasi-conductivity signal and a freewheeling state signal; and / or outputs an anti-conductivity signal after receiving a resonant state signal.

[0083] like Figure 10 The diagram shown is a waveform representation of the synchronous rectification control device in this embodiment. In this embodiment, the first reference voltage VR1 is less than the second reference voltage VR2, but greater than the conduction threshold voltage Von.

[0084] During the freewheeling state, the drain voltage VD_SR of the secondary-side FET2 jumps from a value higher than VR2 to below the turn-on threshold voltage Von, and then slowly rises linearly. During the resonant state, the drain voltage VD_SR of the secondary-side FET2 fluctuates in an approximately sinusoidal manner, during which time the secondary-side FET2 needs to be turned off. During the primary-side conduction state, VD_SR is a square wave higher than the second reference voltage VR2, during which time the secondary-side FET2 also needs to be kept off.

[0085] In the freewheeling state, the state determination circuit outputs a high-level freewheeling state signal, and the conduction determination circuit outputs a high-level quasi-conduction signal. During the resonant state, the state determination circuit outputs a low-level resonant state signal, and the conduction determination circuit outputs a high-level quasi-conduction signal when VD_SR is below the conduction threshold voltage. In this embodiment, a pulse signal with ENCOP at a high level is used as the freewheeling state signal, and a low-level signal is used as the resonant state signal. A pulse signal with COMP at a high level is used as the quasi-conduction signal.

[0086] When both ENCOP and COMP are high-level pulse signals, the conduction determination circuit outputs a high-level conduction signal; when either ENCOP or COMP is a low-level signal, the conduction determination circuit outputs a low-level inverse conduction signal. In this embodiment, the high-level pulse signal of the SRON signal is used as the conduction signal, and the low-level signal is used as the inverse conduction signal.

[0087] After receiving the turn-on signal, the driver module sends a turn-on drive signal to the secondary-side field-effect transistor FET2, causing the gate voltage VG_SR of FET2 to momentarily jump to a high level, thus turning it on. After receiving the turn-off signal, the driver module sends a turn-off drive signal to the secondary-side field-effect transistor FET2, causing the gate voltage VG_SR of FET2 to momentarily jump to a low level, thus turning it off.

[0088] like Figure 11 As shown, the state judgment circuit of this utility model embodiment includes a comparison unit, a rising period detection circuit, a falling period detection circuit, and an output unit.

[0089] The comparison unit compares the current drain voltage VD_SR of the secondary-side field-effect transistor FET2 with the preset first reference voltage VR1 and second reference voltage VR2. If the current drain voltage VD_SR of the secondary-side field-effect transistor FET2 is greater than the first reference voltage VR1, a first voltage rise signal is output; otherwise, a first voltage fall signal is output. If the current drain voltage VD_SR of the secondary-side field-effect transistor FET2 is greater than the second reference voltage VR2, a second voltage rise signal is output; otherwise, a second voltage fall signal is output.

[0090] The rise-period detection circuit generates a rise voltage Vtr based on the first voltage rise signal, the first voltage fall signal, the second voltage rise signal, and the second voltage fall signal.

[0091] The detection circuit during the voltage drop period generates a reduced voltage Vtf based on the first voltage rise signal, the first voltage drop signal, the second voltage rise signal, and the second voltage drop signal.

[0092] The output unit outputs a freewheeling state signal when the first voltage rise signal changes to the first voltage fall signal, if the depreciation voltage Vtf is less than the rise voltage Vtr; and / or, if the depreciation voltage Vtf is greater than the rise voltage Vtr, it outputs a resonance state signal.

[0093] In this embodiment, the rise time Tr is equivalent to the rise voltage Vtr of the drain voltage of the secondary-side field-effect transistor during the period from greater than the first reference voltage VR1 to greater than the second reference voltage VR2; the fall time Tf is equivalent to the fall voltage Vtf of the drain voltage of the secondary-side field-effect transistor during the period from less than the second reference voltage VR2 to less than the first reference voltage VR1.

[0094] Specifically, in this embodiment, the rise-period detection circuit includes a rise state latch trigger unit and a rise voltage generation unit.

[0095] The rising state latch trigger unit outputs a first trigger signal when it detects a first voltage rise signal in sequence; outputs a first hold signal when it detects a second voltage rise signal; and outputs a second trigger signal when it detects a first voltage drop signal.

[0096] The voltage rise generation unit generates a voltage rise Vtr whose voltage value gradually increases according to a first trigger signal; stops increasing the voltage rise Vtr and holds it at the highest value according to a first hold signal; and generates a voltage rise Vtr that gradually decreases from the highest value according to a second trigger signal.

[0097] In this embodiment, the boost voltage Vtr only rises when the drain voltage VD_SR of the secondary-side field-effect transistor FET2 is greater than the first reference voltage VR1. When VD_SR rises to a level greater than the second reference voltage VR2, the boost voltage Vtr stops rising and remains at its highest value. When VD_SR drops below the first reference voltage VR1, the boost voltage Vtr begins to decrease. In this embodiment, the boost voltage Vtr will drop to ground (zero value).

[0098] The detection circuit during the descent period includes a descent state latch trigger unit and a decrement voltage generation unit.

[0099] The falling state latch trigger unit outputs a third trigger signal when it detects the second voltage drop signal in sequence; outputs a second hold signal when it detects the first voltage drop signal; and outputs a fourth trigger signal when it detects the second voltage rise signal.

[0100] The depreciation voltage generation unit generates a gradually increasing depreciation voltage Vtf based on a third trigger signal; it stops increasing the depreciation voltage Vtf and holds it at its highest value based on a second hold signal; and it generates a gradually decreasing depreciation voltage Vtf from its highest value based on a fourth trigger signal.

[0101] In this embodiment, the depreciation voltage Vtf rises only when the drain voltage VD_SR of the secondary-side field-effect transistor FET2 is less than the second reference voltage VR2. When VD_SR drops below the first reference voltage VR1, Vtf stops rising and remains at its highest value. When VD_SR rises again above the second reference voltage VR2, the depreciation voltage Vtf begins to decrease. In this embodiment, the depreciation voltage Vtf will drop to ground (zero value).

[0102] like Figure 12 and Figure 13 The figures shown are circuit implementation diagrams and waveform diagrams of a state determination circuit according to an embodiment of this utility model. The comparison unit includes a first comparator CMP1 and a second comparator CMP2.

[0103] The first comparator CMP1 detects whether the drain voltage VD_SR of the current secondary-side field-effect transistor FET2 is greater than the first reference voltage VR1. If it is, it outputs the first voltage rise signal; otherwise, it outputs the first voltage fall signal.

[0104] Specifically, in this embodiment, the high-level signal of the OUT1 signal is used as the first voltage rise signal, and the low-level signal is used as the first voltage fall signal.

[0105] The second comparator CMP2 detects whether the drain voltage VD_SR of the current secondary-side field-effect transistor FET2 is greater than the second reference voltage VR2. If it is, it outputs the second voltage rise signal; otherwise, it outputs the second voltage fall signal.

[0106] Specifically, in this embodiment, the high-level signal of the OUT2 signal is used as the second voltage rise signal, and the low-level signal is used as the second voltage fall signal.

[0107] The rising state latch trigger unit includes a first latch LAT1 connected to the output of the first comparator CMP1 and the second comparator CMP2, and an NOT gate NOT1 connected to the output of the first comparator CMP1.

[0108] The boost voltage generation unit includes a current source Ibr connected to the power supply VDD, a first switch S1 connected in series with the current source Ibr and controlled by the first latch LAT1, a capacitor Cr connected in series with the first switch S1 and grounded at the other end, and a second switch S2 connected in parallel with the capacitor Cr and controlled by the NOT gate NOT1.

[0109] The Clk terminal of the first latch LAT1 is connected to the output terminal of the first comparator CMP1, and the Reset terminal is connected to the output terminal of the second comparator CMP2.

[0110] Specifically, the first latch LAT1 is an edge-triggered latch trigger. When the OUT1 signal changes from low to high, the Clk terminal receives the rising edge signal and outputs the high level of the D terminal from the Q terminal, outputting the first trigger signal to control the first switch S1 to open, so that the capacitor Cr can be charged from the current source Ibr, thereby increasing the voltage value of the boost voltage Vtr and maintaining this state.

[0111] After the OUT2 signal changes from low to high, the Reset terminal receives the high-level signal, and the first latch LAT1 enters the reset state. The Q terminal outputs a low-level first holding signal, which controls the first switch S1 to open. The capacitor Cr no longer draws current from the current source Ibr, so the rising voltage Vtr stops rising and remains at its highest value.

[0112] After the OUT1 signal transitions from high to low, the first latch LAT1 continues to output a low level, and the first switch S1 remains open. Meanwhile, the NOT gate, upon receiving the low-level OUT1 signal, sends a high-level second trigger signal, controlling the second switch S2 to open. This causes the capacitor Cr to begin discharging, and the boost voltage Vtr begins to decrease. After a short period of decrease, Vtr returns to zero.

[0113] In this embodiment, the falling state latch trigger unit includes NOT2, which is connected to the output of the second comparator CMP2, and LAT2, which is connected to the output of NOT1 and NOT2.

[0114] The Clk terminal of the second latch LAT2 is connected to the output of NOT gate NOT2, and the Reset terminal is connected to the output of NOT gate NOT1.

[0115] In this embodiment, the degraded voltage generation unit includes a current source Ibf connected to the power supply VDD, a third switch S3 connected in series with the current source Ibf and controlled by the second latch LAT2, a capacitor Cf connected in series with the third switch S3 and grounded at the other end, and a fourth switch S4 connected in parallel with the capacitor Cf and controlled by the second comparator CMP2.

[0116] Specifically, the second latch, LAT2, is also an edge-triggered latch-on trigger, triggered upon receiving a rising edge signal at the Clk terminal. When the OUT2 signal transitions from high to low, it is converted into the OUT2b signal (from low to high) by the NOT gate, causing the second latch, LAT2, to output a high-level signal at the D terminal. This outputs a third trigger signal to control the third switch, S3, to open and maintain this state. This allows the capacitor Cf to charge through the current source Ibf, causing the depreciation voltage Vtf to begin rising.

[0117] When the OUT1 signal transitions from high to low, it is converted into the OUT1b signal (from low to high) by the NOT gate. Upon receiving this high-level signal, the Reset terminal of the second latch LAT2 is triggered to reset, outputting a low-level second holding signal to open the third switch S3. This stops the capacitor Cf from charging and maintains the degraded voltage Vtf at its maximum value.

[0118] When the OUT2 signal transitions from low to high, it is converted into the OUT2b signal (from high to low) by the NOT gate. The second latch LAT2 is not triggered and continues to output a low-level signal, while the third switch S3 remains open. However, the fourth switch S4, upon receiving the high-level OUT2 signal (i.e., the fourth trigger signal), is opened, causing capacitor Cf to discharge and the depreciation voltage Vtf to decrease. After a short period, Vtf returns to zero.

[0119] In this embodiment, when the second voltage drop signal, the first voltage drop signal, and the second voltage rise signal are detected in sequence, the second voltage rise signal is directly used as the fourth trigger signal.

[0120] In this embodiment, the output unit includes a third comparator CMP3 connected to capacitors Cr and Cf, a third latch LAT3 connected to the output of the third comparator CMP3, and a delay unit BUF connected to the third latch LAT3.

[0121] The non-inverting input of the third comparator CMP3 is connected to capacitor Cr, the first inverting input is connected to capacitor Cf, the second inverting input is connected to the reference voltage Vref, and the output is connected to the third latch LAT3.

[0122] The Clk terminal of the third latch LAT3 is connected to the output of the NOT gate NOT1, the D terminal is connected to the output of the third comparator CMP3, the Reset terminal is connected to the output of the delay unit BUF, and the output terminal outputs the freewheeling state signal and / or the resonant state signal.

[0123] The input of the delay unit BUF is connected to the turn-on signal, and the output is connected to the Reset terminal of the third latch LAT3.

[0124] Specifically, in this embodiment, the third comparator CMP3 is a three-phase comparator. The first inverting input is connected to capacitor Cf to obtain the value of the degraded voltage Vtf. The reference voltage Vref is connected to the second inverting input, and its value can be designed according to the actual circuit conditions. The non-inverting input is connected to capacitor Cr to obtain the value of the boosted voltage Vtr. If Vtr is greater than Vtf, or greater than the reference voltage Vref, a quasi-freewheeling state signal is output; otherwise, a quasi-resonant state signal is output. In this embodiment, the high-level OUT3 signal is used as the quasi-freewheeling state signal, and the low-level OUT3 signal is used as the quasi-resonant state signal.

[0125] The ratio N of rise time Tr to fall time Tf can be set by controlling the ratio between current sources Ibr and Ibf, or by setting the ratio between capacitors Cr and Cf. Assuming current source Ibr is equal to 0.5 times current source Ibf, or capacitor Cr is equal to twice capacitor Cf, then N equals 0.5. When 0.5 × Tr > Tf (Vtf < Vtr), a high-level OUT3 signal is output; when 0.5 × Tr ≤ Tf (Vtf > Vtr), a low-level OUT3 signal is output. Those skilled in the art can design the value of N according to actual conditions; any positive integer or fraction is acceptable and will not affect the implementation of this invention.

[0126] The third latch, LAT3, is an edge-triggered latch-on trigger. It is triggered upon receiving a rising edge pulse signal at the Clk terminal, outputting the OUT3 signal. Specifically, when the OUT1 signal transitions from high to low, it passes through the NOT gate, causing the output OUT1b to transition from low to high. Upon receiving this rising edge pulse signal, the third latch, LAT3, outputs the OUT3 signal at this time. If the OUT3 signal is high at this time, a high-level freewheeling state signal is output, indicating that the current state is freewheeling, and the output is maintained. If the OUT3 signal is low at this time, a low-level resonant state signal is output, indicating that the current state is resonant, and the output is maintained. In this embodiment, the high-level ENCOP signal is used as the freewheeling state signal, and the low-level ENCOP signal is used as the resonant state signal. Those skilled in the art can invert these signals without affecting the implementation of this invention.

[0127] The turn-on determination circuit, upon receiving a high-level ENCOP signal and a high-level COMP signal, outputs a high-level SRON signal via an AND gate. This SRON signal is then delayed by one clock cycle (or a short time) by the delay unit BUF before being output to the third latch, LAT3. Upon receiving this high-level signal, the Reset terminal of the third latch, LAT3, enters a reset state and outputs a low-level ENCOP signal. The turn-on determination circuit, upon receiving a low-level ENCOP signal, outputs a low-level SRON signal via an AND gate. The delay unit BUF delays the low-level SRON signal by one clock cycle (or a short time) before outputting it to the third latch, LAT3. Upon receiving this low-level signal, the Reset terminal of the third latch, LAT3, remains untriggered and continues to output a low-level ENCOP signal until the Clk terminal receives a rising edge pulse signal and a high-level OUT3 signal, at which point it outputs a high-level ENCOP signal.

[0128] Therefore, the high-level ENCOP signal will only be maintained for one clock cycle (or other short time) before switching to a low level, so that the SRON signal will also only output a high-level signal for one clock cycle (or other short time), ensuring that the secondary-side FET2 will not be erroneously turned on.

[0129] Specifically, during the freewheeling state, the drain voltage VD_SR of the secondary-side field-effect transistor FET2 jumps from a value higher than VR2 to below the turn-on threshold voltage Von, and then slowly rises linearly. During this period, the secondary-side field-effect transistor FET2 needs to be turned on. During the resonant state, the drain voltage VD_SR of the secondary-side field-effect transistor FET2 fluctuates in an approximately sinusoidal manner. During this period, the secondary-side field-effect transistor FET2 needs to be turned off. During the primary-side turn-on period, VD_SR is a square wave higher than the second reference voltage VR2. During this period, the secondary-side field-effect transistor FET2 also needs to be turned off.

[0130] Because in the freewheeling state, the voltage value of VD_SR transitions from a high level to a low level and then rises slowly and linearly, which is significantly different from the sinusoidal fluctuation state of the resonant state, the waveform change of VD_SR voltage can be detected to determine whether it is in the freewheeling state or the resonant state. During the primary-side conduction period before entering the freewheeling state, the rise time Tr of VD_SR from greater than VR1 to greater than VR2 is much longer than the fall time Tf of VD_SR from less than VR2 to less than VR1. In the resonant state, the rise time Tr and the fall time Tf are proportionally symmetrical.

[0131] Therefore, when the drain voltage VD_SR of the secondary-side field-effect transistor FET2 drops to less than the first reference voltage VR1, if the fall time Tf is less than N times the rise time Tr, the current state is freewheeling; if the fall time Tf is greater than or equal to N times the rise time Tr, the current state is resonant.

[0132] In this embodiment, the rise time Tr is equivalent to the rise voltage Vtr of the drain voltage of the secondary-side field-effect transistor during the period from greater than the first reference voltage VR1 to greater than the second reference voltage VR2; and the fall time Tf is equivalent to the fall voltage Vtf of the drain voltage of the secondary-side field-effect transistor during the period from less than the second reference voltage VR2 to less than the first reference voltage VR1.

[0133] Specifically, in this embodiment, the boost voltage Vtr only rises when the drain voltage VD_SR of the secondary-side field-effect transistor FET2 is greater than the first reference voltage VR1. When VD_SR rises to a level greater than the second reference voltage VR2, the boost voltage Vtr stops rising and remains at its highest value. When VD_SR drops below the first reference voltage VR1, the boost voltage Vtr begins to decrease. In this embodiment, the boost voltage Vtr will drop to ground (zero value).

[0134] The depreciation voltage Vtf rises only when the drain voltage VD_SR of the secondary-side field-effect transistor FET2 is less than the second reference voltage VR2. When VD_SR drops below the first reference voltage VR1, Vtf stops rising and remains at its highest value. When VD_SR rises again above the second reference voltage VR2, the depreciation voltage Vtf begins to decrease. In this embodiment, the depreciation voltage Vtf drops to ground (zero value).

[0135] In summary, this invention detects fluctuations in the secondary-side MOSFET to determine whether it is in a freewheeling or resonant state. In the freewheeling state, the secondary-side MOSFET is turned on when its drain voltage is below the turn-on threshold voltage. In the resonant state, the secondary-side MOSFET is not turned on even if its drain voltage is below the turn-on threshold voltage. This avoids system malfunctions caused by incorrect turn-on in the freewheeling state or system failure caused by incorrect turn-on in the resonant state.

[0136] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A synchronous rectification control device, characterized by comprising: It includes a drive module, and an on control module and an off control module connected to the drive module; The drive module receives the conduction signal output by the conduction control module and generates a conduction drive signal that can control the conduction of the secondary-side field-effect transistor of the flyback power charging system. And receive the shutdown signal output by the shutdown control module, and generate a shutdown drive signal that can control the shutdown of the secondary-side field-effect transistor FET2 of the flyback power charging system. The conduction control module includes a state judgment circuit and a conduction determination circuit; The state determination circuit detects the rise time Tr of the drain voltage of the secondary-side field-effect transistor when it changes from a preset first reference voltage VR1 to a preset second reference voltage VR2, and the fall time Tf when it changes from a preset second reference voltage VR2 to a preset first reference voltage VR1. When the drain voltage of the secondary-side field-effect transistor drops to less than the first reference voltage VR1, it determines that the current fall time Tf is less than N times the rise time Tr, and then outputs a freewheeling state signal; and / or, it determines that the current fall time Tf is greater than or equal to N times the rise time Tr, and then outputs a resonance state signal; the first reference voltage VR1 is less than the second reference voltage VR2; N is any positive integer or any positive fraction; the rise time Tr is equivalent to the rise voltage Vtr of the drain voltage of the secondary-side field-effect transistor during the period from greater than the first reference voltage VR1 to greater than the second reference voltage VR2; the fall time Tf is equivalent to the drop voltage Vtf of the drain voltage of the secondary-side field-effect transistor during the period from less than the second reference voltage VR2 to less than the first reference voltage VR1. The conduction determination circuit generates and outputs the conduction signal when it detects that the drain voltage of the secondary-side field-effect transistor is lower than the preset conduction threshold voltage and the freewheeling state signal; and / or generates and outputs the anti-conduction signal when it detects the resonance state signal. The shutdown control module outputs the shutdown signal when it determines that the drain voltage of the secondary-side field-effect transistor FET2 reaches the preset shutdown threshold voltage.

2. The synchronous rectification control device of claim 1, wherein, The state determination circuit includes a comparison unit, a rising period detection circuit, a falling period detection circuit, and an output unit. The comparison unit compares the current drain voltage of the secondary-side field-effect transistor with a preset first reference voltage VR1 and a second reference voltage VR2. If the current drain voltage of the secondary-side field-effect transistor is greater than the first reference voltage VR1, a first voltage rise signal is output; otherwise, a first voltage fall signal is output. If the current drain voltage of the secondary-side field-effect transistor is greater than the second reference voltage VR2, a second voltage rise signal is output; otherwise, a second voltage fall signal is output. The rise-period detection circuit generates the rise voltage Vtr based on the first voltage rise signal, the first voltage fall signal, the second voltage rise signal, and the second voltage fall signal. The detection circuit during the voltage drop period generates the reduced voltage Vtf based on the first voltage rise signal, the first voltage drop signal, the second voltage rise signal, and the second voltage drop signal. When the first voltage rise signal changes to the first voltage fall signal, the output unit outputs the freewheeling state signal if the depreciation voltage Vtf is less than the rise voltage Vtr; and / or, if the depreciation voltage Vtf is greater than the rise voltage Vtr, the output unit outputs the resonance state signal.

3. The synchronous rectification control device of claim 2, wherein, The rise-period detection circuit includes a rise state latch trigger unit and a rise voltage generation unit; The rising state latch trigger unit outputs a first trigger signal when it detects the first voltage rise signal in sequence; outputs a first hold signal when it detects the second voltage rise signal; and outputs a second trigger signal when it detects the first voltage fall signal. The voltage boosting generation unit generates a voltage boosting voltage Vtr that gradually increases in value according to the first trigger signal; stops increasing the voltage boosting voltage Vtr and holds it at the highest value according to the first hold signal; and generates a voltage boosting voltage Vtr that gradually decreases from the highest value according to the second trigger signal. The descent detection circuit includes a descent state latch trigger unit and a decrement voltage generation unit; The falling state latch trigger unit outputs a third trigger signal when it detects the second voltage drop signal in sequence; outputs a second hold signal when it detects the first voltage drop signal; and outputs a fourth trigger signal when it detects the second voltage rise signal. The degraded voltage generation unit generates a gradually increasing degraded voltage Vtf according to the third trigger signal; stops increasing the degraded voltage Vtf and maintains it at the highest value according to the second hold signal; and generates a gradually decreasing degraded voltage Vtf from the highest value according to the fourth trigger signal.

4. The synchronous rectification control apparatus of claim 3, wherein The comparison unit includes a first comparator CMP1 and a second comparator CMP2; The first comparator CMP1 detects whether the drain voltage of the current side field-effect transistor is greater than the first reference voltage VR1. If it is, it outputs the first voltage rise signal; otherwise, it outputs the first voltage fall signal. The second comparator CMP2 detects whether the drain voltage of the current secondary-side field-effect transistor is greater than the second reference voltage VR2. If it is, it outputs the second voltage rise signal; otherwise, it outputs the second voltage fall signal. The voltage value of the first reference voltage VR1 is less than the voltage value of the second reference voltage VR2.

5. The synchronous rectification control apparatus of claim 4, wherein The rising state latch trigger unit includes a first latch LAT1 connected to the outputs of the first comparator CMP1 and the second comparator CMP2, and a NOT gate NOT1 connected to the output of the first comparator CMP1. The voltage boosting unit includes a current source Ibr connected to the power supply VDD, a first switch S1 connected in series with the current source Ibr and controlled by the first latch LAT1, and a capacitor Cr connected in series with the first switch S1 and grounded at the other end, and a second switch S2 connected in parallel with the capacitor Cr and controlled by the NOT gate NOT1. The Clk terminal of the first latch LAT1 is connected to the output terminal of the first comparator CMP1, and the Reset terminal is connected to the output terminal of the second comparator CMP2; The falling state latch triggering unit includes NOT2 connected to the output of the second comparator CMP2 and LAT2 connected to the output of NOT1 and NOT2. The Clk terminal of the second latch LAT2 is connected to the output terminal of the NOT gate NOT2, and the Reset terminal is connected to the output terminal of the NOT gate NOT1; The degraded voltage generation unit includes a current source Ibf connected to the power supply VDD, a third switch S3 connected in series with the current source Ibf and controlled by the second latch LAT2, a capacitor Cf connected in series with the third switch S3 and grounded at the other end, and a fourth switch S4 connected in parallel with the capacitor Cf and controlled by the second comparator CMP2.

6. The synchronous rectification control apparatus of claim 5, wherein The output unit includes a third comparator CMP3 connected to the capacitor Cr and the capacitor Cf, a third latch LAT3 connected to the output of the third comparator CMP3, and a delay unit BUF connected to the third latch LAT3. The non-inverting input of the third comparator CMP3 is connected to the capacitor Cr, the first inverting input is connected to the capacitor Cf, the second inverting input is connected to the reference voltage Vref, and the output is connected to the third latch LAT3. The Clk terminal of the third latch LAT3 is connected to the output terminal of the NOT gate NOT1, the D terminal is connected to the output terminal of the third comparator CMP3, the Reset terminal is connected to the output terminal of the delay unit BUF, and the output terminal outputs the freewheeling state signal and / or the resonant state signal. The input of the delay unit BUF is connected to the conduction signal, and the output is connected to the Reset terminal of the third latch LAT3.

7. The synchronous rectification control apparatus of claim 2, wherein The conduction determination circuit includes a comparator CMP connected to the drain of the secondary-side field-effect transistor and an AND gate connected to the output of the comparator CMP and the output of the state determination circuit. The comparator CMP determines whether the drain voltage of the current secondary-side field-effect transistor is lower than the conduction threshold voltage Von. If so, it outputs a quasi-conduction signal. The AND gate outputs the conduction signal after receiving the quasi-conductivity signal and the freewheeling state signal; and / or outputs the anti-conductivity signal after receiving the resonant state signal.

8. The synchronous rectification control apparatus of claim 5, wherein The first latch LAT1 and the second latch LAT2 are edge-triggered latch triggers; After receiving a rising edge signal indicating that the first voltage rise signal has been detected, the Clk terminal of the first latch LAT1 outputs the first trigger signal to control the first switch S1 to open, so that the capacitor Cr is charged through the current source Ibr, and the rise voltage Vtr begins to rise. When the Reset terminal of the first latch LAT1 receives a high-level signal indicating that the second voltage rise signal has been detected, it is triggered to a reset state, outputs the first holding signal, controls the first switch S1 to open, so that the capacitor Cr stops charging and keeps the rise voltage Vtr at its highest value. After receiving a rising edge signal indicating that the second voltage drop signal has been detected at the Clk terminal of the second latch LAT2, the third trigger signal is output to control the third switch S3 to open, so that the capacitor Cf is charged through the current source Ibf, and the drop voltage Vtf begins to rise. When the Reset terminal of the second latch LAT2 receives a high-level signal indicating that the first voltage drop signal has been detected, it is triggered to a reset state and outputs the second holding signal to control the third switch S3 to open, so that the capacitor Cf stops charging and the dropped voltage Vtf is kept at its maximum value.

9. The synchronous rectification control apparatus of claim 6, wherein The third latch, LAT3, is an edge-triggered latch trigger. The third comparator CMP3 outputs a quasi-freewheeling state signal when it determines that Vtr is greater than Vtf or greater than the reference voltage Vref; otherwise, it outputs a quasi-resonant state signal. The third latch LAT3 is triggered after receiving a rising edge pulse signal at the Clk terminal, and outputs the quasi-freewheeling state signal received at the D terminal as the freewheeling state signal, or outputs the quasi-resonant state signal received at the D terminal as the resonant state signal.

10. A flyback power supply charging system characterized by, The transformer includes a transformer that receives an input voltage and generates an output voltage, wherein the primary winding of the transformer is connected to a primary field-effect transistor (FET), and the secondary winding of the transformer is connected to a secondary FET and a load module; the secondary FET is connected to a synchronous rectification control device as described in any one of claims 1-9. The synchronous rectification control device detects the fluctuation of the drain voltage of the secondary field-effect transistor. When it determines that the drain voltage of the secondary field-effect transistor reaches the preset turn-off threshold voltage, it generates a turn-off drive signal to control the secondary field-effect transistor to turn off. When it is determined that the secondary-side MOSFET is in freewheeling mode and the drain voltage is lower than the turn-on threshold voltage, a turn-on drive signal is generated to control the secondary-side MOSFET to turn on; and / or when it is determined that the secondary-side MOSFET is in resonant mode, the turn-on drive signal is not generated.

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