Three-level topology precharge protection circuit

CN224438816UActive Publication Date: 2026-06-30GUANGDONG BIFU NEW ENERGY CO LTD

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
GUANGDONG BIFU NEW ENERGY CO LTD
Filing Date
2025-08-06
Publication Date
2026-06-30

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Abstract

This utility model relates to the field of photovoltaic inverter technology and discloses a three-level topology pre-charge protection circuit, including: an overcurrent protection module; a voltage detection module; an overvoltage buffer module; and a logic control module. Through the design of the overcurrent protection module and the voltage detection module, multi-level collaborative current limiting is achieved. Physical current limiting is performed using the pre-charge resistor, and combined with voltage detection feedback, a closed-loop control is formed, which significantly reduces the surge current at the moment of power-up of the equipment and prevents overcurrent damage to the equipment. Through the design of the voltage detection module, the total bus voltage, the upper half bus voltage, and the lower half bus voltage are detected respectively. The midpoint potential deviation can be monitored in real time. If the deviation is large, pre-charging is stopped immediately to avoid transistor midpoint overvoltage breakdown and ensure the stability and safety of the pre-charging process.
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Description

Technical Field

[0001] This utility model relates to the field of photovoltaic inverter technology, and in particular to the field of charging protection for photovoltaic inverters, specifically a three-level topology pre-charge protection circuit. Background Technology

[0002] A photovoltaic inverter is an inverter that converts the variable DC voltage generated by photovoltaic solar panels into AC power at the mains frequency. This AC power can be fed back into commercial power transmission systems or supplied to off-grid power grids.

[0003] The "charging protection" function of a photovoltaic inverter mainly refers to a series of protective measures implemented by the inverter or its controller during the charging process of energy storage batteries (such as lead-acid batteries, lithium batteries, etc.) by the photovoltaic power generation system, to ensure the safe, stable and long-life operation of the batteries.

[0004] A search revealed that patent application number CN202323309996.8 discloses a pre-charge protection circuit and a battery device. The pre-charge protection circuit includes a power input terminal for receiving a first voltage and a battery terminal for receiving the battery, as well as a buffer capacitor bank. The pre-charge protection circuit comprises: a control circuit; a pre-charge circuit for reducing and outputting the input current at the power input terminal; a first switching circuit for opening / closing the path between the power input terminal and the buffer capacitor bank; and a voltage conversion circuit for increasing / decreasing and outputting the input first voltage. This invention aims to improve the safety and stability of battery device charging.

[0005] Traditional precharge protection circuits rely on a single resistor to suppress surge current, resulting in surge current peaks exceeding thousands of amperes, posing safety hazards and easily causing equipment damage. Furthermore, they only monitor the total bus voltage, lacking independent detection of the first and second halves of the bus, making it inconvenient to monitor the bus midpoint potential shift / imbalance in real time. However, the bus midpoint potential shift / imbalance is often the main source of faults in the precharge process. Therefore, we need to propose a three-level topology precharge protection circuit. Utility Model Content

[0006] The purpose of this invention is to provide a three-level topology pre-charge protection circuit. Through the design of an overcurrent protection module and a voltage detection module, multi-level collaborative current limiting is achieved. Physical current limiting is performed using a pre-charge resistor, and combined with voltage detection feedback, a closed-loop control is formed, which significantly reduces the surge current at the moment of power-on and prevents overcurrent damage to the equipment. Through the design of the voltage detection module, the total bus voltage, the upper half bus voltage, and the lower half bus voltage are detected respectively. The midpoint potential deviation can be monitored in real time. If the deviation is large, pre-charging is stopped immediately to avoid transistor midpoint overvoltage breakdown, ensuring the stability and safety of the pre-charging process, thereby solving the problems mentioned in the background art.

[0007] To achieve the above objectives, this utility model provides the following technical solution: a three-level topology pre-charge protection circuit, comprising:

[0008] Overcurrent protection module used to reduce the initial surge current at the moment of power-on;

[0009] A voltage detection module to determine whether pre-charging is complete and to ensure balanced charging of DC bus capacitors;

[0010] An overvoltage buffer module used to absorb voltage spikes when switching devices are turned off and to suppress electromagnetic interference;

[0011] A logic control module used to monitor the DC-side capacitor voltage, determine the pre-charge completion status, and output control signals to drive the pre-charge switch;

[0012] The overcurrent protection module, voltage detection module, and overvoltage buffer module are all electrically connected to the logic control module.

[0013] Preferably, the overcurrent protection module includes:

[0014] Pre-charge resistor R1 limits the surge current flowing to the DC bus capacitor;

[0015] Contactor K1 controls the on / off state of the pre-charge path;

[0016] Contactor K2 switches the current flow path according to the charging status;

[0017] DC bus capacitors connected to the DC bus and used for energy storage.

[0018] Preferably, one end of the pre-charge resistor R1 is connected to the positive terminal of the DC bus via a rectifier bridge, the main contact of the contactor K1 is connected in parallel with the normally closed contact of the contactor K2, and the other end of the pre-charge resistor R1 is connected to the wiring terminals of the main contact of the contactor K1 and the normally closed contact of the contactor K2.

[0019] The two ends of the main contacts of contactor K2 are respectively connected to the main contacts of contactor K1 and the positive terminal of the DC bus.

[0020] Preferably, the DC bus capacitor includes capacitor C1 and capacitor C2, wherein capacitor C1 is connected between the positive terminal and the midpoint of the DC bus, and capacitor C2 is connected between the negative terminal and the midpoint of the DC bus.

[0021] Preferably, the voltage detection module includes a MOSFET Q2 and a transistor U2. A resistor R22 is connected between the gate of the MOSFET Q2 and the collector of the transistor U2. A resistor R12 is also connected to the gate of the MOSFET Q2. The drain of the MOSFET Q2 and the resistor R12 are both connected to the power supply voltage.

[0022] Preferably, a resistor R42 is connected between the base and emitter of the transistor U2, a diode D2 connected to the enable terminal of the logic control module is connected to the base of the transistor U2, and a resistor R32 and a parallel resistor R52 and a capacitor C12 are connected between the source of the MOSFET Q2 and the emitter of the transistor U2.

[0023] Preferably, the overvoltage buffer module includes a chip U1, a MOSFET Q1, and a transistor Q21. A capacitor C11 and a resistor R1 are connected between pins 1 and 2 of the chip U1, a capacitor C21 is connected between pins 1 and 3 of the chip U1, a resistor R4 and a resistor R5 are connected between the gate of the MOSFET Q1 and the base of the transistor Q21, and the drain of the MOSFET Q1 and the emitter of the transistor Q21 are both connected to pin 3 of the chip U1.

[0024] Compared with the prior art, the beneficial effects of this utility model are:

[0025] 1. This utility model, through the design of overcurrent protection module and voltage detection module, achieves multi-level collaborative current limiting, utilizes pre-charging resistor for physical current limiting, and combines voltage detection feedback to form closed-loop control, which significantly reduces the surge current at the moment of power-on of the equipment and prevents overcurrent damage to the equipment;

[0026] 2. This utility model, through the design of a voltage detection module, detects the total bus voltage, the upper half bus voltage, and the lower half bus voltage respectively. It can monitor the midpoint potential deviation in real time. If the deviation is large, the pre-charging is stopped immediately to avoid overvoltage breakdown of the transistor midpoint and ensure the stability and safety of the pre-charging process. Attached Figure Description

[0027] Figure 1 This is the circuit diagram of the overcurrent protection module of this utility model;

[0028] Figure 2 This is a circuit diagram of the overvoltage buffer circuit of this utility model;

[0029] Figure 3 This is a circuit diagram of the voltage detection circuit of this utility model. Detailed Implementation

[0030] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0031] Please see Figure 1-3 This utility model provides a technical solution: a three-level topology pre-charge protection circuit, comprising:

[0032] Overcurrent protection module used to reduce the initial surge current at the moment of power-on;

[0033] The overcurrent protection module includes:

[0034] Pre-charge resistor R1 limits the surge current flowing to the DC bus capacitor;

[0035] The pre-charge resistor R1 can reduce the surge current of thousands of amperes to a controllable range, protecting components such as the rectifier bridge, capacitors, and contactors.

[0036] Contactor K1 controls the on / off state of the pre-charge path;

[0037] After pre-charging is completed, contactor K1 becomes part of the main power supply path; contactor K1 is responsible for both establishing the pre-charging circuit and the final connection of the main circuit, and the contacts of contactor K1 can withstand the maximum voltage and rated operating current.

[0038] Contactor K2 switches the current flow path according to the charging status;

[0039] When the coil of contactor K2 is not energized, the pre-charge path is opened: contactor K1 → pre-charge resistor R1 → normally closed contact of contactor K2 → DC bus capacitor.

[0040] When the coil of contactor K2 is energized, the main bypass path is activated: contactor K1 → main contacts of contactor K2 → DC bus capacitor.

[0041] Contactor K2 ensures that the pre-charging resistor R1 is completely disconnected from the circuit after pre-charging is complete, thus avoiding losses and heat generation.

[0042] DC bus capacitors connected to the DC bus and used for energy storage.

[0043] One end of the pre-charge resistor R1 is connected to the positive terminal of the DC bus through a rectifier bridge. The main contact of the contactor K1 is connected in parallel with the normally closed contact of the contactor K2. The other end of the pre-charge resistor R1 is connected to the wiring terminals of the main contact of the contactor K1 and the normally closed contact of the contactor K2.

[0044] The two ends of the main contacts of contactor K2 are respectively connected to the main contacts of contactor K1 and the positive terminal of the DC bus.

[0045] The DC bus capacitor includes capacitor C1 and capacitor C2. Capacitor C1 and capacitor C2 have the same capacitance value to reduce initial deviation. Capacitor C1 is connected between the positive terminal and the midpoint of the DC bus, and capacitor C2 is connected between the negative terminal and the midpoint of the DC bus.

[0046] A voltage detection module to determine whether pre-charging is complete and to ensure balanced charging of DC bus capacitors;

[0047] The voltage detection module includes a MOSFET Q2 and a transistor U2. A resistor R22 is connected between the gate of the MOSFET Q2 and the collector of the transistor U2. A resistor R12 is also connected to the gate of the MOSFET Q2. The drain of the MOSFET Q2 and the resistor R12 are both connected to the power supply voltage.

[0048] A resistor R42 is connected between the base and emitter of the transistor U2. A diode D2 connected to the enable terminal of the logic control module is connected to the base of the transistor U2. A resistor R32 and a parallel resistor R52 and a capacitor C12 are connected between the source of the MOSFET Q2 and the emitter of the transistor U2.

[0049] When the logic control module enable pin is high, transistor U2 is turned on, the gate of MOSFET Q2 is pulled low, MOSFET Q2 is turned on, and VCC flows directly to the logic control module enable pin.

[0050] When the enable pin of the logic control module is low, transistor U2 is cut off, the gate of MOSFET Q2 is cut off, and the enable pin is pulled down to ground.

[0051] Diode D2 provides transient protection against backlash voltage. Resistor R52 and capacitor C12 form an RC low-pass filter circuit to filter out high-frequency noise.

[0052] An overvoltage buffer module used to absorb voltage spikes when switching devices are turned off and to suppress electromagnetic interference;

[0053] The overvoltage buffer module includes a chip U1, a MOSFET Q1, and a transistor Q21. A capacitor C11 and a resistor R1 are connected between pins 1 and 2 of the chip U1, and a capacitor C21 is connected between pins 1 and 3 of the chip U1. A resistor R4 and a resistor R5 are connected between the gate of the MOSFET Q1 and the base of the transistor Q21. The drain of the MOSFET Q1 and the emitter of the transistor Q21 are both connected to pin 3 of the chip U1.

[0054] Resistor R1 is a current-limiting resistor to prevent short-circuit impact. Chip U1 is a voltage regulator used to convert high voltage to low voltage. Capacitor C11 is an input filter capacitor to suppress input ripple. Capacitor C21 is an output filter capacitor used to stabilize the output voltage.

[0055] Resistors R2 and R3 are both voltage divider resistors used to set the transistor trigger threshold. Resistor R4 is a base current limiting resistor used to protect MOSFET Q1. MOSFET Q1 is used to protect the switch. Diode D1 is a clamping diode used for overvoltage protection.

[0056] A logic control module used to monitor the DC-side capacitor voltage, determine the pre-charge completion status, and output control signals to drive the pre-charge switch;

[0057] The logic control module receives the power-on / start command and controls the contactor K1 to close. It continuously monitors the voltage detection signals (V_dc_PN, V_dc_PO, V_dc_ON). When V_dc_PN is greater than or equal to the pre-charge completion threshold, it sends a command to enable the coil of contactor K2.

[0058] If overcurrent is detected, a fault is identified, and charging is terminated. If the target voltage is not reached within the specified time, a fault is identified. If an excessive voltage difference is detected between V_dc_PO and V_dc_ON, a fault is identified.

[0059] When a fault is detected, contactor K1 is disconnected, contactor K2 is disabled, and a fault signal is issued. When the system is powered down, a shutdown command is received, contactor K1 is disconnected, and contactor K2 is disabled.

[0060] V_dc_PN is the total DC bus voltage, V_dc_PO is the upper half voltage of the DC bus, and V_dc_ON is the upper and lower half voltage of the DC bus.

[0061] The overcurrent protection module, voltage detection module, and overvoltage buffer module are all electrically connected to the logic control module.

[0062] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A three-level topology pre-charge protection circuit, characterized in that, include: Overcurrent protection module used to reduce the initial surge current at the moment of power-on; A voltage detection module to determine whether pre-charging is complete and to ensure balanced charging of DC bus capacitors; An overvoltage buffer module used to absorb voltage spikes when switching devices are turned off and to suppress electromagnetic interference; A logic control module used to monitor the DC-side capacitor voltage, determine the pre-charge completion status, and output control signals to drive the pre-charge switch; The overcurrent protection module, voltage detection module, and overvoltage buffer module are all electrically connected to the logic control module.

2. The three-level topology pre-charge protection circuit according to claim 1, characterized in that: The overcurrent protection module includes: Pre-charge resistor R1 limits the surge current flowing to the DC bus capacitor; Contactor K1 controls the on / off state of the pre-charge path; Contactor K2 switches the current flow path according to the charging status; DC bus capacitors connected to the DC bus and used for energy storage.

3. The three-level topology pre-charge protection circuit according to claim 2, characterized in that: One end of the pre-charge resistor R1 is connected to the positive terminal of the DC bus through a rectifier bridge. The main contact of the contactor K1 is connected in parallel with the normally closed contact of the contactor K2. The other end of the pre-charge resistor R1 is connected to the wiring terminals of the main contact of the contactor K1 and the normally closed contact of the contactor K2. The two ends of the main contacts of contactor K2 are respectively connected to the main contacts of contactor K1 and the positive terminal of the DC bus.

4. The three-level topology pre-charge protection circuit according to claim 1, characterized in that: The DC bus capacitor includes capacitor C1 and capacitor C2. Capacitor C1 is connected between the positive terminal and the midpoint of the DC bus, and capacitor C2 is connected between the negative terminal and the midpoint of the DC bus.

5. The three-level topology pre-charge protection circuit according to claim 1, characterized in that: The voltage detection module includes a MOSFET Q2 and a transistor U2. A resistor R22 is connected between the gate of the MOSFET Q2 and the collector of the transistor U2. A resistor R12 is also connected to the gate of the MOSFET Q2. The drain of the MOSFET Q2 and the resistor R12 are both connected to the power supply voltage.

6. The three-level topology pre-charge protection circuit according to claim 5, characterized in that: A resistor R42 is connected between the base and emitter of the transistor U2. A diode D2 connected to the enable terminal of the logic control module is connected to the base of the transistor U2. A resistor R32 and a parallel resistor R52 and a capacitor C12 are connected between the source of the MOSFET Q2 and the emitter of the transistor U2.

7. The three-level topology pre-charge protection circuit according to claim 1, characterized in that: The overvoltage buffer module includes a chip U1, a MOSFET Q1, and a transistor Q21. A capacitor C11 and a resistor R1 are connected between pins 1 and 2 of the chip U1, and a capacitor C21 is connected between pins 1 and 3 of the chip U1. A resistor R4 and a resistor R5 are connected between the gate of the MOSFET Q1 and the base of the transistor Q21. The drain of the MOSFET Q1 and the emitter of the transistor Q21 are both connected to pin 3 of the chip U1.