semiconductor structure

Abstract

In one embodiment, the semiconductor structure includes a substrate having a plurality of deep trenches oriented along a first direction and a second direction, and a plurality of mesas intermediate in the deep trenches. The semiconductor structure also includes a plurality of capacitor banks, wherein each capacitor bank includes a stack of a plurality of conductive layers and a plurality of node dielectric layers alternately disposed in the deep trenches, and a first conductive plug disposed on a first layer of the conductive layers. The semiconductor structure also includes an isolation wall that penetrates the stack of conductive layers and node dielectric layers and enters at least one of the mesas. In a top view, the isolation wall is a closed loop.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure. Background Technology

[0002] Capacitors are incorporated into semiconductor wafers for many applications, such as power supply stabilization. However, manufacturing such capacitors typically requires a large device area. Therefore, there is a need for capacitors that can provide high capacitance while having a small device footprint. Utility Model Content

[0003] Some embodiments disclosed herein provide a semiconductor structure. The semiconductor structure includes a substrate having a plurality of deep trenches oriented along a first direction and a second direction, and a plurality of mesas intermediate in the deep trenches; a plurality of capacitor banks, wherein each capacitor bank includes a stack of a plurality of conductive layers and a plurality of node dielectric layers alternately disposed in the deep trenches, and a first conductive plug disposed on a first layer of the conductive layers; and an isolation wall penetrating the stack of conductive layers and node dielectric layers and entering at least one of the mesas, wherein, in a top view, the isolation wall is a closed loop.

[0004] Some embodiments disclosed herein provide a semiconductor structure. The semiconductor structure includes a substrate comprising a plurality of first deep trenches oriented along a first direction and a plurality of second deep trenches oriented along a second direction perpendicular to the first direction; a first capacitor bank including a first core region and a first peripheral region surrounding the first core region, wherein the first capacitor bank includes a plurality of first capacitor cells located in the first deep trenches of the first core region; a second capacitor bank including a second core region and a second peripheral region surrounding the second core region, and the second capacitor bank includes a plurality of second capacitor cells located in the second deep trenches of the second core region; a first conductive plug landing on the first capacitor bank in the first peripheral region; a second conductive plug landing on the second capacitor bank in the second peripheral region; and an isolation wall laterally surrounding the first capacitor bank and the second capacitor bank.

[0005] Some embodiments disclosed herein provide a semiconductor structure. The semiconductor structure includes a substrate comprising a first number of first deep trenches oriented along a first direction and a first number of second deep trenches oriented along a second direction, wherein the first number is a positive integer; a first capacitor bank formed on the first deep trenches, the first capacitor bank including: a first stack of a plurality of first conductive layers and a plurality of first node dielectric layers alternately disposed in the first number of first deep trenches; and a first conductive plug disposed on one of the first conductive layers; a second capacitor bank formed on the second deep trenches, the second capacitor bank including: a second stack of a plurality of second conductive layers and a plurality of second node dielectric layers alternately disposed in the first number of second deep trenches; and a second conductive plug disposed on one of the second conductive layers; and an isolation wall, in a top view, the isolation wall being a closed loop surrounding a first portion of the first capacitor bank and the second capacitor bank, wherein the first stack of the first conductive layers and the first node dielectric layers is separated from the second stack of the second conductive layers and the second node dielectric layers by the isolation wall outside the closed loop. Attached Figure Description

[0006] The various embodiments disclosed herein can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 A schematic diagram of an exemplary semiconductor package according to some embodiments is illustrated;

[0008] Figure 2 and Figure 3 This is a top view of a deep-trench-capacitor (DTC) structure according to some embodiments of the present disclosure;

[0009] Figures 4 to 7 The illustrations depict methods at various stages of manufacturing deep trench capacitor (DTC) structures according to some embodiments of this disclosure; and

[0010] Figures 8 to 10 This is a top view of a deep trench capacitor (DTC) structure according to some embodiments of the present disclosure.

[0011] [Symbol Explanation]

[0012] 100: Semiconductor Packaging

[0013] 101: Packaging substrate

[0014] 102: Intermediary Layer

[0015] 104: Grain stacking

[0016] 106a, 106b, 106c, 106d: wafers

[0017] 112: Substrate portion

[0018] 114: Intermediate Layer Multilayer Interconnect Structure / MLI Structure

[0019] 118: TSV / Through Silicon Via

[0020] 120, 120A, 120B, 120C, 120D, 120E: DTC structure / deep trench capacitor structure; 122: bump.

[0021] 124: Microbumps

[0022] 130: Bottom grain

[0023] 132: Top grain

[0024] 200:Substrate

[0025] 205, 205A, 205B: Deep trenches

[0026] 210A, 210B, 1010A, 1010B, 1010C: Capacitor Bank

[0027] 210: Capacitor Area / Capacitor Bank

[0028] 220, 320: Outer boundary

[0029] 230: Core Area

[0030] 235,335: Surrounding Area

[0031] 240, 340, 340A, 340B: Conductive plugs

[0032] 310, 310A, 310B: Capacitor bank

[0033] 330: Area

[0034] 350, 850, 950, 1050, 1055: Separation wall

[0035] 401: Countertop

[0036] 500: Dielectric Pad

[0037] 510: Alternating layer stacking

[0038] 520A, 520B, 520C, 520D: Conductive layer

[0039] 530A, 530B, 530C: Node dielectric layers

[0040] 540: Covering dielectric material layer / dielectric layer

[0041] 545: Dielectric filler layer / dielectric layer

[0042] 550: Capacitor Unit

[0043] 620: Dielectric layer

[0044] 624: Conductive via

[0045] 626: Barrier Layer

[0046] 628,751: Insulation layer

[0047] 752: Padding

[0048] 815, 815A, 815B, 915, 915A, 915B, 1015, 1025: DTC unit cells; 1091, 1092, 1093: direction.

[0049] A-A': Cross-section line

[0050] B: Back

[0051] F: Front

[0052] L: Length

[0053] S1, S2, S3: Spacing

[0054] W1, W2: Width

[0055] X, Y, Z: Direction

[0056] XY: Plane Detailed Implementation

[0057] The following disclosure provides many different embodiments or examples of configurations to achieve different features of the subject matter of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely exemplary and not intended to limit this disclosure. For example, as described later, forming a first feature over a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples of the drawings. Such repetition of reference numerals and / or letters is for simplicity and clarity and is not in itself intended to limit the relationship between the various embodiments and / or configurations described.

[0058] Furthermore, for ease of description, spatially related terms such as “below,” “under,” “lower,” “above,” and “upper” may be used in this disclosure to describe an element or feature relative to another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptions used in this disclosure may be interpreted similarly and accordingly.

[0059] Other features and processes may also be included in this disclosure. For example, test structures may be included to assist in verifying and testing 3D packages or 3DIC devices. Test structures may include, for example, test pads formed on a redistribution layer or substrate, which allow for testing of 3D packages or 3DICs, probes and / or probe cards, etc. Verification tests can be performed on intermediate and final structures. In addition, the structures and methods disclosed herein can be combined with intermediate verification test methods incorporating known good dies to increase yield and reduce costs.

[0060] Capacitors are used for a variety of purposes in modern integrated circuits (ICs). For example, decoupling capacitors are configured to decouple one part of a circuit (such as an interconnect) from another part of the circuit. In such a configuration, noise generated by the interconnect can be shunt by the decoupling capacitor to reduce the impact of interconnect noise on the rest of the circuit. Because such capacitors are typically placed close to the circuit to eliminate parasitic inductance and resistance associated with interconnects, high-density capacitors are required in the IC technology or discrete process being studied, thus enabling easy mounting of integrated capacitor devices on the IC.

[0061] The miniaturization of devices on modern integrated circuits has presented challenges for circuit designers working with power delivery networks (PDNs, also known as distribution networks). The past decade has witnessed the rise of non-planar devices (such as FinFETs or nanoFETs), which offer higher drive strength compared to planar devices. The use of non-planar devices increases drive strength per unit area and requires higher current density and larger current transients. This trend makes chips increasingly sensitive to power supply voltage fluctuations, exacerbating the challenges of power integrity in system design. Circuit designers rely on decoupling capacitors as a fundamental tool to reduce PDN impedance and suppress noise by decoupling or bypassing one part of the circuit from another. For signals, noise from interconnects can be shunted by decoupling capacitors before being passed to another circuit. However, decoupling capacitors are typically placed physically close to the desired circuitry to reduce parasitic resistance and inductance.

[0062] On the other hand, packaging technology is rapidly evolving, providing more platforms for employing advanced capacitor technologies. As discussed later, advanced capacitor technologies can be integrated with advanced packaging technologies, such as chip-on-wafer-on-substrate (CoWoS) and system-on-integrated-chip (SoIC) technologies. These advanced packaging technologies enable the application of advanced capacitor technologies.

[0063] Packaging technology was once considered a mere back-end process, largely causing inconvenience. Times have changed. Computing workloads have grown in the last decade more than in the last forty. Cloud computing, big data analytics, artificial intelligence (AI), neural network training, AI inference, mobile computing on advanced smartphones, and even self-driving cars are all pushing the limits of computing. Modern workloads have propelled packaging technology to a position of critical innovation, making it essential for product performance, functionality, and cost. These modern workloads are driving product design to adopt more comprehensive, system-level optimization approaches.

[0064] Wafer-on-Wafer-on-Semiconductor (CoWoS) is a wafer-level multi-die packaging technology. CoWoS is a packaging technology that integrates multiple wafers side-by-side on a silicon interposer to achieve better interconnect density and performance. For example, individual wafers are bonded together using microbumps on the silicon interposer to form a wafer-on-wafer (CoW) structure. The CoW structure is then thinned to expose through-silicon vias (TSVs), and bumps (e.g., C4 bumps) are formed and diced. The CoW structure is then bonded to a packaging substrate to form a CoWoS structure. Because multiple wafers or dies are typically combined side-by-side, CoWoS is considered a 2.5-dimensional (2.5D) wafer-level packaging technology.

[0065] On the other hand, the plurality of wafers bonded to the interposer layer in the CoWoS structure can each comprise stacked dies or small wafers (i.e., modular dies) having multiple layers, multiple wafer sizes, and multiple functions. In one embodiment, a direct bonding technique is used to bond the stacked dies together. This direct bonding is a bumpless bonding technique that includes direct bonding of dielectric layers and direct bonding of metal pads, providing higher integration density, faster speed, and higher bandwidth. In addition to die-to-die bonding, direct bonding can also be used for wafer-to-wafer bonding and die-to-wafer bonding.

[0066] Stacked dies characterized by ultra-high density vertical stacking are sometimes referred to as System-on-Chip (SoIC) technology. SoIC technology enables high performance, low power consumption, and minimal resistance-inductance-capacitance (RLC). SoIC technology integrates active and passive chips separated from a System-on-a-Chip (SoC) into a new integrated SoC system that is electrically identical to the original SoC, achieving better form factor and performance. Therefore, die stacks combined using hybrid bonding are sometimes referred to as SoIC die stacks (“SoIC die stack” and “die stack” are used interchangeably throughout the disclosure).

[0067] Figure 1 A schematic diagram of an exemplary semiconductor package according to some embodiments is illustrated. Figure 1 The illustration shows a semiconductor package 100. Figure 1 In the example shown, the semiconductor package 100 includes an interposer 102, a die stack 104 (e.g., a SoIC die stack), and multiple wafers 106a, 106b, 106c, 106d, and other components. The die stack 104 and the multiple wafers 106a-106d are aligned in the vertical direction (i.e., the Z direction, as shown in the image). Figure 1 As shown), it is located on and bonded to the top surface of the interposer layer 102. The die stack 104 and multiple wafers 106a-106d are arranged side-by-side in a horizontal plane (i.e., the XY plane, as shown). Figure 1 The various locations shown in the diagram. The interposer 102 is further bonded to the package substrate 101.

[0068] Intermediate layer 102 provides an interface substrate between package substrate 101 and die stack 104 or multiple wafers 106a-106d. In some embodiments, package substrate 101 is bonded to another substrate, such as a printed circuit board (PCB). Figure 1 In the example shown, the interposer 102 includes a substrate portion 112 and an interposer multilayer interconnect (MLI) structure 114. The substrate portion 112 includes one or more through-silicon vias (TSVs) 118 extending through the substrate portion 112. Figure 1 In the example shown, a deep trench capacitor (DTC) structure 120 is disposed in the substrate portion 112, and a portion or all of the DTC structure 120 is electrically connected to one or more of the die stack 104 and the plurality of wafers 106a-106d. See below. Figures 4 to 7 To explain the details of DTC structure 120. It should be understood that, Figure 1The semiconductor package 100 shown is one example of the many applications of the DTC structure 120.

[0069] also, Figure 1 The interposer layer 102 shown also includes bumps 122 (e.g., solder bumps, C4 bumps, etc.) and microbumps 124. On the back side of the interposer layer 102 (on Figure 1 (In this context, "B" is used to denote the bump 122), which is configured to bond the interposer 102 to the package substrate 101. It should be understood that the bump 122 is exemplary and not limiting, and other types of bonding techniques may be employed in other embodiments. In some embodiments, each TSV 118 is electrically connected to at least one bump 122.

[0070] On the front of intermediary layer 102 (in) Figure 1 (In the diagram, indicated by "F"), microbumps 124 are configured to bond wafers 106a-106d to the interposer layer 102. It should be understood that microbumps 124 are exemplary and not limiting, and other types of bonding techniques may be employed in other embodiments. Regarding the interface between the interposer layer 102 and the die stack 104, in one embodiment, a direct bonding technique may be used to bond the die stack 104 to the interposer layer 102. In other embodiments, other bonding techniques (e.g., microbumps) may be used to bond the die stack 104 to the interposer layer 102.

[0071] Therefore, the package substrate 101 can be electrically connected to one or more of the die stack 104 and wafers 106a-106d via the interposer layer 102. Exemplary electrical paths include bumps 122, TSVs 118, MLI structures 114, and microbumps 124.

[0072] exist Figure 1In the example shown, the die stack 104 includes a bottom die 130 and a top die 132. A bonding layer is formed on the top surface of the bottom die 130, and another bonding layer is formed on the bottom surface of the top die 132. Pairs of metal bonding pads are formed in these bonding layers. When the top die 132 and the bottom die 130 are bonded together, each pair of metal bonding pads is aligned and in contact with each other in the XY plane, thereby providing an electrical path between the bottom die 130 and the top die 132. Because the metal bonding pads can have a small critical dimension and pitch, the die stack 104 can achieve better interconnect density and performance (e.g., faster speed and higher bandwidth). In some embodiments, the wafers 106a-106d are independent wafers and implement various functions. Each wafer 106a-106d is, for example, a logic wafer, a memory wafer, a computing wafer, a sensor wafer, a radio frequency (RF) wafer, and a high voltage (HV) wafer.

[0073] Figure 2 This is a top view of a deep trench capacitor (DTC) structure according to some embodiments. The DTC structure 120A can be used as... Figure 1 The DTC structure 120. The DTC structure 120A includes multiple capacitor cells (see [link]). Figure 7 The DTC structure 120A may include multiple dielectric layers formed in multiple deep trenches (see [link]). Figure 7 ) and multiple conductive layers (see Figure 7 To form multiple capacitors. For clarity, Figure 2 The dielectric and conductive layers are not shown. In some embodiments, the DTC structure 120A is formed in the substrate 200. The substrate 200 may be as follows: Figure 1 The interposer 102 shown may be any suitable substrate, wafer, or package. In some embodiments, substrate 200 comprises a crystalline semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium phosphide (GaSbP), gallium arsenide (GaAsSb), and indium phosphide (InP). In one embodiment, substrate 200 is made of silicon. In some embodiments, substrate 200 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one embodiment, the insulating layer is an oxygen-containing layer.

[0074] A deep trench 205 is formed in the substrate 200. The deep trench 205 can extend from the top surface of the substrate 200 into the substrate 200. The deep trench 205 may have vertical or inclined sidewalls. Figure 2 As shown, the deep trench 205 may have a width W1 (or the bottom width W1 of the deep trench 205 when the sidewalls are inclined) and a length L. In some embodiments, each deep trench 205 extends laterally with a substantially uniform width, although some deep trenches may have different widths for design purposes. The width W1 of the deep trench 205 may be wide enough to accommodate both the conductive and dielectric layers. The length L may be greater than the width W1. In some embodiments, the width W1 is between about 10 nm and about 2000 nm, and the length L is between about 1 μm and about 10 μm. In some embodiments, the deep trench 205 has an aspect ratio between about 100 and about 1000. In some embodiments, the deep trench 205 has a depth-to-width ratio between about 10 and about 200. Although Figure 2 Only rectangles are shown, but deep trenches 205 in the top view can each be circular, elliptical, rounded rectangle, annular with various shapes of inner and outer perimeters, or any two-dimensional shape that defines a closed volume.

[0075] The deep trench 205 may include a first deep trench 205A and a second deep trench 205B. For example... Figure 2 As shown, the first deep trench 205A has a length direction extending along a first direction (e.g., the X direction), and the second deep trench 205B has a length direction extending along a second direction (e.g., the Y direction), and the second direction is substantially perpendicular to the first direction. That is, the length direction of the first deep trench 205A is substantially perpendicular to the length direction of the second deep trench 205B.

[0076] exist Figure 2 In this context, the DTC structure 120A may further include multiple capacitor banks 210A and multiple capacitor banks 210B (collectively referred to as "capacitor region 210" in the following description). Each capacitor bank 210A may include multiple capacitor cells formed in the first deep trench 205A (see [link to documentation]). Figure 7 Each capacitor bank 210B may include multiple capacitor cells formed in the second deep trench 205A (see [link]). Figure 7 ).exist Figure 2In the example shown, each capacitor bank 210A includes five first deep trenches 205A, and each capacitor bank 210B includes five second deep trenches 205B, but more or fewer first deep trenches 205A and / or second deep trenches 205B may also be used. More specifically, according to some embodiments, each capacitor bank 210A includes five capacitor cells formed in and above the first deep trenches 205A, and each capacitor bank 210B includes five capacitor cells formed in and above the second deep trenches 205B. As will be described in more detail later, the conductive and dielectric layers in each capacitor bank 210 may extend continuously into the deep trenches 205. Therefore, the capacitor cells of the capacitor bank 210 may share the conductive and dielectric layers.

[0077] Capacitor banks 210A and 210B can be alternately arranged as multiple columns and rows extending in the XY plane, such as... Figure 2 As shown. More specifically, capacitor bank 210A and capacitor bank 210B are along... Figure 2 The first direction (e.g., the X direction) alternates laterally. Similarly, capacitor banks 210A and 210B are along... Figure 2 The capacitor bank 210 is arranged laterally in a second direction (e.g., the Y direction). This arrangement of the capacitor bank 210 can effectively reduce the stress generated in the substrate 200, especially when a large area of ​​capacitor bank 210 is applied.

[0078] Conductive plugs 240 are formed to electrically couple capacitor bank 210 to upper interconnects, such as MLI structure 114 of interposer 102 (see [link]). Figure 1 In some embodiments, at least some conductive layers of capacitor bank 210 include portions extending beyond the occupied area (hereinafter referred to as "core region 230") of deep trench 205 to allow conductive plugs 240 to land on portions outside the occupied area (hereinafter referred to as "landing portions"). That is, the outer boundary 220 of capacitor bank 210 may be defined as the landing portion including the conductive layers of capacitor bank 210. For example, as Figure 2 As shown, capacitor bank 210 may have a rectangular outer boundary 220, but may adopt other shapes for different design purposes. The outer boundary 220 is larger than the core area 230 occupied by the deep trench 205. In other words, in addition to the core area 230 occupied by the deep trench 205, each capacitor bank 210 may also require a peripheral area 235 to allow conductive plugs 240 to land on the peripheral area 235. In some embodiments, conductive plugs 240 include a plurality of conductive plugs of different depths, configured to be bonded to different layers of conductive layers, thus requiring the landing portions of the different conductive layers to be spaced apart from each other. Therefore, when using multiple conductive layers, capacitor bank 210 may require a large peripheral area 235 to accommodate these landing portions of the conductive layers.

[0079] In some embodiments, the peripheral region 235 may have a width W2. Adjacent core regions 230 of capacitor banks 210A and 210B may have a spacing S1 (along a first direction or along a second direction), which may be approximately twice the width W2. According to some embodiments, although any two of the first deep trenches 205A (or any two of the second deep trenches 205B) are separated by a spacing S2, the spacing S1 is at least about five times larger than the spacing S2. As the critical dimensions of the wafer or package continue to shrink, it is necessary to reduce the spacing S1 to achieve higher density capacitor banks.

[0080] Figure 3 This is a top view of a deep trench capacitor (DTC) structure 120B according to some embodiments. The DTC structure 120B and... Figure 2 The DTC structure shown is similar to the 120A and features a high-density capacitor bank. Figure 3 For clarity, the dielectric and conductive layers of capacitor bank 310 are not shown in the diagram. Figure 3 In some embodiments shown, the conductive plug 340 engages in the core region 230 of the capacitor bank 310, for example, in the core region 230 of capacitor bank 310A and / or the core region 230 of capacitor bank 310B, rather than in the peripheral region 235 of the capacitor bank 210. In some embodiments, in a top view, each conductive plug 340 does not overlap with the deep trench 205. For example, the conductive plug 340 lands between adjacent deep trenches 205 (e.g., between two adjacent first deep trenches 205A and / or between two adjacent second deep trenches 205B). This reduces the width of the peripheral region 335 of the capacitor. For example, in Figure 3 In the DTC structure 120B, the capacitor bank 210A and the adjacent core regions 230 of the capacitor bank 210B may have a spacing S3 (along a first direction or a second direction). In some embodiments, the spacing S3 is reduced to be less than the spacing S2. In some embodiments, the ratio S3 / S2 of the spacing S3 to the spacing S2 is between about 0.5 and about 1.5. In this way, the capacitor bank 310 can be larger than the capacitor bank 210 (e.g., ...). Figure 2 (As shown) to set a higher density. For example... Figure 3 As shown, region 330 represents DTC structure 120B and Figure 2 The area that can be saved compared to the DTC structure 120A shown is [amount missing].

[0081] Please continue reading. Figure 3In some embodiments, isolation walls 350 are provided to sufficiently reduce or prevent signal interference between adjacent capacitor banks 210. In a top view, isolation walls 350 may be a closed loop, and may contain multiple sub-closed loops. Isolation walls 350 may be disposed between peripheral regions 335 of capacitor banks 310, or the outer boundary 320 of capacitor banks 210 may be defined by isolation walls 350. For example, according to some embodiments, each capacitor bank 310 is laterally surrounded by isolation walls 350. In this way, capacitor banks 310 can be electrically isolated from each other by isolation walls 350 (if capacitor banks 310 are not electrically coupled through upper interconnects).

[0082] Figures 4 to 7 The illustration depicts methods of manufacturing deep trench capacitor (DTC) structures at various stages according to some embodiments of the present disclosure. In some embodiments, Figures 4 to 7 The method illustrates the configuration in manufacturing such as Figure 3 The method of DTC structure 120B shown. Figures 4 to 7 The reference section line A-A' shown in DTC structure 120B is illustrated, where section line A-A' is along a line perpendicular to the plane. Figure 3 The longitudinal direction of the first deep trench 205A shown.

[0083] exist Figure 4 In this embodiment, substrate 200 includes a plurality of deep trenches 205 (e.g., a first deep trench 205A) and a plurality of mesa 401 interposed between two adjacent deep trenches 205. The deep trenches 205 can be formed by forming a patterned mask layer on the front surface of substrate 200. The pattern in the patterned mask layer can be transferred to the upper part of substrate 200. Prior to forming the patterned mask layer, an optional pad dielectric layer (not shown) (e.g., a silicon oxide pad layer) can be formed on the front surface (i.e., the top surface) of substrate 200. In an exemplary embodiment, the pad dielectric layer may include a silicon oxide layer with a thickness between 20 nm and 100 nm, but thicker or thinner pad dielectric layers may also be used.

[0084] The patterned mask layer may include a silicon nitride layer or a borosilicate glass (BSG) layer with a thickness between 200 nm and 600 nm, but different materials and / or smaller or larger thicknesses may also be applied to the optional pad dielectric layer and patterned mask layer. The patterned mask layer can be formed by depositing a cover mask layer, forming a photoresist layer over the cover mask layer, and transferring the pattern of the photoresist layer to the cover mask layer using an anisotropic etching process (e.g., reactive ion etching).

[0085] An anisotropic etching process can be performed to transfer a pattern from a patterned etch mask layer to the upper part of the substrate 200 to form a deep trench 205. For example, a reactive ion etching process comprising a combination of gases including HBr, NF3, O2, and SF6 can be used to form the deep trench 205. The depth of the deep trench 205 can be between 2 micrometers and 20 micrometers, for example, between 3 micrometers and 10 micrometers, but deeper or shallower trenches can also be used. In some embodiments, the deep trench 205 has an aspect ratio between about 10 and about 200. Generally, the deep trench 205 can be formed in the substrate 200, for example, extending downward from the top surface of the substrate 200 into the substrate 200.

[0086] The photoresist layer can be removed before the anisotropic etching process that forms the deep trench 205, or it can be consumed during the anisotropic etching process that forms the deep trench 205. The patterned etch mask layer and optional pad dielectric layer can then be removed by a suitable anisotropic etching process (e.g., wet etching process).

[0087] exist Figure 5 In this embodiment, a dielectric pad 500 may be formed on the physically exposed surface of the substrate 200, including the top surface of the substrate 200 and the sidewalls of the deep trench 205. In some embodiments, the dielectric pad 500 includes a dielectric material capable of providing electrical isolation between the substrate 200 and a conductive layer subsequently formed in the deep trench 205. The dielectric pad 500 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxide, or other suitable materials within the disclosed intended range. In an illustrative example, the dielectric pad 500 may include a silicon oxide layer formed by thermal oxidation of a surface portion of the silicon-containing substrate 200. In some embodiments, the dielectric pad 500 is formed by CVD, ALD, PVD, or other suitable deposition methods. The thickness of the dielectric pad 500 may be between 4 nm and 100 nm, but smaller and larger thicknesses are also possible.

[0088] In some embodiments, conductive and dielectric layers may be alternately disposed in the deep trench 205. For example, an alternating layer stack 510 of conductive layers 520A, 520B, 520C, and 520D and node dielectric layers 530A, 530B, and 530C may be formed in and above the deep trench 205. More specifically, the alternating layer stack 510 may include conductive layers 520A, 520B, 520C, and 520D, respectively, interleaved with the node dielectric layers 530A, 530B, and 530C. The alternating layer stack 510 may extend continuously above the top surface of the substrate 200 (e.g., the top surface of the mesa 401) and into each deep trench 205.

[0089] Each conductive layer 520A, 520B, 520C, and 520D may comprise a metallic material, and may comprise and / or be substantially composed of a conductive metal nitride, an elemental metal, or an intermetallic alloy. In some embodiments, conductive layers 520A, 520B, 520C, and 520D comprise a conductive metal nitride material and / or are substantially composed of a conductive metal nitride material, and may be a metal diffusion barrier material. For example, each conductive layer 520A, 520B, 520C, and 520D may comprise a conductive metal nitride material (e.g., TiN, TaN, or WN) and / or may be substantially composed of a conductive metal nitride material. Other suitable materials within the disclosed contemplated scope may also be used.

[0090] It may be advantageous to incorporate metal diffusion barrier materials into conductive layers 520A, 520B, 520C, and 520D, as diffusion of metal elements through node dielectric layers 530A, 530B, and 530C and / or through dielectric pad 500 can have detrimental effects on deep trench capacitors. Conductive layers 520A, 520B, 520C, and 520D can be formed using conformal deposition processes, such as PVD, CVD, or ALD. The thickness of each conductive layer 520A, 520B, 520C, and 520D can be between 5 nm and 50 nm, for example, between 10 nm and 30 nm, but smaller and larger thicknesses are also possible. In some embodiments, conductive layers 520A, 520B, 520C, and 520D have the same material composition and the same thickness. In some embodiments, conductive layers 520A, 520B, 520C, and 520D have the same material composition but different thicknesses. In some embodiments, conductive layers 520A, 520B, 520C, and 520D have different material compositions and the same thickness.

[0091] Each node dielectric layer 530A, 530B, and 530C may include a node dielectric material, which may be a dielectric metal oxide material having a dielectric constant greater than 7.9 (which is the dielectric constant of silicon nitride), i.e., a "high-k" dielectric metal oxide material, or may include silicon nitride. For example, each node dielectric layer 530A, 530B, and 530C may include a dielectric metal oxide material such as alumina, hafnium oxide, zirconium oxide, tantalum oxide, lanthanum oxide, alloys thereof, or silicates thereof, and / or stacks thereof. In some embodiments, node dielectric layers 530A, 530B, and 530C include alumina. Other suitable materials within the disclosed contemplated range may also be used.

[0092] Each node dielectric layer 530A, 530B, and 530C can be formed using a conformal deposition process, such as CVD or ALD. The thickness of the node dielectric layers 530A, 530B, and 530C can be between 1 nm and 20 nm, for example, between 3 nm and 12 nm, but smaller and larger thicknesses are also possible. In some embodiments, the node dielectric layers 530A, 530B, and 530C have the same material composition and the same thickness. In some embodiments, the node dielectric layers 530A, 530B, and 530C have the same material composition but different thicknesses. In some embodiments, the node dielectric layers 530A, 530B, and 530C have different material compositions and the same thickness. In some embodiments, the node dielectric layers 530A, 530B, and 530C have different material compositions and different thicknesses.

[0093] While this disclosure describes an embodiment using alternating layer stacks 510 comprising four conductive layers and three node dielectric layers, including conductive layers 520A, 520B, 520C, and 520D and node dielectric layers 530A, 530B, and 530C, this disclosure explicitly describes embodiments in which different numbers of conductive layers and different numbers of node dielectric layers can also be used in the alternating layer stack 510. Generally, the alternating layer stack 510 may include at least three conductive layers interleaved with at least two node dielectric layers, which may be formed in and above at least one deep trench 205 formed in the substrate 200. In some other embodiments, the total number of conductive layers may be between 3 and 16, for example, between 4 and 8. The total number of node dielectric layers may be one less than the total number of conductive layers.

[0094] A cover dielectric layer 540 and a dielectric filler layer 545 may be selectively deposited over the alternating layer stack 510. The cover dielectric layer 540 may include the same material as the node dielectric layers 530A, 530B and 530C, and may have a thickness between 1 nm and 20 nm, for example between 3 nm and 12 nm, but smaller and larger thicknesses may also be used.

[0095] A dielectric filler layer 545 may be deposited on top of a covering dielectric layer 540 or an alternating layer stack 510 to fill any remaining cavity volume in the deep trench 205. In one embodiment, the dielectric filler layer 545 comprises doped silicate glass or doped silicate glass, and / or is substantially composed of undoped silicate glass or doped silicate glass. A planarization process (e.g., chemical mechanic polishing, CMP) may be performed on the deposited dielectric filler layer 545 to provide a planarized top surface for the dielectric filler layer 545.

[0096] After forming the dielectric filler layer 545, a DTC structure 120B is formed. For example, the DTC structure 120B may include a dielectric pad 500, an alternating layer stack 510, a covering dielectric layer 540, and a dielectric filler layer 545. In some embodiments, the portion of the DTC structure 120B filled in and above the deep trench 205 may be considered a capacitor cell 550. In some embodiments, the capacitor cell 550 may have a similar width and a similar length to the corresponding deep trench 205. Although Figure 5 Only capacitor cells 550 are shown formed in the first deep trench 205A, but capacitor cells 550 may also fill the second deep trench 205B. Therefore, each capacitor cell 550 may have a length direction extending along the length direction of the deep trench 205, such as extending along a first direction (e.g., the X direction) or along a second direction (e.g., the Y direction).

[0097] According to some embodiments, after forming the dielectric filling material layer 545, a dielectric layer 620 is formed over the dielectric filling material layer 545. In some embodiments, the dielectric layer 620 comprises one or more layers of dielectric material. The dielectric layer 620 may include silicon oxide, spin-coated glass, spin-coated polymer, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), or a low-k dielectric material (e.g., SiO2). x C y (or combinations thereof), and can be formed by any suitable method, such as spin coating, CVD, ALD, or combinations thereof.

[0098] Please see Figure 6 According to some embodiments, a conductive plug 340 is formed in the dielectric layer 620 and electrically coupled to one or more of the conductive layers 520A-520D of the alternating layer stack 510. The conductive plug 340 may penetrate the dielectric layer 620, the dielectric filler layer 545, and the covering dielectric layer 540 to be electrically coupled to one or more of the conductive layers 520A-520D of the alternating layer stack 510. For example, in Figure 6The diagram illustrates two conductive plugs 340A and 340B with different depths, but more or fewer conductive plugs of various depths may also be used. In some embodiments, conductive plugs 340A and 340B land on conductive layers 520C and 520D, respectively. Conductive plugs 340 may be laterally aligned with mesa 401 to avoid damaging capacitor cells 550 in and above the deep trench 205. In some embodiments, each conductive plug 340 lands on a different mesa 401. In some embodiments, more than one conductive plug 340 lands on the same mesa 401 (e.g., arranged in a row along a second direction when the mesa has a length direction along the second direction).

[0099] In some embodiments, the conductive plug 340 includes a conductive via 624, an optional barrier layer 626, and an insulating layer 628. The conductive plug 340 can be formed using any suitable method, such as an embedding method. For example, forming the conductive plug 340 may include forming openings in the dielectric layers; depositing the insulating layer 628 within the openings; etching the insulating layer 628 to expose the underlying multilayers; optionally depositing the barrier layer 626; and filling the openings with a conductive material to form the conductive via 624. According to some embodiments, a seed layer may be deposited prior to forming the conductive material. In some embodiments, the conductive via 624 includes copper, aluminum, tungsten, cobalt, alloys thereof, or combinations thereof, and can be formed using PVD, CVD, ALD, electroplating, or combinations thereof. The barrier layer 626 includes titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof. In some embodiments, chemical mechanical polishing (CMP) may be performed to remove excess material from the dielectric layers, barrier layers, adhesion layers, seed layers, and conductive material that has overfilled the vias. In some embodiments, an additional dielectric layer (not shown) and an additional metal interconnect structure (not shown) are formed over the dielectric layer 620 and the conductive plug 340.

[0100] Since conductive plugs 340A and 340B land on corresponding conductive layers 520C and 520D, the openings of conductive plugs 340A and 340B are formed to a corresponding depth to expose the corresponding conductive layers 520C and 520D. One way to achieve this structure is to form the openings of conductive plugs 340A and 340B in separate processes. The dielectric layer 620 is patterned at least twice to form the corresponding openings. These patterning processes may each include a lithography process and an etching process. After the patterning processes, the openings are formed to expose the respective conductive layers. For example, the opening for forming conductive plug 340B may be formed after the opening for conductive plug 340A, or vice versa. After forming the openings of conductive plugs 340A and 340B, a barrier layer 626 and a conductive via 624 are sequentially disposed in the openings of conductive plugs 340A and 340B.

[0101] In some embodiments, the etching process includes a dry etching process using an etchant containing fluorine, chlorine, or a combination thereof, such as silicon tetrafluoride (SiF4) or silicon-fluorine based SiF4. x (x is 1, 2, or 3), silicon tetrachloride (SiCl4), silicon chloride-based SiCl x (x is 1, 2, or 3), or a combination thereof, to etch dielectric layer 620, dielectric filler layer 545, cover dielectric layer 540, and node dielectric layers 530A, 530B, and 530C. In some embodiments, the etching process further includes a dry etching process using an etchant comprising Cl2, BCl3, other suitable etchants, or combinations thereof, to etch one or more conductive layers 520B-520D (if desired). When the opening passes through multiple layers, the etchant can be changed during a single etching process depending on the material of the layer to be etched. For example, in an etching process forming an opening configured in conductive plug 340A, after etching through dielectric layers 620, 545, and 540, the etchant can be changed to an etchant suitable for etching conductive layer 520D, and then the etchant can be changed to an etchant suitable for etching node dielectric layer 530C.

[0102] In some embodiments, an insulating layer 628 is deposited in the openings to be formed in the conductive plugs 340A and 340B before the conductive vias 624 and the barrier layer 626 are formed. Figure 6 In this configuration, insulating layer 628 is the outer wall of conductive plug 340 to provide electrical isolation from one or more of the conductive layers 520A-520D. For example, conductive plug 340A is designed to be electrically coupled to conductive layer 520C, while insulating layer 628 can prevent conductive via 624 of conductive plug 340A from being electrically coupled to conductive layer 520D.

[0103] Please see Figure 7A dry etching process is performed to form trenches in dielectric layer 620 and through alternating layer stack 510. In some embodiments, the trenches extend into mesa 401 of substrate 200. In some embodiments, the trenches extend into dielectric pads 500. An insulating layer 751 and optionally a pad 752 are deposited in the trenches to form isolation walls 350. Insulating layer 751 is formed of an insulating material, such as a low-k dielectric material described for dielectric layer 620, silicon oxide, silicon oxynitride, other suitable dielectric materials, or combinations thereof. In some embodiments, insulating layer 751 is a different material from dielectric layer 620, but similar or the same material may also be used. Pad 752 may include silicon nitride, silicon oxynitride, dielectric metal oxide, or combinations thereof. In some embodiments, pad 752 may have a different material than insulating layer 751 and / or dielectric layer 620. In some embodiments, the dry etching process configured in the trenches forming isolation walls 350 is similar to the etching process configured in the openings forming conductive plugs 340.

[0104] The isolation wall 350 can cut each of the dielectric pad 500, the alternating layer stack 510, the covering dielectric material layer 540, the dielectric filler material layer 545, and the dielectric layer 620 into separate portions. In some embodiments, such as Figure 3 As shown, the isolation wall 350 may surround one or more capacitor banks 310. In other words, since the conductive layers 520A-520D are cut by the isolation wall 350, one or more capacitor banks 310 may be isolated from another one or more capacitor banks 310 (if not electrically connected via an upper layer interconnect). In some embodiments, the width of the isolation wall 350 exceeds at least 50% of the width of the top surface of the platform 401 on which the isolation wall 350 is located, thereby providing sufficient isolation between two adjacent capacitor banks 310. In some embodiments, the isolation wall 350 covers at least half of the top surface of the platform 401. In this example, the conductive plugs 340 and the isolation wall 350 may be laterally aligned with different platforms 401. In some embodiments, the isolation wall 350 and one or more conductive plugs 340 land on the same platform 401 (e.g., arranged in a row in the second direction when the platform has a length direction along the second direction).

[0105] Figure 8 This is a top view of a deep trench capacitor (DTC) structure according to some embodiments, and Figure 8 The conductive and dielectric layers are not shown. Figure 8 The DTC structure 120C shown is... Figure 3The DTC structure 120B shown is similar. More specifically, a DTC unit cell can be considered as a group of available capacitor banks 310, and in a DTC unit cell, any number of capacitor banks 310 can form a capacitor with a capacitance proportional to the number of capacitor banks 310. Once the design requirements of the wafer to be connected to the DTC structure are known, the size and shape of the DTC cell or the number of capacitor banks 310 to be included in the DTC cell can be calculated accordingly.

[0106] exist Figure 8 The diagram illustrates two DTC unit cells 815A and 815B, whose boundaries can be defined by the shape of the isolation wall 850. DTC unit cell 815A can be formed from a capacitor bank 310B. DTC unit cell 815B can include three capacitor banks, such as two capacitor banks 310A and one capacitor bank 310B. These illustrative examples of DTC unit cells are for illustration only; DTC unit cell 815 can include any number of capacitor banks and any shape, provided it can be defined by a continuous isolation wall 850. When DTC unit cell 815 includes a larger number of capacitor banks 310, DTC unit cell 815 can have a larger capacitance. In some embodiments, DTC unit cell 815B includes three capacitor banks 310 and fifteen capacitor cells 550, and DTC unit cell 815A includes one capacitor bank 310 and five capacitor cells 550. DTC unit 815B may include three times or more of the capacitance of DTC unit 815A.

[0107] In some embodiments, adjacent capacitor banks 310 in DTC unit cell 815B are not cut by isolation wall 850, such that conductive layers 520A-520D, node dielectric layers 530A-530C, cover dielectric layer 540, dielectric filler layer 545, and dielectric layer 620 extend continuously between adjacent capacitor banks 310, for example, extending above the top surface of substrate 200 between adjacent capacitor banks 310. For example, conductive layers 520A-520D, node dielectric layers 530A-530C, cover dielectric layer 540, dielectric filler layer 545, and dielectric layer 620 extend continuously along a first direction between capacitor banks 310B and capacitor banks 310A in DTC unit cell 815B. Furthermore, the conductive layers 520A-520D, the node dielectric layers 530A-530C, the covering dielectric material layer 540, the dielectric filling material layer 545, and the dielectric layer 620 extend continuously along the second direction between the capacitor bank 310B and the capacitor bank 310A in the DTC unit cell 815B. In some embodiments, conductive layers 520A-520D, node dielectric layers 530A-530C, covering dielectric material layer 540, dielectric filling material layer 545, and dielectric layer 620 are cut by an isolation wall 850 outside the DTC unit cell 815B (e.g., outside the closed loop of the DTC unit cell 815B surrounded by the isolation wall 850), and thus, the conductive layers 520A-520D and node dielectric layers 530A-530C disposed in the DTC unit cell 815B are separated from the conductive layers 520A-520D and node dielectric layers 530A-530C disposed outside the DTC unit cell 815B by the isolation wall 850.

[0108] One or more DTC unit cells 815 may contribute to a first functional block of a wafer or package, and other DTC unit cells 815 may contribute to a second functional block or other functional blocks of the wafer or package. In some embodiments, one or more DTC unit cells 815 contribute to a first wafer or a first package, and other DTC unit cells 815 contribute to a second wafer or a second package. Various applications of the DTC unit cells are possible.

[0109] Figure 9 This is a top view of a deep trench capacitor (DTC) structure according to some embodiments. Figure 9 The DTC structure 120D shown is... Figure 3 The DTC structure 120B shown is or Figure 8The DTC structure 120C shown is similar. In a top view, the isolation wall 950 may be a closed loop, and may include one or more sub-closed loops within this closed loop. In some embodiments, the isolation wall 950 extends between two adjacent deep trenches 205 in a single capacitor bank 310. In such embodiments, a DTC unit 915 may have a number of capacitor cells, and not just an integer multiple of five. For example, DTC structure 120D includes two DTC unit units 915A and 915B. DTC unit unit 915A may include the entirety of a capacitor bank 310B and a segment of the capacitor bank 310B. That is, the entirety of a capacitor bank 310B and a segment of the capacitor bank 310B are surrounded by the isolation wall 950 in DTC unit unit 915A. For example, the isolation wall 950 in DTC unit 915A may surround seven deep trenches 205, and DTC unit 915A has seven capacitor cells 550. DTC unit cell 915B may include the entirety of a capacitor bank 310A, the entirety of a capacitor bank 310B, and a segment of the capacitor bank 310A. Specifically, the entirety of a capacitor bank 310B and a segment of the capacitor bank 310A are surrounded by isolation walls 950 in DTC unit cell 915B. For example, the isolation walls 950 in DTC unit cell 915B may surround thirteen deep trenches 205, and DTC unit cell 915A has thirteen capacitor cells 550. In this type of embodiment, a capacitor bank 310 can be divided into separate portions to contribute to different DTC unit cells, thus allowing designers greater flexibility in designing the shapes of various DTC unit cells and how each chip uses the DTC unit cell 915. Redundant capacitor cells 550 can be reduced or avoided, allowing designers to utilize the space of the DTC structure 120D more effectively. The example illustration of DTC unit 915 is for illustrative purposes only. DTC unit 915 may include any number of capacitor banks and any shape, provided that it can be defined by a continuous isolation wall 950.

[0110] Figure 10 This is a top view of a deep trench capacitor (DTC) structure according to some embodiments of the present disclosure. Figure 10 The DTC structure 120E shown is... Figure 3 The DTC structure 120E shown is... Figure 8 The DTC structure shown is 120C or Figure 9The DTC structure 120D shown is similar. DTC structure 120E includes multiple DTC unit cells, such as at least DTC unit cells 1015 and 1025. Both DTC unit cells 1015 and 1025 can include capacitor banks 1010A, 1010B, and 1010C with hexagonal boundaries (hexagonal outlines). The spacing between any two capacitor banks 1010A, 1010B, and 1010C is the same, for example, spacing S2. Capacitor bank 1010A has a third deep trench oriented longitudinally along direction 1091. Capacitor bank 1010B has a fourth deep trench oriented longitudinally along direction 1092. Capacitor bank 1010C has a fifth deep trench oriented longitudinally along direction 1093. Directions 1091, 1092, and 1093 are different from each other. In this example, at least one of capacitor banks 1010A, 1010B, and 1010C has seven deep trenches. The deep trenches in capacitor banks 1010A, 1010B, and 1010C are parallel to each other and extend along one of three directions 1091, 1092, and 1093. In this example, the angle between any two of the three directions 1091, 1092, and 1093 is 120 degrees. The middle deep trench in each of capacitor banks 1010A, 1010B, and 1010C is longer than the other deep trenches. In other words, in each capacitor bank 1010A, 1010B, and 1010C, the middle deep trench is the longest. The two outermost deep trenches are of equal length and are the shortest. Since capacitor banks 1010A, 1010B and 1010C have three different extension directions 1091, 1092 and 1093, the stress generated by the high-density trenches in the large wafer area has components in three directions, thereby reducing wafer warpage.

[0111] exist Figure 10 In this embodiment, the shapes and dimensions of DTC unit cells 1015 and 1025 are defined by isolation walls 1050 and 1055, respectively. Isolation walls 1050 and 1055 are similar to isolation wall 850 and can be formed from similar materials and in a similar manner. In a top view, isolation walls 1050 and 1055 may each be a closed loop, and each closed loop may include one or more sub-closed loops within the closed loop. In some embodiments, isolation wall 1050 extends through capacitor bank 1010A by extending between two adjacent deep trenches in capacitor bank 1010A, thereby separating capacitor bank 1010A. Although isolation wall 1055 only surrounds the outer boundaries of capacitor banks 1010A, 1010B, and 1010C, DTC unit cell 1025 includes the entirety of the capacitor banks, such as four capacitor banks.

[0112] The embodiments disclosed herein provide a semiconductor structure including a high-density DTC structure. In the DTC structure, conductive plugs can land on a conductive layer between adjacent deep trenches in a capacitor bank. This effectively reduces the area of ​​the surrounding region. In some embodiments, adjacent capacitor banks can be electrically isolated by isolation walls. Isolation walls allow designers to design the shape and size of the DTC cells. Isolation walls can surround the outer boundary of the capacitor bank or extend through the capacitor bank, thus enabling designers to arrange the DTC cells more flexibly and efficiently.

[0113] In one embodiment, the semiconductor structure includes a substrate having a plurality of deep trenches oriented along a first direction and a second direction, and a plurality of mesas intermediate in the deep trenches; a plurality of capacitor banks, wherein each capacitor bank includes a stack of a plurality of conductive layers and a plurality of node dielectric layers alternately disposed in the deep trenches, and a first conductive plug disposed on a first layer of the conductive layers; and an isolation wall penetrating the stack of conductive layers and node dielectric layers and entering at least one of the mesas, wherein, in a top view, the isolation wall is a closed loop. In one embodiment, the semiconductor structure further includes a second conductive plug disposed on a second layer of the conductive layers, wherein the second layer of the conductive layers is located below the first layer of the conductive layers. In one embodiment, the second conductive plug has a bottom physically contacting the second layer of the conductive layers and a sidewall physically contacting the first layer of the conductive layers. In one embodiment, the second conductive plug includes an insulating layer and conductive vias laterally surrounded by the insulating layer. In one embodiment, in a top view, the isolation wall extends between two adjacent capacitor banks. In one embodiment, in a top view, the isolation wall surrounds two or more of the capacitor banks. In one embodiment, the first spacing between two adjacent capacitor banks is less than or equal to the second spacing between two adjacent deep trenches.

[0114] In one embodiment, a method of forming a semiconductor structure includes: forming a plurality of deep trenches and a plurality of mesas intermediate in the deep trenches in a substrate; forming a stack of a plurality of conductive layers and a plurality of node dielectric layers alternately disposed in the deep trenches; forming a first conductive plug connected to a first layer of the conductive layers; and forming an isolation wall penetrating the stack of conductive layers and node dielectric layers and entering at least one of the mesas, wherein, in a top view, the isolation wall is a closed loop. In one embodiment, the method further includes: forming a cover dielectric material layer on the stack; forming a dielectric fill material layer on the cover dielectric material layer, wherein the dielectric fill material layer has a flat top surface; and forming a dielectric layer on the dielectric fill material layer. In one embodiment, forming the first conductive plug includes: forming a first opening penetrating a second layer of the conductive layers and a node dielectric layer; forming an insulating layer in the first opening, wherein the insulating layer is in physical contact with the first and second conductive layers; etching the insulating layer in the first opening to expose the first layer of the conductive layers; and forming a conductive material in the first opening. In one embodiment, the method further includes connecting a second conductive plug to a second layer of the conductive layer, wherein forming the second conductive plug includes: forming a second opening after forming a first opening and before forming an insulating layer; forming an insulating layer in the second opening; etching the insulating layer in the second opening to expose the second layer of the conductive layer; and forming a conductive material in the second opening. In one embodiment, in a top view, an isolation wall extends between two adjacent capacitor banks. In one embodiment, the isolation wall is formed after forming the first conductive plug.

[0115] In one embodiment, a semiconductor structure includes a substrate comprising a first number of first deep trenches oriented along a first direction and a first number of second deep trenches oriented along a second direction, wherein the first number is a positive integer; a first capacitor bank formed on the first deep trenches, the first capacitor bank comprising: a first stack of a plurality of first conductive layers and a plurality of first node dielectric layers alternately disposed in the first number of first deep trenches; and a first conductive plug disposed on one of the first conductive layers; a second capacitor bank formed on the second deep trenches, the second capacitor bank comprising: a second stack of a plurality of second conductive layers and a plurality of second node dielectric layers alternately disposed in the first number of second deep trenches; and a second conductive plug disposed on one of the second conductive layers; and an isolation wall, which, in a top view, is a closed loop surrounding a first portion of the first capacitor bank and the second capacitor bank, wherein the first stack of the first conductive layers and the first node dielectric layers is separated from the second stack of the second conductive layers and the second node dielectric layers by the isolation wall outside the closed loop. In one embodiment, the isolation wall includes a first portion extending between two adjacent second deep trenches in a top view. In one embodiment, the isolation wall further includes a second portion extending in a top view between two adjacent first deep trenches and second deep trenches. In one embodiment, in a top view, the isolation wall surrounds a first number of second deep trenches and a second number of first deep trenches, wherein the second number is a positive integer and less than the first number. In one embodiment, the substrate further includes a first number of third deep trenches oriented along a first direction, wherein the first number of third deep trenches have gaps from the first deep trenches in the first direction, and wherein, in a top view, the isolation wall further surrounds the first number of third deep trenches. In one embodiment, the first conductive plug and the second conductive plug have different depths. In one embodiment, in a top view, the first conductive plug does not overlap with the first deep trench.

[0116] In one embodiment, a semiconductor structure includes a substrate comprising a plurality of first deep trenches oriented along a first direction and a plurality of second deep trenches oriented along a second direction, wherein the second direction is perpendicular to the first direction; a first capacitor bank comprising a first core region and a first peripheral region surrounding the first core region, wherein the first capacitor bank includes a plurality of first capacitor cells located in the first deep trenches of the first core region; a second capacitor bank comprising a second core region and a second peripheral region surrounding the second core region, and the second capacitor bank includes a plurality of second capacitor cells located in the second deep trenches of the second core region; a first conductive plug landing on the first capacitor bank in the first peripheral region; a second conductive plug landing on the second capacitor bank in the second peripheral region; and an isolation wall laterally surrounding the first capacitor bank and the second capacitor bank. In one embodiment, the first capacitor bank includes a first stack of a plurality of first conductive layers and a plurality of first node dielectric layers alternately disposed in the first deep trenches; and the second capacitor bank includes a second stack of a plurality of second conductive layers and a plurality of second node dielectric layers alternately disposed in the second deep trenches. In one embodiment, the bottom of the first conductive plug is in physical contact with one of the first conductive layers, and the bottom of the second conductive plug is in physical contact with one of the second conductive layers.

[0117] The foregoing has outlined the features of several embodiments to enable those skilled in the art to better understand the various implementations of this disclosure. Those skilled in the art should understand that this disclosure can easily serve as the basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and various modifications, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a plurality of deep trenches oriented along a first direction and a second direction, and a plurality of mesa surfaces between the plurality of deep trenches; Multiple capacitor banks, each capacitor bank comprising: A stack of multiple conductive layers and multiple node dielectric layers, alternately disposed in the multiple deep trenches; and A first conductive plug is disposed on a first layer of the plurality of conductive layers; and an isolation wall penetrates the stack of the plurality of conductive layers and the plurality of node dielectric layers and enters at least one of the plurality of mesa, wherein, in a top view, the isolation wall is a closed loop.

2. The semiconductor structure as described in claim 1, characterized in that, Further includes: A second conductive plug is disposed on a second layer of the plurality of conductive layers, wherein the second layer of the plurality of conductive layers is located below the first layer of the plurality of conductive layers.

3. The semiconductor structure as described in claim 1, characterized in that, In the top view, the isolation wall extends between two adjacent capacitor banks.

4. The semiconductor structure as described in claim 1, characterized in that, A first spacing between two adjacent capacitor banks is less than or equal to a second spacing between two adjacent deep trenches.

5. A semiconductor structure, characterized in that, include: A substrate includes a plurality of first deep trenches oriented along a first direction and a plurality of second deep trenches oriented along a second direction, wherein the second direction is perpendicular to the first direction; A first capacitor bank includes a first core region and a first peripheral region surrounding the first core region, wherein the first capacitor bank includes a plurality of first capacitor cells located in the plurality of first deep trenches in the first core region. A second capacitor bank includes a second core region and a second peripheral region surrounding the second core region, and the second capacitor bank includes a plurality of second capacitor cells located in the plurality of second deep trenches in the second core region. A first conductive plug lands on the first capacitor bank in the first peripheral region; A second conductive plug lands on the second capacitor bank in the second peripheral region; as well as An isolation wall is horizontally surrounding the first capacitor bank and the second capacitor bank.

6. The semiconductor structure as described in claim 5, characterized in that, The first capacitor bank includes a first stack comprising a plurality of first conductive layers and a plurality of first node dielectric layers alternately disposed in the plurality of first deep trenches; and The second capacitor bank includes a second stack comprising a plurality of second conductive layers and a plurality of second node dielectric layers alternately disposed in the plurality of second deep trenches.

7. The semiconductor structure as described in claim 6, characterized in that, One bottom of the first conductive plug is in physical contact with one of the plurality of first conductive layers, and one bottom of the second conductive plug is in physical contact with one of the plurality of second conductive layers.

8. A semiconductor structure, characterized in that, include: A substrate includes a first number of first deep trenches oriented along a first direction and a first number of second deep trenches oriented along a second direction, wherein the first number is a positive integer; A first capacitor bank is formed on the plurality of first deep trenches, the first capacitor bank comprising: A first stack of multiple first conductive layers and multiple first node dielectric layers is alternately disposed in the first number of the multiple first deep trenches; and A first conductive plug is disposed on one of the plurality of first conductive layers; A second capacitor bank is formed on the plurality of second deep trenches, the second capacitor bank comprising: A second stack of multiple second conductive layers and multiple second node dielectric layers is alternately disposed in the first number of the multiple second deep trenches; and A second conductive plug is disposed on one of the plurality of second conductive layers; and an isolation wall, in a top view, the isolation wall being a closed loop surrounding a first portion of the first capacitor bank and the second capacitor bank, wherein the first stack of the plurality of first conductive layers and the plurality of first node dielectric layers is separated from the second stack of the plurality of second conductive layers and the plurality of second node dielectric layers through an isolation wall outside the closed loop.

9. The semiconductor structure as described in claim 8, characterized in that, In the top view, the isolation wall surrounds the first number of the plurality of second deep trenches and a second number of the plurality of first deep trenches, wherein the second number is a positive integer and less than the first number.

10. The semiconductor structure as described in claim 9, characterized in that, The substrate also includes a first number of third deep trenches oriented along the first direction, wherein the first number of third deep trenches have a gap with the first deep trenches in the first direction, and wherein, in a top view, the isolation wall further surrounds the first number of third deep trenches.

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