Glass substrate chip stacking structure
By using copper pillars and colloid filling in the glass substrate chip stack structure, the heat dissipation and connection stability issues of through-silicon via (TSV) chip stacks are solved, resulting in better heat dissipation and connection stability, and improved product quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHEJIANG DAGUI ELECTRONIC TECHNOLOGY CO LTD
- Filing Date
- 2025-09-01
- Publication Date
- 2026-06-30
Smart Images
Figure CN224439595U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a glass substrate chip stacking structure. Background Technology
[0002] Chip stacking technology is an advanced packaging technology that vertically stacks multiple chips and interconnects them using technologies such as through-silicon vias (TSVs) or microbumps (μBumps), thereby improving performance, capacity, and functional density within a limited space. Fan-out packaging is an advanced semiconductor packaging technology that enables signal transmission by adding a redistribution layer (RDL) to the chip surface, allowing the chip to connect to the outside without the need for a traditional substrate.
[0003] Most existing chip stacks use through-silicon via (TSV) technology for chip layering. After the chips are stacked on the redistribution layer of a fan-out package, the heat dissipation and connection stability during operation are poor, failing to meet the product quality requirements of fan-out packaged chips. Therefore, there is a need to provide a glass substrate chip stacking structure that can solve the problems of poor heat dissipation and connection stability of existing TSV chip stacks on fan-out package redistribution layers. Summary of the Invention
[0004] The purpose of this invention is to provide a glass substrate chip stacking structure that can solve the problems of poor heat dissipation and connection stability of silicon via chips stacked on the fan-out package redistribution layer in the prior art.
[0005] This utility model is implemented as follows:
[0006] A glass substrate chip stacking structure includes a glass substrate, stacked glass substrates, copper pillars, a chip, stacked chips, a fan-out package redistribution layer, and stacked circuitry. Copper pillars are embedded within the glass substrate and the stacked glass substrate, so that when the glass substrate is bonded to the fan-out package redistribution layer, the copper pillars within the glass substrate are electrically connected to the wiring on the fan-out package redistribution layer. The chip is embedded within the glass substrate, attached to the fan-out package redistribution layer, and electrically connected to the wiring on the fan-out package redistribution layer. The stacked glass substrates are arranged on the glass substrate, and the copper pillars within the stacked glass substrates are electrically connected to each other. Stacked circuitry is arranged on top of the chip and electrically connected to the copper pillars within the glass substrate. The stacked chip is embedded within the stacked glass substrate, allowing the stacked chip to be electrically connected to the chip via the stacked circuitry. The stacked circuitry is arranged on the stacked chip and electrically connected to the copper pillars within the stacked glass substrate, allowing adjacent stacked chips to be electrically connected via the stacked circuitry.
[0007] Both the glass substrate and the laminated glass substrate have through holes formed inside them, and the through holes penetrate the glass substrate and the laminated glass substrate. The metal copper pillars can be implanted into the through holes of the glass substrate and the laminated glass substrate.
[0008] Both the glass substrate and the stacked glass substrate have chip slots formed within them, and the chip slots penetrate both the glass substrate and the stacked glass substrate. Chips can be embedded in the chip slots of the glass substrate, and chips in the stacked glass substrate can be embedded in the chip slots of the stacked glass substrate.
[0009] The gap between the chip and the chip slot on the glass substrate is filled with colloid.
[0010] The gaps between the chip slots in the glass substrate of the stacked chip layers are filled with colloid.
[0011] Compared with the prior art, this utility model has the following advantages:
[0012] 1. Because this utility model uses a glass substrate, the stacking of glass substrates has a better heat dissipation effect compared with the traditional silicon substrate stacking. It can solve the problem of poor heat dissipation effect of silicon through-hole chip stacks on the fan-out package redistribution layer in the prior art, which is conducive to improving product quality.
[0013] 2. This utility model improves the connection stability of chip stacks on the fan-out package redistribution layer by implanting metal copper pillars in the glass through-hole as electrical connection between chips and electrical connection between the glass substrate and the redistribution layer of the fan-out package. It solves the problem of poor connection stability of silicon through-hole chip stacks on the fan-out package redistribution layer in the prior art, which is conducive to improving product quality. Attached Figure Description
[0014] Figure 1 This is a schematic diagram of the process steps 1 of the glass substrate chip stacking structure of this utility model;
[0015] Figure 2 This is a schematic diagram of step 2 of the process for the glass substrate chip stacking structure of this utility model;
[0016] Figure 3 This is a schematic diagram of step 3 in the process of the glass substrate chip stacking structure of this utility model;
[0017] Figure 4 This is a schematic diagram of step 4 in the process of the glass substrate chip stacking structure of this utility model;
[0018] Figure 5 This is a schematic diagram of step 5 in the process of the glass substrate chip stacking structure of this utility model;
[0019] Figure 6This is a schematic diagram of step 6 in the process of the glass substrate chip stacking structure of this utility model;
[0020] Figure 7 This is a schematic diagram of steps 7 and 8 of the process for the glass substrate chip stacking structure of this utility model.
[0021] In the figure, 1 is a glass substrate, 11 is a stacked glass substrate, 101 is a through hole, 102 is a chip slot, 2 is a copper pillar, 3 is a chip, 31 is a stacked chip, 4 is a fan-out package redistribution layer, 401 is wiring, 5 is colloid, and 6 is a stacked circuit. Detailed Implementation
[0022] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.
[0023] Please see the appendix Figure 1 To be continued Figure 7 A glass substrate chip stacking structure includes a glass substrate 1, stacked glass substrates 11, copper pillars 2, a chip 3, stacked chips 31, a fan-out package redistribution layer 4, and stacked circuitry 6; the glass substrate 1 and the stacked glass substrates 11 Metal copper pillars 2 are embedded within the glass substrate 1. When the glass substrate 1 is bonded to the fan-out package redistribution layer 4, the metal copper pillars 2 within the glass substrate 1 are electrically connected to the wiring 401 on the fan-out package redistribution layer 4. Chip 3 is embedded within the glass substrate 1, attached to the fan-out package redistribution layer 4, and electrically connected to the wiring 401 on the fan-out package redistribution layer 4. A stacked glass substrate 11 is arranged on the glass substrate 1, and the metal copper pillars 2 within the stacked glass substrate 11 are electrically connected to each other. A stacked circuit 6 is arranged on top of chip 3 and electrically connected to the metal copper pillars 2 within the glass substrate 1. A stacked chip 31 is embedded within the stacked glass substrate 11, so that the stacked chip 31 is electrically connected to chip 3 through the stacked circuit 6. The stacked circuit 6 is arranged on the stacked chip 31 and electrically connected to the metal copper pillars 2 within the stacked glass substrate 11, so that adjacent stacked chip 31s are electrically connected through the stacked circuit 6.
[0024] Compared to traditional silicon substrates, glass substrate 1 is thinner and has better heat dissipation, making it suitable for chip stacking on fan-out package redistribution layer 4. Meanwhile, the implantation of copper pillars 2 within glass substrate 1 and the stacked glass substrate 11, along with the arrangement of stacked circuitry 6, ensures stable electrical connections between chip 3 and stacked chips 31, and between adjacent stacked chips 31.
[0025] Please see the appendix Figure 2 To be continued Figure 4Both the glass substrate 1 and the stacked glass substrate 11 have through holes 101 formed therein, and the through holes 101 penetrate the glass substrate 1 and the stacked glass substrate 11. The metal copper pillar 2 can be implanted in the through holes 101 of the glass substrate 1 and the stacked glass substrate 11.
[0026] Preferably, a through-hole 101 is formed on the glass substrate 1 using a through-glass via (TGV) process to facilitate the implantation of the copper pillar 2. The size of the through-hole 101 is adapted to the size of the copper pillar 2.
[0027] Please see the appendix Figure 3 Both the glass substrate 1 and the stacked glass substrate 11 have chip grooves 102 formed therein, and the chip grooves 102 penetrate the glass substrate 1 and the stacked glass substrate 11; the chip 3 can be embedded in the chip groove 102 of the glass substrate 1, and the stacked chip 31 can be embedded in the chip groove 102 of the stacked glass substrate 11.
[0028] The size of the chip groove 102 inside the glass substrate 1 is determined according to the size of the chip 3. Preferably, the chip groove 102 inside the glass substrate 1 is slightly larger than the size of the chip 3 to ensure the arrangement of the chip 3.
[0029] The size of the chip groove 102 in the stacked glass substrate 11 is determined according to the size of the stacked chip 31. Preferably, the size of the chip groove 102 in the stacked glass substrate 11 is slightly larger than the size of the stacked chip 31 to ensure the arrangement of the stacked chip 31.
[0030] Please see the appendix Figure 6 and attached Figure 7 The gap between the chip 3 and the chip groove 102 of the glass substrate 1 is filled with colloid 5 to improve the stacking stability of the chip 3.
[0031] Please see the appendix Figure 6 and attached Figure 7 The gaps between the chip slots 102 of the stacked glass substrate 11 of the stacked chips 31 are filled with colloid 5 to improve the stacking stability of the stacked chips 31.
[0032] The fabrication process of the glass substrate chip stacking structure of this utility model includes the following steps:
[0033] Please see the appendix Figure 1 Step 1: Provide a glass substrate 1.
[0034] Please see the appendix Figure 2 Step 2: Form a through-hole 101 on the glass substrate 1 using a glass through-hole (TGV) process, and implant a copper pillar 2 in the through-hole 101 for electrical connection.
[0035] By implanting the copper pillar 2, a more stable connection and conduction effect can be achieved compared with the traditional through-silicon via (TSV) process.
[0036] Please see the appendix Figure 3 Step 3: According to the size of chip 3, a groove is cut in the glass substrate 1 to form chip groove 102.
[0037] Please see the appendix Figure 4 Step 4: Bond the glass substrate 1 to the fan-out package redistribution layer 4, so that the metal copper pillar 2 is electrically connected to the wiring 401 on the fan-out package redistribution layer 4.
[0038] Please see the appendix Figure 5 Step 5: Place the chip 3 in the chip slot 102 of the glass substrate 1 and attach it to the fan-out package redistribution layer 4, so that the chip 3 is electrically connected to the wiring 401 on the fan-out package redistribution layer 4.
[0039] Please see the appendix Figure 6 Step 6: Lay up a multilayer circuit 6 on top of the chip 3 and the glass substrate 1, so that the multilayer circuit 6 is electrically connected to the metal copper pillar 2 in the chip 3 and the glass substrate 1.
[0040] In step 6, colloid 5 is filled in the gap between chip 3 and chip groove 102 of glass substrate 1 to improve the stacking stability of chip 3.
[0041] Please see the appendix Figure 7 Step 7: Repeat steps 1 to 3 to provide a stacked glass substrate 11 and a stacked chip 31, and arrange the stacked glass substrate 11 and the stacked chip 31 on the glass substrate 1 and the chip 3 respectively.
[0042] In step 7, the copper pillars 2 in the stacked glass substrate 11 are connected to the copper pillars 2 in the glass substrate 1, and the stacked chip 31 is electrically connected to the chip 3 through the stacked circuit 6, so as to realize the stacked stack and ensure stable connection.
[0043] The stacked chip 31 may be the same as or different from the chip 3, and the stacked glass substrate 11 may be the same as or different from the glass substrate 1. The appropriate stacked glass substrate 11 and stacked chip 31 can be selected according to the actual product requirements.
[0044] Please see the appendix Figure 7 Step 8: A stacked circuit 6 is arranged on top of the stacked chip 31 and the stacked glass substrate 11, so that the stacked circuit 6 is electrically connected to the metal copper pillar 2 in the stacked chip 31 and the stacked glass substrate 11.
[0045] In step 8, colloid 5 is filled in the gap between the stacked chip 31 and the chip groove 102 of the stacked glass substrate 11 to improve the stacking stability of the stacked chip 31.
[0046] Step 9: Repeat steps 7 and 8 to complete the stacking of the multilayer chip 3 on the fan-out package redistribution layer 4.
[0047] During the stacking process of the multilayer chip 3, the chip 31 of the last stacked layer and the stacked glass substrate 11 are used as the chip 3 and glass substrate 1 of the next stacked layer, and the above steps are repeated to stack the multilayer chip 3.
[0048] Appendix Figure 7 The diagram only shows a two-layer chip stack-up structure. The number of chips 31 in the stack-up structure can be increased according to actual stack-up requirements. The stack-up process will not be described in detail here.
[0049] The above are merely preferred embodiments of the present utility model and are not intended to limit the scope of protection of the utility model. Therefore, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the scope of protection of the present utility model.
Claims
1. A glass substrate chip stacking structure, characterized in that: The system includes a glass substrate (1), a stacked glass substrate (11), copper pillars (2), a chip (3), a stacked chip (31), a fan-out package redistribution layer (4), and stacked circuitry (6). Copper pillars (2) are embedded in the glass substrate (1) and the stacked glass substrate (11), so that when the glass substrate (1) is bonded to the fan-out package redistribution layer (4), the copper pillars (2) in the glass substrate (1) are electrically connected to the wiring (401) on the fan-out package redistribution layer (4). The chip (3) is embedded in the glass substrate (1), and the chip (3) is attached to the fan-out package redistribution layer (4) and electrically connected to the wiring (401) on the fan-out package redistribution layer (4). The stacked glass substrate (11) is arranged on the glass substrate (1), and the copper pillars (2) in the stacked glass substrate (11) are electrically connected to the fan-out package redistribution layer (4). The copper pillars (2) inside the glass substrate (1) are electrically connected; the stacked circuit (6) is arranged on the top of the chip (3) and electrically connected to the copper pillars (2) inside the glass substrate (1); the stacked chip (31) is embedded in the stacked glass substrate (11), so that the stacked chip (31) is electrically connected to the chip (3) through the stacked circuit (6); the stacked circuit (6) is arranged on the stacked chip (31) and electrically connected to the copper pillars (2) inside the stacked glass substrate (11), so that the chips (31) of adjacent stacked layers are electrically connected through the stacked circuit (6).
2. The glass substrate chip stacking structure according to claim 1, characterized in that: Both the glass substrate (1) and the stacked glass substrate (11) have through holes (101) formed in them. The through holes (101) penetrate the glass substrate (1) and the stacked glass substrate (11). The metal copper pillar (2) can be implanted in the through holes (101) of the glass substrate (1) and the stacked glass substrate (11).
3. The glass substrate chip stacking structure according to claim 1 or 2, characterized in that: Chip slots (102) are formed in both the glass substrate (1) and the stacked glass substrate (11), and the chip slots (102) penetrate the glass substrate (1) and the stacked glass substrate (11); the chip (3) can be embedded in the chip slot (102) of the glass substrate (1), and the chip (31) of the stacked glass substrate (11) can be embedded in the chip slot (102) of the stacked glass substrate (11).
4. The glass substrate chip stacking structure according to claim 3, characterized in that: The gap between the chip (3) and the chip groove (102) of the glass substrate (1) is filled with colloid (5).
5. The glass substrate chip stacking structure according to claim 3, characterized in that: The gaps between the chip slots (102) of the stacked chips (31) and the stacked glass substrates (11) are filled with colloid (5).