A dual PWM controller for isolated power supplies

Abstract

The utility model discloses a kind of double PWM controllers for isolating power supply, it is related to power management technical field, the input end of LDO1 and LDO2 of the utility model is simultaneously connected power supply VIN, LDO1 converts power supply VIN into driving power supply VCC and gives external power drive circuit power supply, and LDO2 converts power supply VIN into internal power supply VREF and gives internal analog circuit power supply, that is, the driving power supply and analog power supply are separated by LDO1 and LDO2 in the application, to adapt to the power supply of wide input voltage range;Meanwhile, the output end OUTA of first PWM controller is connected the gate of main switch tube Q1, the output end OUTB of second PWM controller is connected the gate of clamping switch tube Q2, when Q1 is turned on, input voltage is applied in transformer primary side, energy is stored in transformer, when Q1 is turned off, stored energy is released to load through secondary side, clamping switch tube Q2 in this time main switch tube Q1 during turn-off, absorb the energy stored in transformer, to limit the rate of primary voltage rise to carry out high efficiency control.

Description

Technical Field

[0001] This utility model relates to the field of power management technology, and in particular to a dual PWM controller for isolated power supplies. Background Technology

[0002] An isolated power supply is a power system that achieves electrical isolation between the input and output through physical isolation means (such as transformers or optocouplers). Isolated power supplies are widely used in high-voltage power supplies, industrial automation, communications, medical equipment, and other fields, especially in applications requiring high electrical isolation and safety. The basic working principle of an isolated power supply is to use a transformer or other isolation components between the input and output, and through the regulation of a switching controller, to convert the AC or DC power input into stable output power, while ensuring electrical isolation between the input and output terminals.

[0003] Common isolated power supply topologies include forward power supplies, flyback power supplies, full-bridge power supplies, and half-bridge power supplies. Each of these topologies has its own advantages and disadvantages, and choosing the appropriate topology has a significant impact on the power supply's efficiency, cost, and size. The control chip is the core component for realizing the isolated power supply function. It is responsible for adjusting the operating state of the switching transistors, controlling power transmission and feedback regulation to ensure stable output voltage and current.

[0004] Currently, common isolated power supply control chips include: optocoupler-based control chips, transformer-based control chips, and integrated control chips. However, due to the large number of loads that require isolated power supply control and the different types of loads, current control chips struggle to maintain high-efficiency control across a wide input voltage range. Utility Model Content

[0005] This utility model provides a dual PWM controller for isolated power supplies, which can solve the problem in the prior art that current control chips are difficult to maintain high-efficiency control while maintaining a wide input voltage range.

[0006] This utility model embodiment provides a dual PWM controller for isolated power supplies, including a first LDO power supply module LDO1, a second LDO power supply module LDO2, a power conversion module, a first PWM controller, a second PWM controller, an external power drive circuit, and an internal analog circuit;

[0007] The input terminal of the power conversion module is connected to the power supply VIN, and the output terminal of the power conversion module is connected to the input terminals of the first LDO power supply module LDO1 and the second LDO power supply module LDO2 respectively.

[0008] The output terminal of the first LDO power supply module LDO1 is connected to the drive power supply VCC, and the drive power supply VCC is connected to an external power drive circuit; the external power drive circuit is used to drive an external load and realize power transmission.

[0009] The output of the second LDO power supply module LDO2 is connected to the internal power supply VREF, which is connected to the internal analog circuit. The internal analog circuit is used to process analog signals inside the chip.

[0010] The input terminals of the first PWM controller and the second PWM controller are respectively connected to the output terminal of the second LDO power supply module LDO2. The output terminal OUTA of the first PWM controller is connected to the gate of the main switch Q1, and the output terminal OUTB of the second PWM controller is connected to the gate of the clamping switch Q2.

[0011] The main switch Q1 is turned on to store energy in the transformer; the clamping switch Q2 is turned on when the main switch Q1 is turned off, and the clamping switch Q2 is used to absorb excess energy stored in the transformer.

[0012] Preferably, the power conversion module includes: a VDD power supply and a reference voltage VBG;

[0013] The input terminal of the VDD power supply is connected to the power supply VIN, the output terminal of the VDD power supply is connected to the input terminal of the reference voltage VBG, and the output terminal of the reference voltage VBG is connected to the input terminals of the first LDO power supply module LDO1 and the second LDO power supply module LDO2 respectively.

[0014] The VDD power supply is the power supply VIN after rectification and filtering.

[0015] The reference voltage VBG is a voltage formed by processing the VDD power supply through a bandgap reference circuit, which is independent of external temperature and external power supply voltage.

[0016] Preferably, it further includes: a phase-locked loop and a current-mode control loop;

[0017] The phase-locked loop adjusts the output frequency of the voltage-controlled oscillator by comparing the phase difference between the input signal and the feedback signal, thereby achieving clock signal synchronization.

[0018] The current-mode control loop is connected to the feedback pins FB, COMP, and CS. The current-mode control loop detects the output current by using a current sampling resistor, compares the sampled voltage with the reference voltage, and adjusts the duty cycle of the PWM signal according to the comparison result to achieve stable output voltage and current.

[0019] Preferably, it also includes: an undervoltage protection module, an overcurrent protection module, and an overtemperature protection module;

[0020] The undervoltage protection module connects the power supply VIN to the UVLO pin through a resistor divider. The voltage of the UVLO pin is compared with the reference voltage VBG to generate a VIN_OK signal to indicate the voltage status of the power supply VIN. The undervoltage point is adjusted by adjusting the voltage division ratio of the resistor to achieve undervoltage protection.

[0021] The overcurrent protection module is used to control the hiccup time according to the size of the capacitor connected to the RES pin when the voltage of the COMP pin is higher than the reference voltage VBG, so as to achieve overcurrent protection.

[0022] The over-temperature protection module monitors the controller temperature in real time through a built-in temperature sensor. When the temperature exceeds the set threshold, it limits the controller's output power or shuts down the functional module through logic control.

[0023] Preferably, it also includes a soft-start module;

[0024] The soft-start module controls the startup time through an external capacitor connected to the SS pin;

[0025] During startup, the output of the error amplifier EA is clamped by the voltage of the SS pin, the reference current Iref charges the external capacitor, causing the voltage of the COMP pin to rise linearly, and gradually increasing the PWM duty cycle to control the startup time.

[0026] Preferably, the first LDO power supply module LDO1 also provides reverse power supply, wherein the reverse power supply is:

[0027] The transformer auxiliary winding T1C is connected to the VCC pin through the rectifier diode D3. The transformer auxiliary winding T1C is unidirectionally transmitted to the primary side and connected to the VCC pin through the transformer auxiliary winding T1B for reverse power supply.

[0028] When the output voltage Vo increases, the reverse supply voltage increases. When the reverse supply voltage exceeds the output voltage of the first LDO power supply module LDO1, the power supply from VIN to VCC is switched to Vo supplying power to VCC.

[0029] Preferably, the dual PWM controller is based on an active clamp flyback topology to build an isolated power supply, which includes: resistors R1, R2, R3, R4, R5, R6, R7, R8, and R9; capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, and C11; and resistor R... sense1. Resistor RT, NMOS transistor Q1, PMOS transistor Q2, switching diode D1, Schottky diode D2, Schottky diode D3, Zener diode D4, optocoupler U1, voltage regulator U2 and transformer T1;

[0030] The input voltage is connected to the VIN pin of the controller. C1 is connected in parallel between VIN and GND1. VIN is connected to the UVLO pin through a voltage divider between R1 and R2. R3 is connected to the RT pin. C2 is connected to the RES pin. C3 is connected to the SS pin. The FB pin is connected to GND1. C4 is connected to VREF. C5 is connected to the VCC, PVCCA, and PVCCB pins. OUTA is connected to the gate of Q1. OUTB is connected to one end of C9. The other end of C9 is connected to the gate of Q2 and the positive terminal of D1. The negative terminal of D1 is connected to GND1. AGND, PGNDA, and PGNDB are connected to GND1.

[0031] The positive terminal of T1A is connected to VIN, and the negative terminal is connected to the drain of Q1, C8, and R5. The other end of C8 is connected to the source of Q2, the other end of R5 is connected to C7, and the other end of C7 is connected to GND1. The source of Q1 is connected to R4 and R... sense Connection, R sense The other end is connected to GND1, the other end of R4 is connected to the CS pin and C6, and the other end of C6 is connected to GND1;

[0032] The positive terminal of T1B is connected to GND2, the negative terminal is connected to the positive terminal of D2, the negative terminal of D2 is connected to C10 and Vo, the other end of C10 is connected to GND2, Vo is connected to R6, R7 and R8, the other end of R6 is connected to terminal A of U1, the other end of R7 is connected to C11, the other end of R8 is connected to terminal A of U2 and R9, the other end of C11 is connected to terminal B of U1 and terminal C of U2, the other end of R9 is connected to terminal B of U2 and GND2, terminal C of U1 is connected to GND1, and terminal D of U1 is connected to the COMP pin.

[0033] Preferably, the flyback power transfer process of the NMOS transistor Q1 is as follows:

[0034] The voltage of VIN is divided by R1 and R2 and then sent to the UVLO pin. When the voltage of the UVLO pin is greater than the set undervoltage threshold, the chip starts to operate.

[0035] The voltage VIN generates the drive power supply voltage VCC through the internal LDO1. The VCC voltage generates the internal power supply VREF through LDO2. The SS pin starts charging, the loop starts, and Q1 is turned off. CS is controlled by resistors R4 and R... senseWhen pulled to ground, the COMP voltage is clamped by the SS voltage during startup, achieving soft start. As the COMP voltage rises to the comparator's toggling threshold, the internal PWM comparator outputs 0, and OUTA generates a high-turn-on drive, causing Q1 to turn on. The voltage then flows from VIN through T1A, Q1, and R... sense The generated current path stores energy in the primary winding T1A of transformer T1, R sense The sampling voltage on the CS pin increases with the increase of current. The voltage on the CS pin gradually rises until it exceeds the COMP voltage, causing the PWM comparator to flip to 1. OUTA generates a low shutdown drive, turning off Q1. CS is controlled by R4 and R sense When pulled to ground, the COMP voltage is greater than CS, and the PWM comparator returns to 0.

[0036] When Q1 is off, transformer T1 transfers the energy from T1A to T1B, which is then transferred to capacitor C10 via the unidirectional conduction of D2, causing the output voltage Vo to rise. The Vo voltage is then divided by R8 and R9 and input to U2. When the input voltage of U2 is lower than the reference voltage, the output current of U2 decreases, and COMP on the primary side is pulled up by the internal pull-up resistor of the chip. When the input voltage of U2 is higher than the reference voltage, the output current of U2 increases, and the current transmitted to the primary side through optocoupler U1 increases, pulling COMP down and thus adjusting the duty cycle of the primary side OUTA to stabilize the output voltage Vo.

[0037] This utility model provides a dual PWM controller for isolated power supplies, which has the following advantages compared with the prior art:

[0038] This invention separates the drive power supply from the analog power supply by using a first LDO power supply module LDO1 and a second LDO power supply module LDO2. The input terminals of both LDO1 and LDO2 are connected to the power supply VIN. LDO1 converts VIN into a drive power supply VCC to power the external power drive circuit, while LDO2 converts VIN into an internal power supply VREF to power the internal analog circuit. This allows the invention to adapt to power supplies with a wide input voltage range by using LDO1 and LDO2. Simultaneously, the invention connects the output terminal OUTA of the first PWM controller to the main switching transistor Q1. The gate of the first PWM controller is connected to the gate of the clamping switch Q2. When the main switch Q1 is turned on, the first PWM controller controls the input voltage to be applied to the primary side of the transformer, and the energy is stored in the transformer. When the main switch Q1 is turned off, the stored energy is released to the load through the secondary side. At this time, the second PWM controller controls the clamping switch Q2 to absorb and consume the excess energy stored in the transformer during the period when the main switch Q1 is turned off, so as to limit the rate of rise of the primary voltage for high-efficiency control. That is, the present invention maintains high-efficiency control while having a wide input voltage range.

[0039] Furthermore, this invention integrates dual PWM drive, dual LDO power supply, phase-locked loop, current mode control, slope compensation, undervoltage protection, overcurrent protection, and overtemperature protection, which can significantly reduce the number of external components and improve the reliability of the system. Attached Figure Description

[0040] Figure 1 A functional block diagram of a dual PWM controller for an isolated power supply provided for an embodiment of this utility model;

[0041] Figure 2 A schematic diagram of an active clamp flyback topology for a dual PWM controller for an isolated power supply provided in an embodiment of this utility model;

[0042] Figure 3 A schematic diagram of the working waveform of the flyback section of a dual PWM controller for an isolated power supply provided in an embodiment of this utility model;

[0043] Figure 4 A schematic diagram showing the waveform relationship between OUTA and OUTB of a dual PWM controller for an isolated power supply, provided for an embodiment of this utility model;

[0044] Figure 5 This is a schematic diagram of the hiccuping process waveform of a dual PWM controller for an isolated power supply provided in an embodiment of the present invention. Detailed Implementation

[0045] To make the above-mentioned objects, features, and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a full understanding of this utility model. However, this utility model can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this utility model. Therefore, this utility model is not limited to the specific embodiments disclosed below.

[0046] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0047] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0048] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0049] In this utility model, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0050] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0051] See Figure 1 This utility model provides a dual PWM controller for isolated power supplies. Its control chip integrates multiple functions such as dual PWM drive, phase-locked loop, current mode control, slope compensation, undervoltage protection, overcurrent protection, overtemperature protection, and electromagnetic interference suppression. It significantly reduces the number of external components and improves the reliability of the system. At the same time, it integrates dual LDOs, supports reverse power supply, and can meet a wide input voltage range while significantly improving drive efficiency.

[0052] exist Figure 1 In the diagram, the functions of each control pin are represented as follows:

[0053] SS: Soft start, the soft start time is determined by the external capacitor.

[0054] FB: System output voltage feedback terminal, internally connected to the inverting input terminal of the error amplifier.

[0055] COMP: Output of the internal error amplifier, input of the internal PWM comparator.

[0056] CS: Peak current detection input terminal, internally connected to the input terminal of the PWM comparator.

[0057] RT: Oscillator control pin. The operating frequency is designed by configuring the resistor RT between this pin and ground.

[0058] RES: Short circuit / overcurrent protection hiccup restart time configuration pin. The hiccup restart time is designed by configuring the capacitor between this pin and GND.

[0059] SYNC: Frequency synchronization pin. This pin can be connected to an external signal for synchronization.

[0060] SYNC_O: Frequency output terminal.

[0061] AGND: Simulated ground.

[0062] PGNDA: Power ground of OUTA.

[0063] PGNDB: Power ground of OUTB.

[0064] OUTB: Gate drive output pin.

[0065] OUTA: Gate drive output pin.

[0066] PVCCB: OUTB power supply.

[0067] PVCCA: OUTA power supply.

[0068] VIN: Power supply.

[0069] VCC: LDO1 output, driving power supply.

[0070] VREF: LDO2 output, internal power supply.

[0071] UVLO: Bus undervoltage protection input terminal.

[0072] The overall control system adopts a current-mode loop control method, mainly including the power supply section, phase-locked loop, protection section, and main loop section; the working principles of each part are as follows:

[0073] 1. Power supply section.

[0074] After VIN is powered on, a coarse VDD power supply is generated through the pre-power supply module to power low-voltage circuits such as the bandgap reference and LDO1. The bandgap reference module generates the reference voltage VBG and the reference current Iref. LDO1 uses VBG as a reference and through negative feedback to convert VIN into a stable VCC voltage to power the power drive. The VCC reverse protection circuit can cut off the output of LDO1 when there is a reverse input voltage on the VCC pin. LDO2 uses VBG as a reference and through negative feedback to convert VCC into a precise VREF voltage to power the internal low-voltage analog circuit. The two-stage LDO structure separates the drive power supply from the analog power supply, which allows VCC reverse power supply to improve efficiency and is suitable for operation over a wide VIN range.

[0075] 2. Phase-locked loop (PLL).

[0076] A phase-locked loop (PLL) is used to generate the system's operating clock; it can generate a stable and adjustable clock, or synchronize with an external clock; different resistors connected to the RT pin can adjust the internal clock CLK frequency; when there is an external clock input on the SYNC pin, the PLL will synchronize CLK with the external clock; SYNC_O outputs a clock with the same frequency as CLK, and VRAMP is a triangular wave voltage with the same frequency as the clock, used for slope compensation.

[0077] 3. Protected section.

[0078] The protection section collects system information to monitor the working status in real time and uses a logic control module to control the system to deal with abnormal operating conditions. The protection section includes undervoltage protection, overcurrent protection, and overtemperature protection modules. For undervoltage protection, VIN is connected to the UVLO pin through a resistor divider. The voltage at the UVLO pin is compared with the reference voltage VBG to generate a VIN_OK signal to indicate that the VIN voltage is good. The undervoltage point can be flexibly adjusted by adjusting the voltage division ratio of the resistor. For overcurrent protection, when the system experiences overcurrent / short circuit, the output voltage will decrease and the COMP voltage will increase. When COMP is greater than the set value VBG, the overcurrent / short circuit hiccup time control module controls the hiccup time according to the size of the capacitor connected to the RES pin.

[0079] 4. Main ring road.

[0080] When the internal EN signal goes high, the COMP voltage is pulled high by EA, and at the same time, the Iref current charges the SS pin, and the SS voltage gradually increases. The COMP voltage is clamped by the OPA module to realize the soft start function. The COMP and CS are used to reset the RS flip-flop through the result of the PWM comparator, and the CLK signal is used to set the RS flip-flop. The output of the RS flip-flop is driven to generate OUTA and OUTB signals after overlapping control.

[0081] like Figure 2 The diagram shows an application scheme using the control chip designed in this invention, which is based on an active clamp flyback topology. It includes resistors R1~R1, Rsense, and RT; capacitors C1~C10; NMOS and PMOS transistors Q1 and Q2; a switching diode D1; Schottky diodes D2 and D3; a Zener diode D4; an optocoupler U1; a three-terminal adjustable parallel voltage regulator U2; and a transformer T1.

[0082] The connection is as follows: the input voltage is connected to the VIN pin of the controller; C1 is connected in parallel between VIN and GND1 for voltage regulation; VIN is divided by R1 and R2 and connected to the UVLO pin; R3 is connected to the RT pin; C2 is connected to the RES pin; C3 is connected to the SS pin; the FB pin is connected to GND1; C4 is connected to VREF; C5 is connected to the VCC, PVCCA, and PVCCB pins; OUTA is connected to the gate of Q1; OUTB is connected to one end of capacitor C9; the other end of C9 is connected to the gate of Q2 and the positive terminal of D1; the negative terminal of D1 is connected to GND1. 1. Connect AGND, PGNDA, and PGNDB to GND1. SYNC and SYNC_O can be connected to the frequency input and output respectively. The positive terminal of T1A is connected to VIN, and the negative terminal is connected to the drain of Q1, C8, and R5. The other end of C8 is connected to the source of Q2. The other end of R5 is connected to C7. The other end of C7 is connected to GND1. The source of Q1 is connected to R4 and Rsense. The other end of Rsense is connected to GND1. The other end of R4 is connected to the CS pin and C6. The other end of C6 is connected to GND1. The positive terminal of T1B is connected to GND2, and the negative terminal is connected to the positive terminal of D2. The negative terminal of D2 is connected to C10 and VO. The other end of C10 is connected to GND2. VO is connected to R6, R7, and R8. The other end of R6 is connected to terminal A of U1. The other end of R7 is connected to C11. The other end of R8 is connected to terminal A of U2 and R9. The other end of C11 is connected to terminal B of U1 and terminal C of U2. The other end of R9 is connected to terminal B of U2 and GND2. Terminal C of U1 is connected to GND1, and terminal D is connected to the COMP pin.

[0083] Its working principle includes:

[0084] 1. Power transmission process of main switch Q1 flyback.

[0085] When VIN is powered on, the voltage after being divided by R1 and R2 is applied to the UVLO pin of the chip. When this voltage exceeds the set undervoltage threshold, the chip is enabled. The VIN voltage generates the drive power supply voltage VCC through the internal LDO1. The VCC voltage generates the internal power supply VREF through LDO2. The SS pin starts charging, and the loop begins to attempt to start. Initially, Q1 is turned off, and CS is pulled to ground by resistors R4 and Rsense. During the startup process, the COMP voltage is clamped by the SS voltage to achieve soft start. As the COMP voltage rises to the comparator's toggle threshold, the internal PWM comparator outputs 0. When the clock edge of the internal oscillator arrives, OUTA generates a high-turn-on drive to turn on Q1, which is then driven by V... The current path generated by IN through T1A, Q1, and Rsense stores energy in the primary side T1A of transformer T1. The sampling voltage on Rsense increases with the increase of this current. The voltage on the CS pin gradually rises until it exceeds the COMP voltage, causing the PWM comparator to flip to 1. At this time, OUTA generates a low shutdown drive to turn off Q1. CS is pulled to ground by R4 and Rsense. The COMP voltage is greater than CS, and the PWM comparator returns to 0. The above process is repeated when the next clock edge arrives. At the same time, when Q1 is turned off, the energy of T1A is transferred to T1B through transformer T1. After the unidirectional conduction of D2, it is transferred to capacitor C10, causing the output voltage Vo to rise continuously. The Vo voltage is divided by resistors R8 and R9 and then input to U2. U2 is a general-purpose three-terminal regulator with a fixed reference. The output current is controlled by the difference between the input voltage and the reference voltage. This difference is then fed back to the primary side via optocoupler U1, forming negative feedback control. When the input voltage of U2 is lower than the reference voltage, the output current of U2 decreases, and the COMP resistor on the primary side is pulled high by the internal pull-up resistor. When the input voltage of U2 is higher than the reference voltage, the output current of U2 increases, and the current transmitted to the primary side through optocoupler U1 increases, pulling COMP low. This adjusts the duty cycle of the primary side OUTA, achieving a stable output voltage Vo. The specific operating waveform is shown below. Figure 3 As shown.

[0086] 2. Active clamping operation of auxiliary switch Q2.

[0087] The operation of the clamping switch Q2 during the on and off phases of the active clamp flyback converter includes:

[0088] Q2 conduction phase:

[0089] When Q1 is turned off, the magnetic field on the primary side of the transformer begins to collapse; due to the leakage inductance of the transformer, a high voltage spike is generated in the reverse direction; without a clamping circuit, this voltage spike may damage Q1 or other components; when the clamping switch Q2 is turned on, a new current path is provided for the primary winding T1A of transformer T1; this current path absorbs and consumes the excess energy stored in the transformer and limits the rate at which the primary voltage rises.

[0090] Q2 Shutdown Phase:

[0091] After Q2 is turned on for a period of time, the magnetic field energy in the transformer is completely released, and the current on the primary side decreases to zero. When the magnetic field is completely consumed, Q2 is turned off. At this time, the function of Q2 is completed, and the current path on the primary side of the transformer is cut off. After the clamping switch is turned off, the system enters the next working cycle, the main switch is turned on again, and a new energy transmission begins.

[0092] The combination of the Q2 turn-on and Q2 turn-off phases ensures that the active clamp flyback converter can effectively suppress excessively high voltage spikes during energy transfer, improving system reliability and efficiency. The switching waveform relationship between OUTA and OUTB is as follows: Figure 4 As shown.

[0093] 3. Reverse power supply function.

[0094] Because the chip's VCC pin is bidirectional, it is powered by the internal LDO1 when VOUT is not enabled. At this time, the output current of VCC is entirely provided by VIN, and the efficiency decreases significantly as the voltage difference between VIN and VCC increases. The transformer T1C transmits power unidirectionally to the primary side through T1B and connects to the VCC pin for reverse power supply. As the output voltage VO increases, the reverse power supply voltage also increases. When this voltage exceeds the output voltage of the internal LDO1, the power supply from VIN to VCC will switch to VO to power VCC. Compared with the method of generating VCC from VIN through LDO, the scheme of generating VO from VIN and then generating VCC from VO is more efficient, especially when the VIN voltage is high. Reverse power supply can significantly improve the driving efficiency of VCC, thereby improving the overall efficiency of the system.

[0095] 4. Overcurrent / short circuit protection function.

[0096] When an overcurrent / short circuit occurs in the system, the Vo voltage decreases. After being divided by R8 and R9, the voltage input to U2 decreases, and this decrease is fed back to the primary side through optocoupler U1, causing the COMP voltage to rise. When COMP is greater than VBG, the chip charges the external capacitor RES. If the COMP voltage remains higher than VBG, the system is determined to be in overcurrent / short circuit protection mode and enters a hiccup restart state. If the COMP voltage is less than VBG after restarting, the chip discharges to the RES terminal, and the system operates normally. The hiccup process is as follows: Figure 5 As shown.

[0097] This invention suppresses high-frequency noise through active clamping, improves efficiency through reverse power supply via VCC, significantly reduces the number of external components by integrating multiple functions, and meets a wide input voltage range through dual LDOs.

[0098] The embodiments described above are merely illustrative of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. A dual PWM controller for isolated power supplies, characterized by, include: The system includes a first LDO power supply module LDO1, a second LDO power supply module LDO2, a power conversion module, a first PWM controller, a second PWM controller, an external power drive circuit, and an internal analog circuit. The input terminal of the power conversion module is connected to the power supply VIN, and the output terminal of the power conversion module is connected to the input terminals of the first LDO power supply module LDO1 and the second LDO power supply module LDO2 respectively. The output terminal of the first LDO power supply module LDO1 is connected to the drive power supply VCC, and the drive power supply VCC is connected to an external power drive circuit; the external power drive circuit is used to drive an external load and realize power transmission. The output of the second LDO power supply module LDO2 is connected to the internal power supply VREF, which is connected to the internal analog circuit. The internal analog circuit is used to process analog signals inside the chip. The input terminals of the first PWM controller and the second PWM controller are respectively connected to the output terminal of the second LDO power supply module LDO2. The output terminal OUTA of the first PWM controller is connected to the gate of the main switch Q1, and the output terminal OUTB of the second PWM controller is connected to the gate of the clamping switch Q2. By turning on the main switch Q1, energy is stored in the transformer; the clamping switch Q2 is turned on when the main switch Q1 is turned off, and the clamping switch Q2 is used to absorb excess energy stored in the transformer.

2. A dual PWM controller for isolated power supplies according to claim 1, characterized in that, The power conversion module includes: a VDD power supply and a reference voltage VBG; The input terminal of the VDD power supply is connected to the power supply VIN, the output terminal of the VDD power supply is connected to the input terminal of the reference voltage VBG, and the output terminal of the reference voltage VBG is connected to the input terminals of the first LDO power supply module LDO1 and the second LDO power supply module LDO2 respectively. The VDD power supply is the power supply VIN after rectification and filtering. The reference voltage VBG is a voltage formed by processing the VDD power supply through a bandgap reference circuit, which is independent of external temperature and external power supply voltage.

3. A dual PWM controller for isolated power supplies as defined in claim 1, wherein, Also includes: Phase-locked loop and current-mode control loop; The phase-locked loop adjusts the output frequency of the voltage-controlled oscillator by comparing the phase difference between the input signal and the feedback signal, thereby achieving clock signal synchronization. The current-mode control loop is connected to the feedback pins FB, COMP, and CS. The current-mode control loop detects the output current by using a current sampling resistor, compares the sampled voltage with the reference voltage, and adjusts the duty cycle of the PWM signal according to the comparison result to achieve stable output voltage and current.

4. A dual PWM controller for isolated power supplies as defined in claim 1, wherein, Also includes: Undervoltage protection module, overcurrent protection module, and overtemperature protection module; The undervoltage protection module connects the power supply VIN to the UVLO pin through a resistor divider. The voltage of the UVLO pin is compared with the reference voltage VBG to generate a VIN_OK signal to indicate the voltage status of the power supply VIN. The undervoltage point is adjusted by adjusting the voltage division ratio of the resistor to achieve undervoltage protection. The overcurrent protection module is used to control the hiccup time according to the size of the capacitor connected to the RES pin when the voltage of the COMP pin is higher than the reference voltage VBG, so as to achieve overcurrent protection. The over-temperature protection module monitors the controller temperature in real time through a built-in temperature sensor. When the temperature exceeds the set threshold, it limits the controller's output power or shuts down the functional module through logic control.

5. A dual PWM controller for isolated power supplies as defined in claim 1, wherein, It also includes a soft-start module; The soft-start module controls the startup time through an external capacitor connected to the SS pin; During startup, the output of the error amplifier EA is clamped by the voltage of the SS pin, the reference current Iref charges the external capacitor, causing the voltage of the COMP pin to rise linearly, and gradually increasing the PWM duty cycle to control the startup time.

6. A dual PWM controller for isolated power supplies as defined in claim 1, wherein, The first LDO power supply module LDO1 also provides reverse power supply, which is as follows: The transformer auxiliary winding T1C is connected to the VCC pin through the rectifier diode D3. The transformer auxiliary winding T1C is unidirectionally transmitted to the primary side and connected to the VCC pin through the transformer auxiliary winding T1B for reverse power supply. When the output voltage Vo increases, the reverse supply voltage increases. When the reverse supply voltage exceeds the output voltage of the first LDO power supply module LDO1, the power supply from VIN to VCC is switched to Vo supplying power to VCC.

7. A dual PWM controller for isolated power supplies according to claim 1, characterized in that, The dual PWM controller is based on an active clamp flyback topology to build an isolated power supply. The isolated power supply includes: resistors R1, R2, R3, R4, R5, R6, R7, R8, and R9; capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, and C11; and resistor R... sense 1. Resistor RT, NMOS transistor Q1, PMOS transistor Q2, switching diode D1, Schottky diode D2, Schottky diode D3, Zener diode D4, optocoupler U1, voltage regulator U2 and transformer T1; The input voltage is connected to the VIN pin of the controller. C1 is connected in parallel between VIN and GND1. VIN is connected to the UVLO pin through a voltage divider between R1 and R2. R3 is connected to the RT pin. C2 is connected to the RES pin. C3 is connected to the SS pin. The FB pin is connected to GND1. C4 is connected to VREF. C5 is connected to the VCC, PVCCA, and PVCCB pins. OUTA is connected to the gate of Q1. OUTB is connected to one end of C9. The other end of C9 is connected to the gate of Q2 and the positive terminal of D1. The negative terminal of D1 is connected to GND1. AGND, PGNDA, and PGNDB are connected to GND1. The positive terminal of T1A is connected to VIN, and the negative terminal is connected to the drain of Q1, C8, and R5. The other end of C8 is connected to the source of Q2, the other end of R5 is connected to C7, and the other end of C7 is connected to GND1. The source of Q1 is connected to R4 and R... sense Connection, R sense The other end is connected to GND1, the other end of R4 is connected to the CS pin and C6, and the other end of C6 is connected to GND1; The positive terminal of T1B is connected to GND2, the negative terminal is connected to the positive terminal of D2, the negative terminal of D2 is connected to C10 and Vo, the other end of C10 is connected to GND2, Vo is connected to R6, R7 and R8, the other end of R6 is connected to terminal A of U1, the other end of R7 is connected to C11, the other end of R8 is connected to terminal A of U2 and R9, the other end of C11 is connected to terminal B of U1 and terminal C of U2, the other end of R9 is connected to terminal B of U2 and GND2, terminal C of U1 is connected to GND1, and terminal D of U1 is connected to the COMP pin.

8. A dual PWM controller for an isolated power supply according to claim 7, characterized in that, The flyback power transfer process of the NMOS transistor Q1 is as follows: The voltage of VIN is divided by R1 and R2 and then sent to the UVLO pin. When the voltage of the UVLO pin is greater than the set undervoltage threshold, the chip starts to operate. The voltage VIN generates the drive power supply voltage VCC through the internal LDO1. The VCC voltage generates the internal power supply VREF through LDO2. The SS pin starts charging, the loop starts, and Q1 is turned off. CS is controlled by resistors R4 and R... sense When pulled to ground, the COMP voltage is clamped by the SS voltage during startup, achieving soft start. As the COMP voltage rises to the comparator's toggling threshold, the internal PWM comparator outputs 0, and OUTA generates a high-turn-on drive, causing Q1 to turn on. The voltage then flows from VIN through T1A, Q1, and R... sense The generated current path stores energy in the primary winding T1A of transformer T1, R sense The sampling voltage on the CS pin increases with the increase of current. The voltage on the CS pin gradually rises until it exceeds the COMP voltage, causing the PWM comparator to flip to 1. OUTA generates a low shutdown drive, turning off Q1. CS is controlled by R4 and R sense When pulled to ground, the COMP voltage is greater than CS, and the PWM comparator returns to 0. When Q1 is off, transformer T1 transfers the energy from T1A to T1B, which is then transferred to capacitor C10 via the unidirectional conduction of D2, causing the output voltage Vo to rise. The Vo voltage is then divided by R8 and R9 and input to U2. When the input voltage of U2 is lower than the reference voltage, the output current of U2 decreases, and COMP on the primary side is pulled up by the internal pull-up resistor of the chip. When the input voltage of U2 is higher than the reference voltage, the output current of U2 increases, and the current transmitted to the primary side through optocoupler U1 increases, pulling COMP down and thus adjusting the duty cycle of the primary side OUTA to stabilize the output voltage Vo.

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