Phase-locked loop circuit, quantum computing measurement and control system and quantum computer
By combining a mixer, loop filter, and voltage-controlled oscillator in a phase-locked loop circuit design, the problem of phase noise degradation of the frequency-doubling clock signal was solved, and a stable output of the high-frequency reference clock signal was achieved, meeting the requirements of the quantum computing measurement and control system and improving the reliability and maintainability of the circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ORIGIN QUANTUM COMPUTING TECH (HEFEI) CO LTD
- Filing Date
- 2025-06-30
- Publication Date
- 2026-07-03
AI Technical Summary
The existing phase-locked loop circuits suffer from phase noise degradation during frequency multiplication, making it difficult to meet the stringent requirements of quantum computing measurement and control systems for high-frequency reference clock signals. In particular, the low frequency of the phase detector in traditional phase-locked loop circuits necessitates the use of high-frequency dividers and frequency dividers, which further deteriorates the near-end phase noise performance.
A phase-locked loop circuit design combining a mixer, loop filter, and voltage-controlled oscillator is adopted. Through low-pass filtering and dynamic frequency adjustment, the phase noise at the far and near ends of the frequency multiplication clock signal is improved, avoiding the use of high-frequency dividers and reducing near-end phase noise in the feedback link.
It significantly improves the near-end and far-end phase noise performance of the frequency multiplication clock signal, enabling the phase noise level of the stable output frequency signal of the voltage-controlled oscillator to meet the requirements of quantum computing measurement and control systems, and enhancing the reliability and maintainability of the phase-locked loop circuit.
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Figure CN224459778U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of quantum computer technology, and in particular to a phase-locked loop circuit, a quantum computing measurement and control system, and a quantum computer. Background Technology
[0002] A quantum computer is a high-performance computing device based on the principles of quantum mechanics. It consists of core components such as quantum chips and a quantum measurement and control integrated machine, used to perform high-speed mathematical and logical operations and process quantum information. In the quantum computing measurement and control system of a quantum computer, the radio frequency transmission and acquisition link relies on a high-frequency reference clock signal, typically 3-8 GHz. Currently, this high-frequency reference clock signal is usually obtained by multiplying a lower-frequency clock signal using a multi-stage frequency multiplier circuit. However, the frequency multiplication process causes phase noise to deteriorate at a rate of 20logN (where N is the number of frequency multiplications), making it difficult for the phase noise level of the high-frequency reference clock signal output by the frequency multiplier circuit to meet the stringent requirements of the quantum computing measurement and control system.
[0003] Existing phase-locked loop (PLL) circuits are widely used to optimize phase noise, and they typically consist of a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). While such PLL circuits can effectively optimize the far-end phase noise of the high-frequency reference clock signal generated by the aforementioned frequency multiplier circuit, the low phase detection frequency of the phase detector necessitates a high-ratio divider in the feedback link from the VCO output signal to the phase detector. This further deteriorates the near-end phase noise performance of the final signal, thus limiting its application in quantum computers.
[0004] It should be noted that the information disclosed in the background section of this application is intended only to enhance the understanding of the general background of this application, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content
[0005] The purpose of this invention is to provide a phase-locked loop circuit, a quantum computing measurement and control system, and a quantum computer to optimize the phase noise performance of high-frequency frequency multiplication clock signals, so that the phase noise level of the target frequency signal output by the voltage-controlled oscillator can meet the stringent requirements of the quantum computing measurement and control system for high-frequency reference clock signals.
[0006] To achieve the above objectives, this utility model provides the following technical solution:
[0007] The first aspect of this utility model provides a phase-locked loop circuit, comprising:
[0008] A mixer, wherein the two input terminals of the mixer are respectively used to receive a frequency signal and a frequency-multiplied clock signal after frequency multiplication, so as to generate a difference frequency signal based on the frequency difference between the frequency-multiplied clock signal and the frequency signal.
[0009] A loop filter, the input of which is electrically connected to the output of the mixer, is used to perform low-pass filtering on the difference frequency signal and generate a first voltage-controlled signal.
[0010] A voltage-controlled oscillator, the input of which is electrically connected to the output of the loop filter, outputs the frequency signal and adjusts the frequency of the frequency signal according to the first voltage control signal until it is locked to the target frequency.
[0011] The phase-locked loop circuit described above further includes: a power divider module, wherein the input terminal of the power divider module is electrically connected to the output terminal of the voltage-controlled oscillator, and one of the plurality of output terminals of the power divider module is electrically connected to one input terminal of the mixer, so as to divide the frequency signal into multiple paths and output them respectively at the plurality of output terminals.
[0012] As described above, the phase-locked loop circuit further includes, in this case, an amplifier and a power divider.
[0013] The input terminal of the amplifier is electrically connected to the output terminal of the voltage-controlled oscillator to amplify the frequency signal.
[0014] The input terminal of the power divider is electrically connected to the output terminal of the amplifier, and one of the multiple output terminals of the power divider is electrically connected to one input terminal of the mixer, so as to divide the amplified frequency signal into multiple paths and output them at multiple output terminals respectively.
[0015] The phase-locked loop circuit described above further includes an attenuator, which is electrically connected between the power divider and the mixer, for reducing the power of the divided frequency signal to a preset range.
[0016] The phase-locked loop circuit described above further includes an LDO regulator for supplying power to the loop filter.
[0017] The phase-locked loop circuit described above further includes a capture circuit for providing a second voltage-controlled signal, which serves as an initial voltage-controlled signal to cause the voltage-controlled oscillator to output the frequency signal.
[0018] As described above, the phase-locked loop circuit further includes a triangular wave generation circuit.
[0019] As described above, the phase-locked loop circuit further includes a sapphire dielectric oscillator.
[0020] The second aspect of this utility model provides a quantum computing measurement and control system, including a quantum measurement and control link and the aforementioned phase-locked loop circuit. The quantum measurement and control link is electrically connected to the output terminal of the phase-locked loop circuit to use the frequency signal of the target frequency as a reference clock signal.
[0021] The third aspect of this utility model provides a quantum computer, characterized in that it includes the above-mentioned quantum computing measurement and control system.
[0022] The beneficial effects of this utility model are as follows:
[0023] In the phase-locked loop circuit of this application, the loop filter, through its low-pass filtering function, combines with the dynamic frequency adjustment function of the voltage-controlled oscillator to work together to improve the far-end and near-end phase noise of the frequency-multiplied clock signal. Furthermore, this circuit employs a mixer, effectively avoiding the problem in traditional phase-locked loop circuits where a high-frequency divider is required due to the low frequency of the phase detector. This significantly reduces the near-end phase noise introduced in the feedback link and effectively improves near-end phase noise performance.
[0024] In summary, the phase-locked loop circuit of this application improves the near-end and far-end phase noise performance of the frequency-doubled clock signal, enabling the phase noise level of the target frequency signal stably output by the voltage-controlled oscillator to meet the requirements of the quantum computing measurement and control system for a high-frequency reference clock signal, and thus can be used as a high-frequency reference clock signal.
[0025] The quantum computing measurement and control system and quantum computer provided by this utility model include the aforementioned phase-locked loop circuit, and therefore have the same beneficial effects, which will not be repeated here. Attached Figure Description
[0026] Figure 1 A schematic diagram of the phase-locked loop circuit provided in the embodiment of this utility model. Figure 1 ;
[0027] Figure 2 A schematic diagram of the phase-locked loop circuit provided in the embodiment of this utility model. Figure 2 ;
[0028] Figure 3 A schematic diagram of the power distribution module provided in an embodiment of this utility model;
[0029] In the attached diagram, the following are the reference numerals: 10, mixer; 20, loop filter; 30, voltage-controlled oscillator; 40, power divider module; 41, amplifier; 42, power divider; 50, attenuator; 60, amplifier circuit. Detailed Implementation
[0030] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of this application. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0031] In the description of this utility model, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.
[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0033] Figure 1 A schematic diagram of the phase-locked loop circuit provided in the embodiment of this utility model. Figure 1 ;like Figure 1 As shown: This application discloses a phase-locked loop circuit, including:
[0034] Mixer 10 has two input terminals for receiving a frequency signal and a frequency-multiplied clock signal after frequency multiplication, respectively, to generate a difference frequency signal based on the frequency difference between the frequency-multiplied clock signal and the frequency signal.
[0035] The input terminal of the loop filter 20 is electrically connected to the output terminal of the mixer 10 to perform low-pass filtering on the difference frequency signal and generate the first voltage-controlled signal.
[0036] The voltage-controlled oscillator 30 has its input terminal electrically connected to the output terminal of the loop filter 20 to output a frequency signal, and adjusts the frequency of the frequency signal according to the first voltage control signal until it is locked to the target frequency.
[0037] The working principle of the phase-locked loop circuit in this embodiment is as follows: Mixer 10 accurately compares the frequency signal output by voltage-controlled oscillator 30 with the frequency-multiplied clock signal after frequency multiplication, generating a difference frequency signal representing the frequency difference between the two. Loop filter 20 performs low-pass filtering on the difference frequency signal to generate a first voltage-controlled signal. Voltage-controlled oscillator 30 adjusts the frequency of its output frequency signal according to the first voltage-controlled signal until the frequency of the frequency signal is locked to the target frequency.
[0038] In the phase-locked loop circuit of this embodiment, the loop filter 20, through its low-pass filtering function, combines with the dynamic frequency adjustment function of the voltage-controlled oscillator 30 to work together to improve the far-end and near-end phase noise of the frequency-multiplied clock signal. Furthermore, this circuit employs a mixer 10, effectively avoiding the problem in traditional phase-locked loop circuits where a high-frequency divider is required due to the low frequency of the phase detector. This significantly reduces the near-end phase noise introduced in the feedback link and effectively improves near-end phase noise performance.
[0039] In summary, the phase-locked loop (PLL) circuit of this embodiment improves the near-end and far-end phase noise performance of the frequency-doubling clock signal, ensuring that the phase noise level of the target frequency signal stably output by the voltage-controlled oscillator 30 meets the requirements of the quantum computing measurement and control system for a high-frequency reference clock signal, and can be used as a high-frequency reference clock signal. Furthermore, because the PLL circuit of this embodiment uses fewer components and has a more streamlined circuit structure, the installation, maintenance, and debugging difficulty of the PLL circuit are significantly reduced, effectively improving the reliability and maintainability of the PLL circuit.
[0040] The frequency-multiplied clock signal in this embodiment is a high-frequency clock signal obtained by multiplying a low-frequency clock signal, typically between 3-8 GHz. The specific circuit for the frequency multiplication process is not limited. For example, the frequency-multiplied clock signal can be obtained by processing a 100 MHz low-frequency clock signal through a frequency multiplier circuit. This circuit includes multiple amplifiers connected in series and frequency multiplier elements (e.g., frequency multipliers) between any two adjacent amplifiers. The amplifiers amplify the power of the input signal, and the frequency multiplier elements amplify the frequency of the amplified signal. The specific number of amplifiers and frequency multiplier elements in the frequency multiplier circuit depends on the required frequency of the frequency-multiplied clock signal.
[0041] In this embodiment, the target frequency is the frequency of the frequency-multiplied clock signal after frequency multiplication.
[0042] In this embodiment, the loop filter 20 can be either active or passive. In some embodiments of this embodiment, the loop filter 20 is active. Compared to a passive loop filter, the active loop filter 20 can provide higher gain and wider loop bandwidth, thereby achieving faster lock-in time and better dynamic response. Furthermore, the active loop filter 20 helps reduce phase noise and improve frequency stability. To further reduce phase noise, the phase-locked loop circuit also includes an LDO (low dropout linear regulator) to power the loop filter 20. Using an LDO regulator to power the loop filter 20 provides a stable, low-noise power supply, thereby helping to reduce the phase noise of the phase-locked loop circuit.
[0043] In this embodiment, the type of voltage-controlled oscillator 30 is not specifically limited. In order to further reduce phase noise, in some implementations of this embodiment, the voltage-controlled oscillator 30 adopts a sapphire dielectric oscillator.
[0044] Figure 2 A schematic diagram of the phase-locked loop circuit provided in the embodiment of this utility model. Figure 2 In some implementations of this embodiment, such as Figure 2 As shown: In Figure 1 Based on the phase-locked loop circuit, the phase-locked loop circuit also includes: a power divider module 40, the input terminal of the power divider module 40 is electrically connected to the output terminal of the voltage-controlled oscillator 30, and one of the multiple output terminals of the power divider module 40 is electrically connected to one input terminal of the mixer 10, so as to divide the frequency signal into multiple paths and output them at multiple output terminals respectively.
[0045] In this embodiment, the power divider module 40 splits the frequency signal output from the voltage-controlled oscillator 30 into multiple paths, allowing the signal to be used at multiple output terminals. This not only allows the same frequency signal to be used for different circuit requirements but also helps reduce interference between different circuit sections, improving the overall stability and signal quality of the circuit. In this embodiment, the power divider module 40 is designed to have at least two output terminals, but the number is not specifically limited and can be two, three, or more. The divided frequency signals are allocated to different uses: one signal is used as a feedback signal and output to the mixer 10 to maintain the stable operation of the phase-locked loop; the remaining signals can be output to the quantum measurement and control link (e.g., the RF transmission and acquisition link) as a high-frequency reference clock signal for that link, or output to other circuits that require such signals.
[0046] Figure 3 A schematic diagram of the power divider module provided in an embodiment of this utility model; as shown Figure 3As shown: In some embodiments of this example, the power divider module 40 includes an amplifier 41 and a power divider 42; the input terminal of the amplifier 41 is electrically connected to the output terminal of the voltage-controlled oscillator 30 to amplify the frequency signal; the input terminal of the power divider 42 is electrically connected to the output terminal of the amplifier 41, and one of the multiple output terminals of the power divider 42 is electrically connected to one input terminal of the mixer 10 to divide the amplified frequency signal into multiple paths and output them at multiple output terminals respectively.
[0047] In this embodiment, the power divider module 40 amplifies the frequency signal output from the voltage-controlled oscillator 30 via amplifier 41, enhancing signal power to compensate for potential attenuation during transmission and subsequent power division, and ensuring signal integrity. The power divider 42 evenly distributes the amplified signal to multiple output terminals. This not only allows the same frequency signal to be used for different circuit requirements, such as as a feedback signal for the mixer 10 and a high-frequency reference clock signal for the quantum measurement and control link, but also helps reduce interference between different circuit sections, improving overall circuit stability and signal quality.
[0048] In some embodiments of this example, the phase-locked loop circuit further includes an attenuator 50, which is electrically connected between the power divider 42 and the mixer 10, and is used to reduce the power of the frequency signal after power division to a preset range.
[0049] In this embodiment, the preset range is the linear input power range of the mixer 10, ensuring that the mixer 10 operates within its optimal dynamic range to prevent performance degradation or damage due to excessively strong signals. Furthermore, the attenuator 50 in this embodiment can be an adjustable attenuator 50 constructed from a π-type resistor network, including series resistors (R1, R2) and parallel resistors (R3). By changing the combination of R1 / R2 / R3 resistance values, the attenuation range can be adjusted.
[0050] In this embodiment, the initial voltage control signal of the voltage-controlled oscillator 30 can be provided by the voltage-controlled oscillator 30 itself or by an external circuit. To accelerate the locking process of the phase-locked loop (PLL) circuit and improve its stability and dynamic performance, in some implementations of this embodiment, the PLL circuit further includes a spreader circuit 60 for providing a second voltage control signal. This second voltage control signal serves as the initial voltage control signal, enabling the voltage-controlled oscillator 30 to output a frequency signal. The spreader circuit 60 provides the initial voltage control signal when the PLL circuit starts up, thus prompting the frequency signal output by the voltage-controlled oscillator 30 to quickly approach the target frequency.
[0051] In this embodiment, the specific type of the capture circuit 60 is not limited. For example, it can be a Wien bridge oscillator circuit, a triangular wave generation circuit, or other circuits. In some implementations of this embodiment, the capture circuit 60 is a triangular wave generation circuit. Compared with other capture circuits 60, the triangular wave generation circuit has the advantages of fast frequency sweep, high controllability, low noise level, and simple circuit.
[0052] Based on the same concept, this application also proposes a quantum computing measurement and control system, including a quantum measurement and control link and a phase-locked loop circuit as described in the above embodiment. The quantum measurement and control link is electrically connected to the output of the phase-locked loop circuit so as to use the frequency signal of the target frequency as a reference clock signal.
[0053] The quantum computing measurement and control system of this application includes the phase-locked loop circuit of the above embodiments, and therefore has the same beneficial effects as the above phase-locked loop circuit, which will not be described again here.
[0054] Based on the same concept, this application also proposes a quantum computer, including the above-mentioned quantum computing measurement and control system.
[0055] The quantum computer of this application includes the aforementioned quantum computing measurement and control system. Since the aforementioned quantum computing measurement and control system includes the aforementioned phase-locked loop circuit, the quantum computer of this application has the same beneficial effects as the aforementioned phase-locked loop circuit, which will not be described in detail here.
[0056] In this specification, references to terms such as "some embodiments" or "examples" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0057] The above are merely preferred embodiments of this utility model and do not constitute any limitation on this utility model. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and contents disclosed in this utility model without departing from the scope of the technical solutions of this utility model shall still fall within the protection scope of this utility model.
Claims
1. A phase-locked loop circuit, characterized by comprising: include: A mixer, wherein the two input terminals of the mixer are respectively used to receive a frequency signal and a frequency-multiplied clock signal after frequency multiplication to generate a difference frequency signal based on the frequency difference between the frequency-multiplied clock signal and the frequency signal; A loop filter, the input of which is electrically connected to the output of the mixer, is used to perform low-pass filtering on the difference frequency signal and generate a first voltage-controlled signal. A voltage-controlled oscillator, the input of which is electrically connected to the output of the loop filter, outputs the frequency signal and adjusts the frequency of the frequency signal according to the first voltage control signal until it is locked to the target frequency.
2. The phase-locked loop circuit of claim 1, wherein, Also includes: The power divider module has its input terminal electrically connected to the output terminal of the voltage-controlled oscillator, and one of its multiple output terminals is electrically connected to one input terminal of the mixer, so as to divide the frequency signal into multiple paths and output them at multiple output terminals respectively.
3. The phase-locked loop circuit of claim 2, wherein, The power divider module includes: an amplifier and a power divider; The input terminal of the amplifier is electrically connected to the output terminal of the voltage-controlled oscillator to amplify the frequency signal; The input terminal of the power divider is electrically connected to the output terminal of the amplifier, and one of the multiple output terminals of the power divider is electrically connected to one input terminal of the mixer, so as to divide the amplified frequency signal into multiple paths and output them at multiple output terminals respectively.
4. The phase-locked loop circuit of claim 3, wherein, It also includes an attenuator, which is electrically connected between the power divider and the mixer, and is used to reduce the power of the frequency signal after power division to a preset range.
5. The phase-locked loop circuit of claim 1, wherein, It also includes an LDO regulator for powering the loop filter.
6. The phase-locked loop circuit of claim 1, wherein, It also includes a capture circuit for providing a second voltage control signal, which serves as an initial voltage control signal, so that the voltage-controlled oscillator outputs the frequency signal.
7. The phase-locked loop circuit of claim 6, wherein, The capture circuit includes a triangular wave generation circuit.
8. The phase-locked loop circuit of claim 1, wherein, The voltage-controlled oscillator includes a sapphire dielectric oscillator.
9. A quantum computing measurement and control system, characterized in that, It includes a quantum measurement and control link and a phase-locked loop circuit as described in any one of claims 1-8, wherein the quantum measurement and control link is electrically connected to the phase-locked loop circuit to use the frequency signal of the target frequency as a reference clock signal.
10. A quantum computer, comprising: Includes the quantum computing measurement and control system as described in claim 9.