Multilayer substrate and electronic device

Abstract

The utility model provides a kind of multilayer substrate and electronic equipment.The multilayer substrate has laminated body, the 1st conductor layer, the 2nd conductor layer and the 1st interlayer connecting conductor.There is no additional conductor layer between the negative main surface of the 1st conductor layer and the positive main surface of the 2nd conductor layer.The 1st through hole through the 1st insulator layer along the Z axis is provided in the 1st insulator layer.The 2nd through hole through the 2nd insulator layer along the Z axis is provided in the 2nd insulator layer.When viewed in downward direction, the 2nd through hole overlaps the 1st through hole.When viewed in positive direction of Z axis, the area of the end of the positive side of Z axis of the 2nd through hole is greater than the area of the end of the negative side of Z axis of the 1st through hole.The 1st interlayer connecting conductor extends along the Z axis in the 1st through hole and the 2nd through hole, and electrically connects the 1st conductor layer and the 2nd conductor layer.There is space between the boundary of the 1st insulator layer and the 2nd insulator layer and the 1st interlayer connecting conductor.

Description

Technical Field

[0001] This invention relates to a multilayer substrate having a structure in which multiple insulating layers are stacked. Background Technology

[0002] As a prior art invention related to multilayer substrates, a signal transmission line as described in, for example, Patent Document 1 is known. This signal transmission line includes interlayer connecting conductors.

[0003] Prior art literature

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent No. 7205667 Utility Model Content

[0006] Problems to be solved by utility models

[0007] Furthermore, in the field of signal transmission lines described in Patent Document 1, there is a requirement to suppress damage to interlayer conductors.

[0008] Therefore, the purpose of this invention is to provide a multilayer substrate, an electronic device, and a method for manufacturing a multilayer substrate that can suppress the breakage of interlayer interconnect conductors.

[0009] Technical solutions for solving the problem

[0010] In one aspect of the multilayer substrate involved in this utility model,

[0011] The multilayer substrate comprises a laminate, a first conductor layer, a second conductor layer, and an interlayer interconnection conductor.

[0012] The laminate has a structure in which multiple insulating layers, including a first insulating layer and a second insulating layer, are stacked along the Z-axis.

[0013] The first conductor layer and the second conductor layer each have a positive principal plane and a negative principal plane, respectively.

[0014] The first insulating layer and the second insulating layer each have a positive principal surface and a negative principal surface, respectively.

[0015] The positive principal surface of the second insulating layer is in contact with the negative principal surface of the first insulating layer.

[0016] The first conductor layer is located on the positive side of the Z-axis compared to the first insulator layer.

[0017] The second conductor layer is located on the negative side of the Z-axis compared to the second insulator layer.

[0018] There is no other conductor layer between the negative principal plane of the first conductor layer and the positive principal plane of the second conductor layer.

[0019] A first through hole is provided in the first insulating layer, extending through the first insulating layer along the Z-axis.

[0020] A second through hole is provided in the second insulating layer, extending through the second insulating layer along the Z-axis.

[0021] When viewed from a downward direction, the second through hole overlaps with the first through hole.

[0022] When viewed in the positive direction of the Z-axis, the area of ​​the end of the second through hole on the positive side of the Z-axis is greater than the area of ​​the end of the first through hole on the negative side of the Z-axis.

[0023] The first interlayer connecting conductor extends along the Z-axis within the first through-hole and the second through-hole, and electrically connects the first conductor layer and the second conductor layer.

[0024] There is a space between the boundary of the first insulating layer and the second insulating layer and the inter-layer connecting conductor.

[0025] One aspect of this utility model relates to an electronic device that includes the aforementioned multilayer substrate.

[0026] One aspect of this utility model relates to a method for manufacturing a multilayer substrate, comprising:

[0027] Preparation process: Prepare a first insulating layer and a second insulating layer having a positive principal surface and a negative principal surface arranged along the Z-axis;

[0028] The first through-hole forming process forms a first through-hole that penetrates the first insulating layer along the Z-axis;

[0029] The second through-hole forming process forms a second through-hole that penetrates the second insulating layer along the Z-axis; and

[0030] In the first interlayer conductor formation process, the first insulating layer and the second insulating layer are stacked such that the negative principal surface of the first insulating layer and the positive principal surface of the second insulating layer are in contact, and an interlayer conductor extending along the Z-axis is formed within the first through-hole and the second through-hole.

[0031] When viewed in the positive direction of the Z-axis, the area of ​​the end of the second through hole on the positive side of the Z-axis is greater than the area of ​​the end of the first through hole on the negative side of the Z-axis.

[0032] There is a space between the boundary between the first insulating layer and the second insulating layer and the inter-layer connecting conductor.

[0033] The space faces at least a portion of the inner circumferential surface of the first through hole and at least a portion of the inner circumferential surface of the second through hole.

[0034] Utility Model Effect

[0035] According to the multilayer substrate and the manufacturing method of the multilayer substrate involved in this utility model, the damage of the interlayer conductor can be suppressed. Attached Figure Description

[0036] Figure 1 This is an exploded perspective view of the multilayer substrate 10.

[0037] Figure 2 This is a cross-sectional view of the multilayer substrate 10.

[0038] Figure 3 This is a cross-sectional view of the multilayer substrate 10.

[0039] Figure 4 This is a cross-sectional view during the manufacturing of the multilayer substrate 10.

[0040] Figure 5 This is a cross-sectional view of the multilayer substrate 10a.

[0041] Figure 6 This is a cross-sectional view of the multilayer substrate 10b.

[0042] Figure 7 This is a cross-sectional view of the multilayer substrate 10c.

[0043] Figure 8 This is a cross-sectional view of a multilayer substrate (10d).

[0044] Figure 9 This is a cross-sectional view of the multilayer substrate 10e.

[0045] Figure 10 This is a cross-sectional view of the multilayer substrate 10f.

[0046] Figure 11 This is a cross-sectional view of a 10g multilayer substrate.

[0047] Figure 12 This is a cross-sectional view of a multilayer substrate 10h.

[0048] Figure 13 This is a cross-sectional view of the multilayer substrate 10i.

[0049] Figure 14 This is a cross-sectional view of the multilayer substrate 10j.

[0050] Figure 15This is a cross-sectional view near the first interlayer interconnect conductor v3a of the multilayer substrate 10k.

[0051] Figure 16 This is a cross-sectional view near the first interlayer interconnect conductor v3a of the multilayer substrate 10l.

[0052] Figure 17 This is a cross-sectional view near the interlayer conductor v3a of the first layer of the multilayer substrate 10m.

[0053] Figure 18 This is a cross-sectional view near the first interlayer interconnect conductor v3a of the multilayer substrate 10n.

[0054] Figure 19 This is a cross-sectional view of a multilayer substrate 10°.

[0055] Figure 20 This is a cross-sectional view of a 10p multilayer substrate.

[0056] Figure 21 This is a cross-sectional view of an electronic device 1 having a multilayer substrate 10.

[0057] Explanation of reference numerals in the attached figures

[0058] 1: Electronic devices

[0059] 10, 10a~10p: Multilayer substrate

[0060] 12: Layered bodies

[0061] 16a~16f: Insulating layer

[0062] 18a, 18b: Protective layers

[0063] 20: Signal Conductor Layer

[0064] 22: First grounding conductor layer

[0065] 22a: First conductor layer

[0066] 24: Second grounding conductor layer

[0067] 25: Third grounding conductor layer

[0068] 25a: Second conductor layer

[0069] 26a, 26b: Install electrodes

[0070] 100: Casing

[0071] A1: Interval 1

[0072] A2: Second Interval

[0073] CP: Central Committee

[0074] DP: Lower end

[0075] E: Outer edge

[0076] MP: Middle section

[0077] Sp1, Sp2: Space

[0078] UP: Upper end

[0079] h0: Through hole

[0080] h1a, h3a, h3d, h4a, h4d: First through hole

[0081] h1b, h3b, h3c, h4b, h4c: Second through hole

[0082] h3e, h3f: Third through hole

[0083] v1~v4, v3a, v3b, v4a, v4b: Interlayer conductors of the first layer

[0084] V1, V3a~V3c, V4a~V4c, V11a~V11e, V13a~V13c, V14a~V14e: Interlayer conductors of the second layer. Detailed Implementation

[0085] (Implementation Method)

[0086] [Structure of multilayer substrates]

[0087] Hereinafter, the structure of the multilayer substrate 10 according to the embodiments of the present invention will be described with reference to the accompanying drawings. Figure 1 This is an exploded perspective view of the multilayer substrate 10. Figure 2 as well as Figure 3 This is a cross-sectional view of the multilayer substrate 10. Figure 2 In, it is shown Figure 1 The cross-section at point AA. Figure 3 In, it is shown Figure 1 The cross-section at BB. Additionally, at... Figure 1 In the text, only representative inter-layer connecting conductors v3 and v4 among the multiple inter-layer connecting conductors v3 and v4 are marked with reference labels.

[0088] In this specification, directions are defined as follows: The stacking direction of the laminate 12 of the multilayer substrate 10 is parallel to the vertical axis. Furthermore, the vertical axis coincides with the Z-axis. The upward direction is the positive direction of the Z-axis. The downward direction is the negative direction of the Z-axis. Furthermore, the direction in which the signal conductor layer 20 of the multilayer substrate 10 extends is parallel to the left-right axis. Furthermore, when viewed from the downward direction, the linewidth direction of the signal conductor layer 20 is parallel to the front-back axis. The vertical axis, front-back axis, and left-right axis are orthogonal to each other. Alternatively, the vertical axis, left-right axis, and front-back axis may differ from the vertical axis, left-right axis, and front-back axis used when the multilayer substrate 10 is employed.

[0089] Hereinafter, X refers to a component or part of the multilayer substrate 10. In this specification, unless otherwise specified, the various parts of X are defined as follows: Front part of X means the front half of X. Rear part of X means the rear half of X. Left part of X means the left half of X. Right part of X means the right half of X. Upper part of X means the upper half of X. Lower part of X means the lower half of X. Front end of X means the end of X in the forward direction. Rear end of X means the end of X in the rear direction. Left end of X means the end of X in the left direction. Right end of X means the end of X in the right direction. Upper end of X means the end of X in the upward direction. Lower end of X means the end of X in the downward direction. Front end of X means the front end of X and its vicinity. Rear end of X means the rear end of X and its vicinity. The left end of X refers to the left side of X and its vicinity. The right end of X refers to the right side of X and its vicinity. The upper end of X refers to the upper part of X and its vicinity. The lower end of X refers to the lower part of X and its vicinity.

[0090] First, refer to Figure 1 The structure of the multilayer substrate 10 will now be described. The multilayer substrate 10 transmits high-frequency signals. In electronic devices such as smartphones, the multilayer substrate 10 is used to electrically connect two circuits. For example... Figure 1 As shown, the multilayer substrate 10 includes a laminate 12, protective layers 18a and 18b, a signal conductor layer 20, a first ground conductor layer 22 (first conductor layer), a second ground conductor layer 24, a third ground conductor layer 25 (second conductor layer), mounting electrodes 26a and 26b, first interlayer connection conductors v1 and v2, a plurality of first interlayer connection conductors v3, and a plurality of first interlayer connection conductors v4.

[0091] The laminate 12 has a plate shape. Therefore, the laminate 12 has an upper main surface and a lower main surface located below the upper main surface. The upper and lower main surfaces of the laminate 12 have a rectangular shape with long sides extending along the left and right axes. Therefore, the length of the laminate 12 along the left and right axes is longer than the length along the front and rear axes. The laminate 12 is flexible.

[0092] like Figure 1 As shown, the laminate 12 has a structure in which multiple insulating layers 16a to 16d, including insulating layer 16a (first insulating layer) and insulating layer 16b (second insulating layer), are stacked along a vertical axis (Z-axis). Insulating layers 16a to 16d each have an upper principal surface (positive principal surface) and a lower principal surface (negative principal surface). The insulating layers 16a to 16d are arranged sequentially from top to bottom. Thus, the upper principal surface (positive principal surface) of insulating layer 16b (second insulating layer) is in contact with the negative principal surface of insulating layer 16a (first insulating layer). The lower principal surface of insulating layer 16c is in contact with the upper principal surface of insulating layer 16d. The material of insulating layers 16a to 16d is, for example, a thermoplastic resin. The thermoplastic resin is, for example, a liquid crystal polymer. In this way, the material of insulating layers 16a to 16d (the material of the first insulating layer and the material of the second insulating layer) is a flexible resin. Furthermore, in insulating layers 16a to 16d, adjacent insulating layers are fused together. That is, insulating layer 16a (first insulating layer) and insulating layer 16b (second insulating layer) are fused together. Insulating layer 16c and insulating layer 16d are fused together.

[0093] High-frequency signals are transmitted in the signal conductor layer 20. For example... Figure 1 As shown, the signal conductor layer 20 is disposed in the laminate 12. Figure 1 As shown, the signal conductor layer 20 is located on the lower main surface of the insulating layer 16b. The signal conductor layer 20 has a linear shape extending along the left and right axes.

[0094] like Figure 1 As shown, a first ground conductor layer 22 is disposed on the laminate 12. The first ground conductor layer 22 is located above the signal conductor layer 20, and overlaps with the signal conductor layer 20 when viewed downwards. In this embodiment, the first ground conductor layer 22 is located on the upper main surface of the insulator layer 16a. Therefore, the first ground conductor layer 22 (first conductor layer) is located above the insulator layer 16a (first insulator layer) (on the positive side of the Z-axis). Furthermore, the first ground conductor layer 22 covers approximately the entire upper main surface of the insulator layer 16a. A ground potential is connected to the first ground conductor layer 22.

[0095] like Figure 1As shown, a second ground conductor layer 24 is disposed in the laminate 12. The second ground conductor layer 24 is located below the signal conductor layer 20, and overlaps with the signal conductor layer 20 when viewed downwards. In this embodiment, the second ground conductor layer 24 is located on the lower main surface of the insulator layer 16d. Therefore, the second ground conductor layer 24 is located below the insulator layer 16d. Furthermore, the second ground conductor layer 24 covers approximately the entire lower main surface of the insulator layer 16d. A ground potential is connected to the second ground conductor layer 24. The signal conductor layer 20, the first ground conductor layer 22, and the second ground conductor layer 24, as described above, have a stripline structure.

[0096] like Figure 1 As shown, a third ground conductor layer 25 is disposed in the laminate 12. The third ground conductor layer 25 is located lower than the first ground conductor layer 22 and higher than the second ground conductor layer 24. In this embodiment, the third ground conductor layer 25 is located on the lower main surface of the insulator layer 16b. Therefore, the third ground conductor layer 25 (the second conductor layer) is located lower (on the negative side of the Z-axis) than the insulator layer 16b (the second insulator layer). Furthermore, the third ground conductor layer 25 covers approximately the entire lower main surface of the insulator layer 16b. However, the third ground conductor layer 25 is not connected to the signal conductor layer 20. Therefore, an opening is provided in the third ground conductor layer 25. Moreover, the signal conductor layer 20 is located within the opening. A ground potential is connected to the third ground conductor layer 25.

[0097] like Figure 1 As shown, mounting electrode 26a is disposed on the laminate 12. Mounting electrode 26a is located on the upper main surface of laminate 12. More specifically, mounting electrode 26a is located at the left end of the upper main surface of insulating layer 16a. When viewed from the downward direction, mounting electrode 26a overlaps with the left end of signal conductor layer 20. When viewed from the downward direction, mounting electrode 26a has a rectangular shape. Mounting electrode 26a is an external terminal for high-frequency signal input / output. Mounting electrode 26a does not contact the first ground conductor layer 22. The construction of mounting electrode 26b is symmetrical to that of mounting electrode 26a, therefore its description is omitted.

[0098] like Figure 1 As shown, the first interlayer connecting conductor v1 is disposed in the laminate 12. Figure 1 as well as Figure 2 As shown, the first interlayer connecting conductor v1 electrically connects the mounting electrode 26a and the left end of the signal conductor layer 20. More specifically, a first through-hole h1a is provided in the insulating layer 16a (first insulating layer) extending along the vertical axis (Z-axis) through the insulating layer 16a (first insulating layer). The first through-hole h1a has a tapered shape that tapers upwards (in the positive direction of the Z-axis). Therefore, the upper end of the first through-hole h1a is thinner than the lower end of the first through-hole h1a.

[0099] A second through hole h1b is provided in the insulating layer 16b (the second insulating layer) and extends along the vertical axis (Z-axis) through the insulating layer 16b (the second insulating layer). The second through hole h1b has a tapered shape that tapers downwards (in the negative direction of the Z-axis). Therefore, the lower end of the second through hole h1b is thinner than the upper end of the second through hole h1b.

[0100] When viewed downwards, the second through hole h1b overlaps with the first through hole h1a. When viewed upwards (in the positive Z-axis direction), the area of ​​the upper end (the end on the positive Z-axis side) of the second through hole h1b is greater than the area of ​​the lower end (the end on the negative Z-axis side) of the first through hole h1a. Therefore, when viewed upwards (in the positive Z-axis direction), the lower end (the end on the negative Z-axis side) of the first through hole h1a is recessed into the upper end (the end on the positive Z-axis side) of the second through hole h1b. That is, when viewed upwards, the lower end of the first through hole h1a does not extend beyond the upper end of the second through hole h1b. As described above, the second through hole h1b is connected to the first through hole h1a.

[0101] The first-layer interconnect conductor v1 extends along the vertical axis (Z-axis) within the first through-hole h1a and the second through-hole h1b. The upper end UP of the first-layer interconnect conductor v1 contacts the mounting electrode 26a. The lower end DP of the first-layer interconnect conductor v1 contacts the left end of the signal conductor layer 20. The first-layer interconnect conductor v1 has an intermediate portion MP located between the upper end UP (the end on the positive side of the Z-axis) and the lower end DP (the end on the negative side of the Z-axis). The intermediate portion MP is located at the same position as the central CP on the vertical axis (Z-axis) of the first-layer interconnect conductor v1. However, the intermediate portion MP may not be aligned with the central CP. The first interlayer connecting conductor v1 has a first section A1 and a second section A2. The first section A1 has a tapered shape that tapers as it approaches the middle section MP from the upper end UP (the end on the positive side of the Z-axis). The second section A2 has a tapered shape that tapers as it approaches the middle section MP from the lower end DP (the end on the negative side of the Z-axis).

[0102] Furthermore, a space Sp0 exists between the boundary of insulating layer 16a (first insulating layer) and insulating layer 16b (second insulating layer) and the first interlayer connecting conductor v1. Moreover, the space Sp0 exists between the inner peripheral surface of the second through-hole h1b and the central CP on the upper and lower axes (Z-axis) of the first interlayer connecting conductor v1. The space Sp0 faces at least a portion of the inner peripheral surface of the first through-hole h1a and at least a portion of the inner peripheral surface of the second through-hole h1b. In this embodiment, the space Sp0 faces the entire inner peripheral surface of the first through-hole h1a and the entire inner peripheral surface of the second through-hole h1b. Therefore, the first interlayer connecting conductor v1 is only connected to the upper end of the inner peripheral surface of the first through hole h1a and the lower end of the inner peripheral surface of the second through hole h1b, and is not connected to the portion other than the upper end of the inner peripheral surface of the first through hole h1a and the portion other than the lower end of the inner peripheral surface of the second through hole h1b. Therefore, by the existence of space Sp0, the first interlayer connecting conductor v1 does not contact the boundary between the insulating layer 16a (first insulating layer) and the insulating layer 16b (second insulating layer).

[0103] Furthermore, when viewed in the downward direction (the negative direction of the Z-axis), at least a portion of the side surface of the first interlayer connecting conductor v1 in the first interval A1, at least a portion of the side surface of the first interlayer connecting conductor v1 in the second interval A2, and at least a portion of the space Sp0 overlap. Thus, a portion of the space Sp0 exists between the side surface of the first interlayer connecting conductor v1 in the first interval A1 and the side surface of the first interlayer connecting conductor v1 in the second interval A2.

[0104] Furthermore, the construction of mounting electrode 26b and interlayer connecting conductor v2 is symmetrical to that of mounting electrode 26a and interlayer connecting conductor v1, therefore, the description is omitted. High-frequency signals with frequencies of 1 GHz or higher and 1 THz or lower are transmitted using the mounting electrodes 26a and 26b (first conductor layer), signal conductor layer 20 (second conductor layer), and interlayer connecting conductors v1 and v2 as described above.

[0105] like Figure 3As shown, the plurality of first-layer interconnecting conductors v3 respectively include first-layer interconnecting conductors v3a and v3b. The plurality of first-layer interconnecting conductors v3a electrically connect the first ground conductor layer 22 (first conductor layer) and the third ground conductor layer 25 (second conductor layer). More specifically, in the insulating layer 16a (first insulating layer), a plurality of first through holes h3a are provided, which penetrate the insulating layer 16a (first insulating layer) along the vertical axis (Z-axis). The plurality of first through holes h3a each have a tapered shape that tapers upwards (in the positive direction of the Z-axis). Therefore, the upper end of the first through hole h3a is thinner than the lower end of the first through hole h3a. When viewed downwards, the plurality of first through holes h3a are located ahead of the signal conductor layer 20. The plurality of first through holes h3a are arranged in a row along the horizontal axis.

[0106] In insulating layer 16b (second insulating layer), a plurality of second through holes h3b are provided, extending along the vertical axis (Z-axis) through insulating layer 16b (second insulating layer). Each of the plurality of second through holes h3b has a tapered shape that tapers downwards (in the negative direction of the Z-axis). Therefore, the lower end of each second through hole h3b is thinner than its upper end. When viewed downwards, the plurality of second through holes h3b are located ahead of the signal conductor layer 20. The plurality of second through holes h3b are arranged in a row along the horizontal axis. That is, the plurality of second through holes h3b are arranged along the signal line.

[0107] When viewed downwards, the multiple second through holes h3b overlap with the multiple first through holes h3a. When viewed upwards (in the positive Z-axis direction), the area of ​​the upper end (the end on the positive Z-axis side) of the second through hole h3b is greater than the area of ​​the lower end (the end on the negative Z-axis side) of the first through hole h3a. Therefore, when viewed upwards (in the positive Z-axis direction), the lower end (the end on the negative Z-axis side) of the first through hole h3a is recessed into the upper end (the end on the positive Z-axis side) of the second through hole h3b. That is, when viewed upwards, the lower end of the first through hole h3a does not extend beyond the upper end of the second through hole h3b. As described above, the multiple second through holes h3b are connected to the multiple first through holes h3a.

[0108] The first interlayer connecting conductor v3a extends along the vertical axis (Z-axis) within the first through hole h3a and the second through hole h3b. The upper end UP of the first interlayer connecting conductor v3a contacts the first grounding conductor layer 22. The lower end DP of the first interlayer connecting conductor v3a contacts the third grounding conductor layer 25. The first interlayer connecting conductor v3a has an intermediate portion MP located between the upper end UP (the end on the positive side of the Z-axis) and the lower end DP (the end on the negative side of the Z-axis). The intermediate portion MP is located at the same position as the central CP on the vertical axis (Z-axis) of the first interlayer connecting conductor v3a. However, the intermediate portion MP may not be aligned with the central CP. The first interlayer connecting conductor v3a has a first section A1 and a second section A2. The first section A1 has a tapered shape that tapers as it approaches the middle section MP from the upper end UP (the end on the positive side of the Z-axis). The second section A2 has a tapered shape that tapers as it approaches the middle section MP from the lower end DP (the end on the negative side of the Z-axis).

[0109] Furthermore, a space Sp1 exists between the boundary of insulating layer 16a (first insulating layer) and insulating layer 16b (second insulating layer) and the first interlayer connecting conductor v3a. Moreover, space Sp1 exists between the inner peripheral surface of the second through-hole h3b and the central CP on the upper and lower axes (Z-axis) of the first interlayer connecting conductor v3a. Space Sp1 faces at least a portion of the inner peripheral surface of the first through-hole h3a and at least a portion of the inner peripheral surface of the second through-hole h3b. In this embodiment, space Sp1 faces the entire inner peripheral surface of the first through-hole h3a and the entire inner peripheral surface of the second through-hole h3b. Therefore, the first interlayer connecting conductor v3a is only connected to the upper end of the inner peripheral surface of the first through hole h3a and the lower end of the inner peripheral surface of the second through hole h3b, and is not connected to the portion other than the upper end of the inner peripheral surface of the first through hole h3a and the portion other than the lower end of the inner peripheral surface of the second through hole h3b. Therefore, by the existence of space Sp1, the first interlayer connecting conductor v3a does not contact the boundary between the insulating layer 16a (first insulating layer) and the insulating layer 16b (second insulating layer).

[0110] Furthermore, when viewed in the downward direction (the negative direction of the Z-axis), at least a portion of the side surface of the first interlayer connecting conductor v3a in the first interval A1, at least a portion of the side surface of the first interlayer connecting conductor v3a in the second interval A2, and at least a portion of the space Sp1 overlap. Thus, a portion of the space Sp1 exists between the side surface of the first interlayer connecting conductor v3a in the first interval A1 and the side surface of the first interlayer connecting conductor v3a in the second interval A2.

[0111] Multiple first-layer interconnecting conductors v3b electrically connect the second ground conductor layer 24 and the third ground conductor layer 25, respectively. More specifically, multiple first through-holes h3d are provided in the insulating layer 16d, extending through the insulating layer 16d along the vertical axis. Each of the multiple first through-holes h3d has a tapered shape that tapers downwards. Therefore, the lower end of the first through-hole h3d is thinner than the upper end of the first through-hole h3d. When viewed downwards, the multiple first through-holes h3d are located ahead of the signal conductor layer 20. The multiple first through-holes h3d are arranged in a row along the left-right axis.

[0112] In the insulating layer 16c, a plurality of second through holes h3c are provided, extending through the insulating layer 16c along the vertical axis. Each of the plurality of second through holes h3c has a tapered shape that tapers upwards. Therefore, the upper end of each second through hole h3c is thinner than its lower end. When viewed downwards, the plurality of second through holes h3c are located ahead of the signal conductor layer 20. The plurality of second through holes h3c are arranged in a row along the left-right axis. The plurality of second through holes h3c are arranged along the signal line.

[0113] When viewed downwards, the multiple second through holes h3c overlap with the multiple first through holes h3d. When viewed upwards, the area of ​​the lower end of the second through hole h3c is larger than the area of ​​the upper end of the first through hole h3d. Therefore, when viewed upwards, the upper end of the first through hole h3d is recessed into the lower end of the second through hole h3c. That is, when viewed upwards, the upper end of the first through hole h3d does not extend beyond the lower end of the second through hole h3c. As described above, the multiple second through holes h3c are connected to the multiple first through holes h3d.

[0114] The first interlayer connecting conductor v3b extends along the vertical axis within the first through hole h3d and the second through hole h3c. The upper end UP of the first interlayer connecting conductor v3b contacts the third grounding conductor layer 25. The lower end DP of the first interlayer connecting conductor v3b contacts the second grounding conductor layer 24. The first interlayer connecting conductor v3b has an intermediate portion MP located between the upper end UP and the lower end DP of the first interlayer connecting conductor v3b. The intermediate portion MP is located at the same position as the central CP on the vertical axis (Z-axis) of the first interlayer connecting conductor v3b. However, the intermediate portion MP may not be consistent with the central CP. The first interlayer connecting conductor v3b has a first section A1 and a second section A2. The first section A1 has a tapered shape that tapers as it approaches the intermediate portion MP from the lower end DP, and the second section A2 has a tapered shape that tapers as it approaches the intermediate portion MP from the upper end UP.

[0115] Furthermore, a space Sp2 exists between the boundaries of insulator layers 16d and 16c and the first interlayer connecting conductor v3b. Space Sp2 faces at least a portion of the inner circumferential surface of the first through-hole h3d and at least a portion of the inner circumferential surface of the second through-hole h3c. In this embodiment, space Sp2 faces the entire inner circumferential surface of the first through-hole h3d and the entire inner circumferential surface of the second through-hole h3c. Therefore, the first interlayer connecting conductor v3b only contacts the lower end of the inner circumferential surface of the first through-hole h3d and the upper end of the inner circumferential surface of the second through-hole h3c, and not the portion other than the lower end of the inner circumferential surface of the first through-hole h3d or the portion other than the upper end of the inner circumferential surface of the second through-hole h3c. Therefore, by the existence of space Sp2, the first interlayer connecting conductor v3b does not contact the boundaries of insulator layers 16d and 16c.

[0116] The multiple interlayer connecting conductors v4 have a symmetrical structure with the multiple interlayer connecting conductors v3, so the description is omitted. The first grounding conductor layer 22 (first conductor layer), the third grounding conductor layer 25 (second conductor layer), and the interlayer connecting conductors v3a, v3b, v4a, and v4b are connected to the grounding potential as described above.

[0117] like Figure 1 As shown, the protective layer 18a covers a portion of the upper main surface of the laminate 12. Thus, the protective layer 18a protects the first ground conductor layer 22. However, rectangular openings H1 to H6 are provided in the protective layer 18a. When viewed downwards, opening H1 overlaps with the mounting electrode 26a. Therefore, the mounting electrode 26a is exposed from the multilayer substrate 10 to the outside. Opening H2 is located before opening H1. A portion of the first ground conductor layer 22 is exposed from the multilayer substrate 10 to the outside via opening H2. Opening H3 is located after opening H1. A portion of the first ground conductor layer 22 is exposed from the multilayer substrate 10 to the outside via opening H3. Thus, a portion of the first ground conductor layer 22 functions as a grounding terminal. Furthermore, the structures of openings H4 to H6 are symmetrical to the structures of openings H1 to H3, therefore, their description is omitted.

[0118] Protective layer 18b covers the lower main surface of laminate 12. Thus, protective layer 18b protects the second grounding conductor layer 24. The materials of the protective layers 18a and 18b are different from the materials of the insulating layers 16a to 16d. Protective layers 18a and 18b are so-called solder resists. The solder resist is a mixture of alkali-soluble resin, photopolymerization initiator, epoxy resin for improving heat resistance, and inorganic powders.

[0119] The signal conductor layer 20, the first ground conductor layer 22, the second ground conductor layer 24, the third ground conductor layer 25, and the mounting electrodes 26a and 26b described above are formed, for example, by etching a metal foil disposed on the upper or lower main surface of the insulating layers 16a to 16d. The metal foil is, for example, copper foil. Thus, the signal conductor layer 20, the first ground conductor layer 22, the second ground conductor layer 24, the third ground conductor layer 25, and the mounting electrodes 26a and 26b are metal foils disposed on the main surfaces of the insulating layers 16a to 16d.

[0120] Furthermore, the first-layer interconnect conductors v1 to v4 are, for example, via conductors. The material of the first-layer interconnect conductors v1 to v4 is an alloy containing Sn. The material of the first-layer interconnect conductors v1 to v4 is, for example, solder. However, the melting point of the material of the first-layer interconnect conductors v1 to v4 may also be below the melting point of the solder used for mounting electronic components. Therefore, if the first-layer interconnect conductors v1 to v4 melt during the mounting of electronic components, the stress applied to the first-layer interconnect conductors v1 to v4 is suppressed. As a result, damage to the first-layer interconnect conductors v1 to v4 is suppressed.

[0121] Furthermore, when viewed in the downward direction (negative direction of the Z-axis), at least a portion of the side surface of the first interlayer connecting conductor v3a in the first interval A1, at least a portion of the side surface of the first interlayer connecting conductor v3a in the second interval A2, and at least a portion of the space Sp1 overlap. Thus, a portion of the space Sp1 exists between the side surface of the first interlayer connecting conductor v3a in the first interval A1 and the side surface of the first interlayer connecting conductor v3a in the second interval A2. Therefore, it becomes less likely for capacitance to form between the side surface of the first interlayer connecting conductor v3a in the first interval A1 and the side surface of the first interlayer connecting conductor v3a in the second interval A2. As a result, the formation of an LC resonant circuit between the side surface of the first interlayer connecting conductor v3a in the first interval A1 and the side surface of the first interlayer connecting conductor v3a in the second interval A2 can be suppressed, making it less likely for unwanted resonance to occur.

[0122] [Manufacturing method of multilayer substrate 10]

[0123] Next, the manufacturing method of the multilayer substrate 10 will be described with reference to the accompanying drawings. Figure 4 This is a cross-sectional view during the manufacturing of the multilayer substrate 10.

[0124] First, insulating layers 16a (first insulating layer) and 16b (second insulating layer) with an upper main surface (positive main surface) and a lower main surface (negative main surface) arranged along the vertical axis (Z-axis) are prepared (preparation step). Specifically, insulating layers 16a, 16b, and 16d with metal foil adhered to the upper or lower main surface are prepared. Then, signal conductor layer 20, first ground conductor layer 22, second ground conductor layer 24, third ground conductor layer 25, and mounting electrodes 26a and 26b are formed by patterning the metal foil. Furthermore, no metal foil is adhered to the upper or lower main surface of insulating layer 16c.

[0125] Next, as Figure 2 as well as Figure 4 As shown in the upper part, a first through hole h1a, a plurality of first through holes h3a, and a plurality of first through holes h4a are formed along the upper and lower axes (Z-axis) to penetrate the insulating layer 16a (first insulating layer) (first through hole forming process). Similarly, a plurality of first through holes h1b, a plurality of second through holes h3b, and a plurality of second through holes h4b are formed along the upper and lower axes (Z-axis) to penetrate the insulating layer 16b (second insulating layer) (second through hole forming process).

[0126] Next, insulating layers 16a to 16d are arranged sequentially from top to bottom. Then, solder is filled into the first through hole h1a, multiple first through holes h3a, multiple first through holes h4a, second through holes h1b, multiple second through holes h3b, and multiple second through holes h4b. Afterward, the laminate formed by stacking insulating layers 16a to 16d is crimped (crimping process). In the crimping process, isotropic pressing is used. Furthermore, heat treatment is performed in the crimping process. In this way, the insulator layer 16a (first insulator layer) and the insulator layer 16b (second insulator layer) are stacked such that the lower main surface (negative main surface) of the insulator layer 16a (first insulator layer) and the upper main surface (positive main surface) of the insulator layer 16b (second insulator layer) are in contact, and the first interlayer connecting conductors v1, v2, v3, v4 (first interlayer connecting conductor forming process) are formed in the first through holes h1a, h3a, h4a and the second through holes h1b, h3b, h4b extending along the upper and lower axes (Z axis).

[0127] Finally, as Figure 2 as well as Figure 3 As shown, protective layers 18a and 18b are formed on the laminate 12. After the above processes, the multilayer substrate 10 is completed.

[0128] [Effect]

[0129] According to the multilayer substrate 10, damage to the first-layer interconnect conductors v1 to v4 can be suppressed. Hereinafter, the first-layer interconnect conductor v3a will be used as an example for explanation. A multilayer substrate with a first-layer interconnect conductor extending through adjacent upper and lower insulating layers will be studied as a comparative example. Generally, if a force is applied to the multilayer substrate, a large force is applied to the first-layer interconnect conductor at the boundary between two adjacent upper and lower insulating layers. If such a large force is applied to the first-layer interconnect conductor, damage to the first-layer interconnect conductor may occur.

[0130] Therefore, in the multilayer substrate 10, when viewed from the upward direction, the area of ​​the upper end of the second through-hole h3b is larger than the area of ​​the lower end of the first through-hole h3a. Consequently, a space Sp1 is easily formed between the boundary of the insulating layers 16a and 16b and the first interlayer connection conductor v3a. Therefore, large forces exerted on the first interlayer connection conductor v3a at the boundary of the insulating layers 16a and 16b can be suppressed. As a result, according to the multilayer substrate 10, damage to the first interlayer connection conductor v3a can be suppressed.

[0131] According to the multilayer substrate 10, it is difficult for capacitance to form between the interlayer connecting conductors v1 to v4 and the surrounding conductors. Hereinafter, the interlayer connecting conductor v3a will be used as an example for explanation. Generally, the interlayer connecting conductor and the surrounding conductor face each other through an insulating layer. In this case, capacitance is formed between the interlayer connecting conductor and the surrounding conductor. Such capacitance causes the electrical characteristics of the circuit inside the multilayer substrate to change from a desired value. For example, when high-frequency signals are transmitted between the interlayer connecting conductor and the surrounding conductor, the isolation between the interlayer connecting conductor and the surrounding conductor decreases. Furthermore, when the interlayer connecting conductor is connected to ground potential and high-frequency signals are transmitted between the surrounding conductor, the characteristic impedance of the surrounding conductor decreases.

[0132] Therefore, in the multilayer substrate 10, a space Sp1 exists between the boundary of the insulating layer 16a and the insulating layer 16b and the first layer interconnect conductor v3a. Consequently, the amount of insulating layer present between the first layer interconnect conductor v3a and other conductors decreases. Therefore, the dielectric constant between the first layer interconnect conductor v3a and other conductors decreases. Based on the above, according to the multilayer substrate 10, capacitance is less likely to form between the first layer interconnect conductor v3a and surrounding conductors.

[0133] In the multilayer substrate 10, when viewed from the upward direction, the area of ​​the upper end of the second through-hole h3b is larger than the area of ​​the lower end of the first through-hole h3a. In particular, in the multilayer substrate 10, when viewed from the upward direction, the lower end of the first through-hole h3a is recessed into the upper end of the second through-hole h3b. Therefore, when stacking insulating layers 16a to 16d, even if the second through-hole h3b is offset relative to the first through-hole h3a in the forward, backward, left, or right direction, the area of ​​overlap between the upper end of the second through-hole h3b and the lower end of the first through-hole h3a when viewed from the upward direction does not easily change.

[0134] In the multilayer substrate 10, when viewed from the upward direction, the area of ​​the upper end of the second through-hole h3b is larger than the area of ​​the lower end of the first through-hole h3a. Therefore, the thickness of the first interlayer connecting conductor v3a is determined by the thickness of the first through-hole h3a. That is, a thin first interlayer connecting conductor v3a is easily formed. Furthermore, the position of the first interlayer connecting conductor v3a is determined by the upper end of the first through-hole h3a, which has a smaller area. Therefore, the first interlayer connecting conductor v3a is less likely to deviate forward, backward, leftward, or rightward within the first through-hole h3a and the second through-hole h3b. As a result, a space Sp1 is easily formed.

[0135] According to the multilayer substrate 10, damage to the first-layer interconnect conductors v1 to v4 can also be suppressed for the following reasons. Hereinafter, the first-layer interconnect conductor v3a will be used as an example for explanation. More specifically, the central CP of the upper and lower axes of the first-layer interconnect conductor v3a is relatively thin and therefore easily damaged. However, a space Sp1 exists between the inner peripheral surface of the second through-hole h3b and the central CP on the upper and lower axes of the first-layer interconnect conductor v3a. Therefore, it is not easy to apply a large force to the central CP of the upper and lower axes of the first-layer interconnect conductor v3a. As a result, according to the multilayer substrate 10, damage to the first-layer interconnect conductor v3a can be suppressed.

[0136] According to the multilayer substrate 10, damage to the first interlayer connecting conductors v1 to v4 can also be suppressed for the following reasons. Hereinafter, the first interlayer connecting conductor v3a will be used as an example for explanation. More specifically, the first interlayer connecting conductor v3a has a first section A1 and a second section A2. The first section A1 has a tapered shape that tapers as it approaches the middle section MP from the upper end UP, and the second section A2 has a tapered shape that tapers as it approaches the middle section MP from the lower end DP. Thus, the first interlayer connecting conductor v3a has a shape that narrows near the middle section MP. Therefore, a space Sp1 is easily formed between the boundary of the insulating layer 16a and the insulating layer 16b and the first interlayer connecting conductor v3a. Therefore, it is possible to suppress the application of large forces on the first interlayer connecting conductor v3a at the boundary of the insulating layer 16a and the insulating layer 16b. As a result, according to the multilayer substrate 10, damage to the first interlayer connecting conductor v3a can be suppressed.

[0137] In the multilayer substrate 10, the first interlayer connection conductor v3a has a first section A1 and a second section A2. The first section A1 has a tapered shape that tapers as it approaches the middle section MP from the upper end UP, and the second section A2 has a tapered shape that tapers as it approaches the middle section MP from the lower end DP. As a result, the area of ​​the joint between the first interlayer connection conductor v3a and the first ground conductor layer 22, and the area of ​​the joint between the first interlayer connection conductor v3a and the third ground conductor layer 25, are increased. Consequently, the bonding strength between the first interlayer connection conductor v3a and the first ground conductor layer 22, and the bonding strength between the first interlayer connection conductor v3a and the third ground conductor layer 25, are improved.

[0138] In the multilayer substrate 10, the first through-hole h3a has a tapered shape that tapers towards the top. Furthermore, the second through-hole h3b has a tapered shape that tapers towards the bottom. As a result, the area of ​​the first ground conductor layer 22 exposed in the first through-hole h3a becomes smaller, and the area of ​​the third ground conductor layer 25 exposed in the second through-hole h3b also becomes smaller.

[0139] In the multilayer substrate 10, the first through-hole h3a has a tapered shape that tapers towards the top. Furthermore, the second through-hole h3b has a tapered shape that tapers towards the bottom. As a result, a space Sp1 is easily formed between the boundary of the insulating layers 16a and 16b and the first layer inter-conductor v3a.

[0140] In the multilayer substrate 10, when viewed from below, at least a portion of the side surface of the first interlayer connecting conductor v1 in the first interval A1, at least a portion of the side surface of the first interlayer connecting conductor v1 in the second interval A2, and at least a portion of the space Sp0 overlap. Consequently, a portion of the space Sp0 exists between the side surface of the first interlayer connecting conductor v1 in the first interval A1 and the side surface of the first interlayer connecting conductor v1 in the second interval A2. Therefore, it becomes less likely for capacitance to form between the side surface of the first interlayer connecting conductor v1 in the first interval A1 and the side surface of the first interlayer connecting conductor v1 in the second interval A2. As a result, the formation of an LC resonant circuit between the side surface of the first interlayer connecting conductor v1 in the first interval A1 and the side surface of the first interlayer connecting conductor v1 in the second interval A2 can be suppressed, making it less likely for unwanted resonance to occur.

[0141] (Example 1)

[0142] Hereinafter, the multilayer substrate 10a according to the first modified example will be described with reference to the accompanying drawings. Figure 5 This is a cross-sectional view of the multilayer substrate 10a.

[0143] The multilayer substrate 10a differs from the multilayer substrate 10 in the shape of the first through-hole h3a and the shape of the second through-hole h3b. More specifically, the inner peripheral surfaces of the first through-hole h3a and the second through-hole h3b have a dome shape. In a cross-section parallel to the upper and lower axes, the inner peripheral surfaces of the first through-hole h3a and the second through-hole h3b have a curved shape. As a result, the space Sp1 becomes larger. The other structures of the multilayer substrate 10a are the same as those of the multilayer substrate 10, and therefore descriptions are omitted. The multilayer substrate 10a performs the same function as the multilayer substrate 10.

[0144] (Second variation)

[0145] Hereinafter, the multilayer substrate 10b of the second modified example will be described with reference to the accompanying drawings. Figure 6 This is a cross-sectional view of the multilayer substrate 10b.

[0146] The multilayer substrate 10b differs from the multilayer substrate 10 in the shape of the first through-hole h3a and the shape of the second through-hole h3b. More specifically, the first through-hole h3a and the second through-hole h3b are cylindrical. This allows for easy formation of the first through-hole h3a and the second through-hole h3b. The other structures of the multilayer substrate 10b are the same as those of the multilayer substrate 10, and therefore descriptions are omitted. The multilayer substrate 10b performs the same functions as the multilayer substrate 10.

[0147] (3rd variation)

[0148] Hereinafter, the multilayer substrate 10c of the third modified example will be described with reference to the accompanying drawings. Figure 7 This is a cross-sectional view of the multilayer substrate 10c.

[0149] The multilayer substrate 10c differs from the multilayer substrate 10 in the shape of the interlayer connecting conductor v3a. More specifically, in the multilayer substrate 10c, the upper end of the interlayer connecting conductor v3a is not connected to the outer edge E of the upper end of the first through-hole h3a. This increases the space Sp1. The other structures of the multilayer substrate 10c are the same as those of the multilayer substrate 10, and therefore are omitted from the description. The multilayer substrate 10c performs the same function as the multilayer substrate 10.

[0150] (4th variation)

[0151] Hereinafter, the multilayer substrate 10d involved in the fourth modified example will be described with reference to the accompanying drawings. Figure 8 This is a cross-sectional view of a multilayer substrate (10d).

[0152] The multilayer substrate 10d differs from the multilayer substrate 10 in the shape of the interlayer conductor v3a. More specifically, the upper part of the interlayer conductor v3a contacts the upper part of the inner peripheral surface of the first through-hole h3a. The other structures of the multilayer substrate 10d are the same as those of the multilayer substrate 10, and therefore are omitted from the description. The multilayer substrate 10d performs the same function as the multilayer substrate 10.

[0153] (5th variation)

[0154] Hereinafter, the multilayer substrate 10e according to the fifth modified example will be described with reference to the accompanying drawings. Figure 9 This is a cross-sectional view of the multilayer substrate 10e.

[0155] The multilayer substrate 10e differs from the multilayer substrate 10 in the shape of the first interlayer connecting conductor v3a. More specifically, the upper end of the first interlayer connecting conductor v3a extends between the lower main surface of the first ground conductor layer 22 and the upper main surface of the insulating layer 16a. As a result, the bonding strength between the first interlayer connecting conductor v3a and the first ground conductor layer 22 is improved.

[0156] Furthermore, when viewed in the downward direction (negative direction of the Z-axis), at least a portion of the side surface of the first interlayer connecting conductor v3a in the first interval A1, at least a portion of the side surface of the first interlayer connecting conductor v3a in the second interval A2, and at least a portion of the space Sp1 overlap. Thus, a portion of the space Sp1 exists between the side surface of the first interlayer connecting conductor v3a in the first interval A1 and the side surface of the first interlayer connecting conductor v3a in the second interval A2. Therefore, it becomes less likely for capacitance to form between the side surface of the first interlayer connecting conductor v3a in the first interval A1 and the side surface of the first interlayer connecting conductor v3a in the second interval A2. As a result, the formation of an LC resonant circuit between the side surface of the first interlayer connecting conductor v3a in the first interval A1 and the side surface of the first interlayer connecting conductor v3a in the second interval A2 can be suppressed, making it less likely for unwanted resonance to occur. The other structures of the multilayer substrate 10e are the same as those of the multilayer substrate 10, and therefore descriptions are omitted. The multilayer substrate 10e performs the same function as the multilayer substrate 10.

[0157] (Sixth variation)

[0158] Hereinafter, the multilayer substrate 10f involved in the sixth modified example will be described with reference to the accompanying drawings. Figure 10 This is a cross-sectional view of the multilayer substrate 10f.

[0159] The multilayer substrate 10f differs from the multilayer substrate 10 in the shape of the interlayer connecting conductor v3a. The interlayer connecting conductor v3a has a cylindrical shape. Therefore, when shear stress is applied to the interlayer connecting conductor v3a in either the left or right direction, the force is applied uniformly to the entire interlayer connecting conductor v3a. As a result, the interlayer connecting conductor v3a is less prone to breakage. The other structures of the multilayer substrate 10f are the same as those of the multilayer substrate 10, and therefore descriptions are omitted. The multilayer substrate 10f achieves the same functional effect as the multilayer substrate 10.

[0160] (Seventh variation)

[0161] Hereinafter, the multilayer substrate 10g involved in the seventh modified example will be described with reference to the accompanying drawings. Figure 11 This is a cross-sectional view of a 10g multilayer substrate.

[0162] The multilayer substrate 10g differs from the multilayer substrate 10 in the materials of the insulating layers 16a and 16d. The material of insulating layer 16a (the first insulating layer) differs from that of insulating layer 16b (the second insulating layer). The material of insulating layer 16d differs from that of insulating layer 16c. Insulating layers 16a and 16d function as adhesive layers. Furthermore, it is difficult to ensure that the thickness of insulating layers 16a and 16d along their vertical axes matches the target value. Therefore, it is sufficient to reduce the thickness of insulating layers 16a and 16d along their vertical axes, thereby lowering the dielectric constant of insulating layers 16b and 16c, and increasing the thickness of insulating layers 16b and 16c along their vertical axes. This results in excellent electrical properties and reduces deviations in electrical properties. Additionally, to lower the dielectric constant of insulating layers 16a and 16d, insulating layers 16a and 16d may also contain air bubbles. The other structures of the multilayer substrate 10g are the same as those of the multilayer substrate 10, so the description is omitted. The multilayer substrate 10g has the same function as the multilayer substrate 10.

[0163] (Example 8)

[0164] Hereinafter, the multilayer substrate 10h involved in the eighth modified example will be described with reference to the accompanying drawings. Figure 12 This is a cross-sectional view of a multilayer substrate 10h.

[0165] The multilayer substrate 10h differs from the multilayer substrate 10 in that the materials of the insulating layers 16a and 16d, and the laminate 12 further includes insulating layers 16e and 16f (the third insulating layer). The insulating layers 16e and 16f (the third insulating layer) have an upper principal surface (positive principal surface) and a lower principal surface (negative principal surface). Insulating layer 16e is located above insulating layer 16a. Therefore, the lower principal surface (negative principal surface) of insulating layer 16e (the third insulating layer) is in contact with the upper principal surface (positive principal surface) of insulating layer 16a (the first insulating layer). Insulating layer 16f is located below insulating layer 16d. Therefore, the upper principal surface of insulating layer 16f is in contact with the lower principal surface of insulating layer 16d. The materials of insulating layers 16e and 16f are the same as those of insulating layers 16b and 16c. Insulating layer 16a (first insulating layer) is an adhesive layer that bonds insulating layer 16e (third insulating layer) and insulating layer 16b (second insulating layer). Insulating layer 16d is an adhesive layer that bonds insulating layer 16f and insulating layer 16c. Thus, insulating layer 16e and insulating layer 16b are firmly bonded. Insulating layer 16c and insulating layer 16f are firmly bonded.

[0166] The first grounding conductor layer 22 is located on the upper main surface of the insulating layer 16e. The second grounding conductor layer 24 is located on the lower main surface of the insulating layer 16f. Furthermore, a third through-hole h3e is provided in the insulating layer 16e. A third through-hole h3f is provided in the insulating layer 16f. The first interlayer connecting conductor v3a extends along the vertical axis within the third through-hole h3e. The first interlayer connecting conductor v3b extends along the vertical axis within the third through-hole h3f. Thus, the upper end of the first interlayer connecting conductor v3a contacts the first grounding conductor layer 22. The lower end of the first interlayer connecting conductor v3b contacts the second grounding conductor layer 24. The other structures of the multilayer substrate 10h are the same as those of the multilayer substrate 10, and therefore descriptions are omitted. The multilayer substrate 10h performs the same functions as the multilayer substrate 10.

[0167] (9th variation)

[0168] Hereinafter, the multilayer substrate 10i according to the 9th modified example will be described with reference to the accompanying drawings. Figure 13 This is a cross-sectional view of the multilayer substrate 10i.

[0169] The multilayer substrate 10i differs from the multilayer substrate 10 in that the materials of the insulating layers 16a and 16d, and the laminate 12 further includes insulating layers 16e and 16f (the third insulating layer). The insulating layers 16e and 16f (the third insulating layer) have an upper principal surface (positive principal surface) and a lower principal surface (negative principal surface). Insulating layer 16e is located above insulating layer 16a. Therefore, the lower principal surface (negative principal surface) of insulating layer 16e (the third insulating layer) is in contact with the upper principal surface (positive principal surface) of insulating layer 16a (the first insulating layer). Insulating layer 16f is located below insulating layer 16d. Therefore, the upper principal surface of insulating layer 16f is in contact with the lower principal surface of insulating layer 16d. The materials of insulating layers 16e and 16f are the same as those of insulating layers 16b and 16c. Insulating layer 16a (first insulating layer) is an adhesive layer that bonds insulating layer 16e (third insulating layer) and insulating layer 16b (second insulating layer). Insulating layer 16d is an adhesive layer that bonds insulating layer 16f and insulating layer 16c. Thus, insulating layer 16e and insulating layer 16b are firmly bonded. Insulating layer 16c and insulating layer 16f are firmly bonded.

[0170] The first grounding conductor layer 22 is located on the lower main surface of the insulating layer 16e. The second grounding conductor layer 24 is located on the upper main surface of the insulating layer 16f. Therefore, the upper end of the interlayer connecting conductor v3a contacts the first grounding conductor layer 22. The lower end of the interlayer connecting conductor v3b contacts the second grounding conductor layer 24. The other structures of the multilayer substrate 10i are the same as those of the multilayer substrate 10, and therefore descriptions are omitted. The multilayer substrate 10i performs the same functions as the multilayer substrate 10.

[0171] (Example 10)

[0172] Hereinafter, the multilayer substrate 10j involved in the 10th modified example will be described with reference to the accompanying drawings. Figure 14 This is a cross-sectional view of the multilayer substrate 10j.

[0173] The multilayer substrate 10j differs from the multilayer substrate 10 in that it has a through-hole h0 in the insulating layer 16d. The through-hole h0 extends through the insulating layer 16d along its vertical axis. When viewed downwards, the through-hole h0 overlaps with the signal conductor layer 20. By providing such a through-hole h0, damage to the first through-hole h1a and the second through-hole h1b can be suppressed when the insulating layers 16a to 16d are pressed together. Furthermore, the capacitance between the signal conductor layer 20 and the second ground conductor layer 24 can be reduced through the through-hole h0. This allows the characteristic impedance to be kept constant. The other structures of the multilayer substrate 10j are the same as those of the multilayer substrate 10, and therefore descriptions are omitted. The multilayer substrate 10j achieves the same functional effects as the multilayer substrate 10.

[0174] (Example 11)

[0175] Hereinafter, the multilayer substrate 10k involved in the 11th modification will be described with reference to the accompanying drawings. Figure 15 This is a cross-sectional view near the first interlayer interconnect conductor v3a of the multilayer substrate 10k.

[0176] The multilayer substrate 10k differs from the multilayer substrate 10 in that the first conductor layer 22a, corresponding to the first ground conductor layer 22, and the second conductor layer 25a, corresponding to the third ground conductor layer 25, are smaller. More specifically, when viewed in the downward direction (negative Z-axis direction), the area of ​​the first conductor layer 22a is smaller than the area of ​​the upper end (positive Z-axis end) of the first through-hole h3a. Furthermore, when viewed in the downward direction (negative Z-axis direction), the area of ​​the second conductor layer 25a is smaller than the area of ​​the lower end (negative Z-axis end) of the second through-hole h3b. As a result, the interlayer connecting conductor v3a becomes thinner, thus increasing the space around the interlayer connecting conductor v3a. Furthermore, by reducing the size of the first conductor layer 22a and the second conductor layer 25a, the capacitance with the surrounding conductors can be reduced. The other structures of the multilayer substrate 10k are the same as those of the multilayer substrate 10, and therefore descriptions are omitted. The multilayer substrate 10k achieves the same functional effects as the multilayer substrate 10.

[0177] (12th variation)

[0178] Hereinafter, the multilayer substrate 10l according to the 12th modified example will be described with reference to the accompanying drawings. Figure 16 This is a cross-sectional view near the first interlayer interconnect conductor v3a of the multilayer substrate 10l.

[0179] The multilayer substrate 10l differs from the multilayer substrate 10 in the shape of the interlayer connecting conductor v3a. More specifically, the interlayer connecting conductor v3a has a tapered shape that tapers downwards. According to this construction, since the narrowed portion is where it contacts the second conductor layer 25a (and since the overall thickness of the interlayer connecting conductor v3a is greater than the thickness of the interlayer connecting conductor v3a at the point where it contacts the second conductor layer 25a), the rigidity of the interlayer connecting conductor v3a is increased. Therefore, the interlayer connecting conductor v3a is less prone to breakage. The other construction of the multilayer substrate 10l is the same as that of the multilayer substrate 10, and therefore descriptions are omitted. The multilayer substrate 10l achieves the same functional effects as the multilayer substrate 10. Furthermore, in Figure 16 In the example shown, the solder is only in contact with the surface of the second conductor layer 25a, but it can also be in contact with its sides. This configuration can improve the bonding strength between the interlayer connecting conductor v3a and the second conductor layer 25a.

[0180] (Example 13)

[0181] Hereinafter, the multilayer substrate 10m involved in the 13th modified example will be described with reference to the accompanying drawings. Figure 17 This is a cross-sectional view near the interlayer conductor v3a of the first layer of the multilayer substrate 10m.

[0182] The multilayer substrate 10m differs from the multilayer substrate 10 in the shape of the second through-hole h3b. More specifically, the second through-hole h3b extends to the insulating layer 16d. Therefore, capacitance is less likely to form between the interlayer connecting conductor v3a and the surrounding conductors. The other structures of the multilayer substrate 10m are the same as those of the multilayer substrate 10, and therefore descriptions are omitted. The multilayer substrate 10m performs the same functions as the multilayer substrate 10.

[0183] (Example 14)

[0184] Hereinafter, the multilayer substrate 10n involved in the 14th modified example will be described with reference to the accompanying drawings. Figure 18 This is a cross-sectional view near the first interlayer interconnect conductor v3a of the multilayer substrate 10n.

[0185] The multilayer substrate 10n differs from the multilayer substrate 10 in the shape of the interlayer connecting conductor v3a. More specifically, in the multilayer substrate 10n, the lower end of the interlayer connecting conductor v3a is connected to the outer edge E of the lower end of the second through-hole h3b. Thus, the interlayer connecting conductor v3a is firmly connected to the second conductor layer 25a. The other structures of the multilayer substrate 10n are the same as those of the multilayer substrate 10, and therefore descriptions are omitted. The multilayer substrate 10n performs the same functions as the multilayer substrate 10.

[0186] (Example 15)

[0187] Hereinafter, the multilayer substrate 10o involved in the 15th modified example will be described with reference to the accompanying drawings. Figure 19 This is a cross-sectional view of a multilayer substrate 10°.

[0188] The multilayer substrate 10o differs from the multilayer substrate 10 in that it also includes a signal conductor layer 20a and interlayer connecting conductors V1, V3a-V3c, V4a-V4c, and the laminate 12 also includes insulating layers 16e-16g (third insulating layers). More specifically, the insulating layers 16e-16g are stacked sequentially from top to bottom between insulating layers 16b and 16c.

[0189] Interlayer connecting conductors V1, V3a, and V4a extend along the vertical axis (Z-axis) through insulating layer 16e (the third insulating layer). Interlayer connecting conductors V3b and V4b extend along the vertical axis (Z-axis) through insulating layer 16f (the third insulating layer). Interlayer connecting conductors V3c and V4c extend along the vertical axis (Z-axis) through insulating layer 16g (the third insulating layer). There is no space between the interlayer connecting conductors V1, V3a-V3c, V4a-V4c and insulating layers 16e-16g (the third insulating layer).

[0190] Interlayer connecting conductors V3a to V3c electrically connect interlayer connecting conductors v3a and v3b of the first layer. Interlayer connecting conductors V4a to V4c electrically connect interlayer connecting conductors v4a and v4b of the first layer. Interlayer connecting conductor V1 electrically connects signal conductor layer 20 and signal conductor layer 20a.

[0191] Here, the laminate 12 has an upper main surface (positive main surface) and a lower main surface (negative main surface). Furthermore, the distance from the insulating layer 16a (first insulating layer) to the upper main surface (positive main surface) of the laminate 12 is shorter than the distance from the insulating layers 16e-16c (third insulating layers) to the upper main surface (positive main surface) of the laminate 12. Therefore, in the multilayer substrate 10o, both increased wiring density and increased strength of the multilayer substrate 10 can be achieved. The other structures of the multilayer substrate 10o are the same as those of the multilayer substrate 10, and therefore descriptions are omitted. The multilayer substrate 10o performs the same functions as the multilayer substrate 10.

[0192] (Example 16)

[0193] Hereinafter, the multilayer substrate 10p involved in the 16th modified example will be described with reference to the accompanying drawings. Figure 20 This is a cross-sectional view of a 10p multilayer substrate.

[0194] The multilayer substrate 10p differs from the multilayer substrate 10 in the following aspects.

[0195] • The laminate 12 also includes insulating layers 16e to 16k.

[0196] The multilayer substrate 10p also includes a radiating conductor layer 50, ground conductor layers 120, 122, 124, and interlayer connecting conductors V11a to V11e, V13a to V13c, and V14a to V14e.

[0197] Insulator layers 16a to 16k are stacked in a top-to-bottom arrangement. Interlayer connecting conductors V11a to V11e penetrate insulator layers 16b to 16d, 16g, and 16h along the vertical axis. Interlayer connecting conductors V13a to V13c penetrate insulator layers 16b to 16d along the vertical axis. Interlayer connecting conductors V14a to V14e penetrate insulator layers 16b to 16d, 16g, and 16h along the vertical axis. There is no space between the interlayer connecting conductors V11a to V11e, V13a to V13c, and V14a to V14e and the insulator layers 16b to 16d, 16g, and 16h (the third insulating layer).

[0198] Interlayer connecting conductors V11a to V11c electrically connect the radiation conductor layer 50 and the interlayer connecting conductor v1b of the first layer. Interlayer connecting conductors V11d and V11e electrically connect the interlayer connecting conductor v1b of the first layer and the signal conductor layer 20.

[0199] Interconnecting conductors V13a to V13c of the second layer electrically connect the grounding conductor layer 120 and the interconnecting conductor v3b of the first layer. Interconnecting conductors V14a to V14c of the second layer electrically connect the grounding conductor layer 120 and the interconnecting conductor v4b of the first layer. Interconnecting conductors V14d and V14e of the second layer electrically connect the interconnecting conductor v4b of the first layer and the grounding conductor layer 124.

[0200] Here, the multilayer substrate 10p has a first line section A11 and a second line section A12 arranged along a front-rear axis (X-axis) orthogonal to the vertical axis (Z-axis). An insulating layer 16f (the first insulating layer) is located in the first line section A11 and the second line section A12. On the other hand, insulating layers 16a and insulating layers 16b to 16d (the third insulating layers) are located in the first line section A11 but not in the second line section A12. Therefore, the thickness of the first line section A11 along the vertical axis (Z-axis) is greater than the thickness of the second line section A12 along the vertical axis (Z-axis). Stress tends to concentrate at the boundary between the first line section A11 and the second line section A12. In particular, stress tends to concentrate in the insulating layer 16f. Therefore, the insulating layer 16f (the first insulating layer) is located in the first line section A11 and the second line section A12. As a result, the spaces Sp0, Sp2, and Sp4 deform, thus suppressing the application of forces to the first-layer interlayer connecting conductors v1b, v3b, and v4b. Consequently, in the multilayer substrate 10p, the strength of the multilayer substrate 10p can be increased while ensuring the thickness along the upper and lower axes. The other structures of the multilayer substrate 10p are the same as those of the multilayer substrate 10, and therefore descriptions are omitted. The multilayer substrate 10p achieves the same functional effect as the multilayer substrate 10.

[0201] (Electronic devices)

[0202] The structure of electronic device 1 will now be described with reference to the accompanying drawings. Figure 21 This is a cross-sectional view of an electronic device 1 having a multilayer substrate 10.

[0203] Electronic device 1 includes a multilayer substrate 10 and a housing 100. The housing 100 houses the multilayer substrate 10. Electronic device 1 is a wireless communication terminal such as a smartphone. In addition, the multilayer substrate 10 is bent.

[0204] (Other implementation methods)

[0205] The multilayer substrates involved in this utility model are not limited to multilayer substrates 10, 10a to 10p, and can be modified within the scope of its intent. In addition, the structures of multilayer substrates 10, 10a to 10p can be arbitrarily combined.

[0206] In addition, at least one of the materials of insulating layer 16a (first insulating layer) and insulating layer 16b (second insulating layer) may be a liquid crystal polymer, polyimide, perfluoroalkoxyalkane or polytetrafluoroethylene.

[0207] In addition, in the 11th to 13th modifications, at least one of the following conditions must be met: when viewed in the downward direction (negative direction of the Z-axis), the area of ​​the first conductor layer 22a is less than the area of ​​the upper end (positive side of the Z-axis) of the first through hole h3a; or when viewed in the downward direction (negative direction of the Z-axis), the area of ​​the second conductor layer 25a is less than the area of ​​the lower end (negative side of the Z-axis) of the second through hole h3b.

[0208] Furthermore, the first grounding conductor layer 22 may be located on the upper main surface of the insulating layer 16a, or it may be located above the upper main surface of the insulating layer 16a. That is, the first grounding conductor layer 22 may not be connected to the upper main surface of the insulating layer 16a.

[0209] Furthermore, the third grounding conductor layer 25 may be located on the lower main surface of the insulating layer 16b, or it may be located below the lower main surface of the insulating layer 16b. That is, the third grounding conductor layer 25 may not be connected to the lower main surface of the insulating layer 16b.

[0210] Alternatively, space Sp1 may exist between the inner circumferential surface of the second through hole h3b and the central CP on the upper and lower axes (Z-axis) of the first interlayer connecting conductor v3a.

[0211] Furthermore, the melting point of the material of the first-layer interconnect conductors v1 to v4 can be higher than the melting point of the solder used for mounting electronic components. Therefore, the first-layer interconnect conductors v1 to v4 do not melt during the mounting of electronic components. This suppresses deformation of the first-layer interconnect conductors v1 to v4. Consequently, variations in the electrical properties of the multilayer substrate 10 can be suppressed.

[0212] In addition, Figure 4 Alternatively, after the insulating layers 16b and 16c are crimped, the insulating layers 16a to 16d can be crimped.

[0213] Furthermore, the thickness of the upper and lower axes of the insulating layer 16a is less than the thickness of the upper and lower axes of the insulating layer 16b. However, the thickness of the upper and lower axes of the insulating layer 16a can also be equal to or greater than the thickness of the upper and lower axes of the insulating layer 16b.

[0214] Furthermore, the thickness of the upper and lower axes of the insulating layer 16d is less than the thickness of the upper and lower axes of the insulating layer 16c. However, the thickness of the upper and lower axes of the insulating layer 16d can also be equal to or greater than the thickness of the upper and lower axes of the insulating layer 16c.

[0215] Furthermore, the size relationship between the through holes formed in the insulating layer 16a and the insulating layer 16b can also be reversed.

[0216] Alternatively, an adhesive layer may be provided between the insulating layer 16b and the insulating layer 16c.

[0217] Alternatively, when viewed from below, a portion of the interlayer connecting conductor v3a and a portion of the interlayer connecting conductor v4a may overlap. Alternatively, when viewed from below, the interlayer connecting conductor v3a and the interlayer connecting conductor v4a may not overlap.

[0218] Furthermore, air bubbles can be present inside the interlayer conductors v1 to v4. This allows for the lightweighting of the multilayer substrates 10, 10a to 10p.

[0219] In addition, the materials of protective layers 18a and 18b can be the same as those of insulating layers 16a to 16f.

[0220] This utility model has the following structure. (1)

[0222] A multilayer substrate,

[0223] The multilayer substrate comprises a laminate, a first conductor layer, a second conductor layer, and an interlayer interconnection conductor.

[0224] The laminate has a structure in which multiple insulating layers, including a first insulating layer and a second insulating layer, are stacked along the Z-axis.

[0225] The first insulating layer and the second insulating layer each have a positive principal surface and a negative principal surface, respectively.

[0226] The positive principal surface of the second insulating layer is in contact with the negative principal surface of the first insulating layer.

[0227] The first conductor layer is located on the positive side of the Z-axis compared to the first insulator layer.

[0228] The second conductor layer is located on the negative side of the Z-axis compared to the second insulator layer.

[0229] A first through hole is provided in the first insulating layer, extending through the first insulating layer along the Z-axis.

[0230] A second through hole is provided in the second insulating layer, extending through the second insulating layer along the Z-axis.

[0231] When viewed from a downward direction, the second through hole overlaps with the first through hole.

[0232] When viewed in the positive direction of the Z-axis, the area of ​​the end of the second through hole on the positive side of the Z-axis is greater than the area of ​​the end of the first through hole on the negative side of the Z-axis.

[0233] The first interlayer connecting conductor extends along the Z-axis within the first through-hole and the second through-hole, and electrically connects the first conductor layer and the second conductor layer.

[0234] There is a space between the boundary of the first insulating layer and the second insulating layer and the inter-layer connecting conductor. (2)

[0236] According to the multilayer substrate described in (1), wherein,

[0237] The space faces at least a portion of the inner circumferential surface of the first through hole and at least a portion of the inner circumferential surface of the second through hole. (3)

[0239] According to the multilayer substrate described in (1) or (2), wherein,

[0240] The space exists between the inner circumferential surface of the first through hole or the inner circumferential surface of the second through hole and the center of the Z-axis of the first interlayer connecting conductor. (4)

[0242] According to any one of (1) to (3) the multilayer substrate, wherein,

[0243] When viewed in the positive direction of the Z-axis, the negative end of the first through hole on the Z-axis is recessed into the positive end of the second through hole on the Z-axis. (5)

[0245] According to any one of (1) to (4) the multilayer substrate, wherein,

[0246] The first through hole has a tapered shape that tapers towards the positive direction of the Z-axis.

[0247] The second through hole has a tapered shape that tapers as it moves toward the negative direction of the Z-axis. (6)

[0249] According to any one of (1) to (5) the multilayer substrate, wherein,

[0250] The first interlayer connecting conductor has a middle portion between the end located on the positive side of the Z-axis and the end located on the negative side of the Z-axis of the first interlayer connecting conductor.

[0251] The first interlayer connecting conductor has a first section and a second section, the first section having a tapered shape that tapers as it approaches the middle portion from the positive end of the Z-axis, and the second section having a tapered shape that tapers as it approaches the middle portion from the negative end of the Z-axis. (7)

[0253] According to the multilayer substrate described in (6), wherein,

[0254] When viewed in the negative direction of the Z-axis, at least a portion of the side surface of the first interlayer connecting conductor in the first interval, at least a portion of the side surface of the first interlayer connecting conductor in the second interval, and at least a portion of the space overlap with each other. (8)

[0256] According to any one of (1) to (7) the multilayer substrate, wherein,

[0257] When viewed in the negative direction of the Z-axis, the area of ​​the first conductor layer is smaller than the area of ​​the end of the first through hole on the positive side of the Z-axis; or, when viewed in the negative direction of the Z-axis, the area of ​​the second conductor layer is smaller than the area of ​​the end of the second through hole on the negative side of the Z-axis. (9)

[0259] According to any one of (1) to (8), the multilayer substrate, wherein,

[0260] The material of the first interlayer connecting conductor is an alloy containing Sn. (10)

[0262] According to any one of (1) to (9), the multilayer substrate, wherein,

[0263] The melting point of the material of the first interlayer connecting conductor is below the melting point of the solder used for mounting electronic components. (11)

[0265] According to any one of (1) to (10) the multilayer substrate, wherein,

[0266] The materials of the first insulating layer and the second insulating layer are flexible resins. (12)

[0268] According to any one of (1) to (11), the multilayer substrate, wherein,

[0269] The material of the first insulating layer is different from the material of the second insulating layer. (13)

[0271] According to any one of (1) to (12), the multilayer substrate, wherein,

[0272] At least one of the materials of the first insulating layer and the second insulating layer is a liquid crystal polymer, polyimide, perfluoroalkoxyalkane, or polytetrafluoroethylene. (14)

[0274] According to any one of (1) to (13) the multilayer substrate, wherein,

[0275] The first insulating layer and the second insulating layer are fused together. (15)

[0277] According to any one of (1) to (13) the multilayer substrate, wherein,

[0278] The laminate also includes a third insulating layer.

[0279] The third insulating layer has a positive principal surface and a negative principal surface.

[0280] The negative principal surface of the third insulating layer is in contact with the positive principal surface of the first insulating layer.

[0281] The second insulating layer is an adhesive layer that bonds the first insulating layer and the third insulating layer together. (16)

[0283] According to any one of (1) to (15) the multilayer substrate, wherein,

[0284] A high-frequency signal with a frequency of 1 GHz or higher and 1 THz or lower is transmitted through the first conductor layer, the second conductor layer and the inter-layer connecting conductor, or a ground potential is connected to the first conductor layer, the second conductor layer and the inter-layer connecting conductor. (17)

[0286] According to any one of (1) to (16) the multilayer substrate, wherein,

[0287] The multilayer substrate also includes a second interlayer interconnect conductor.

[0288] The plurality of insulating layers further includes a third insulating layer.

[0289] The second interlayer connecting conductor extends through the third insulating layer along the Z-axis.

[0290] There is no space between the interlayer conductor in the second layer and the third insulating layer. (18)

[0292] According to the multilayer substrate described in (17), wherein,

[0293] The laminate has a positive principal plane and a negative principal plane.

[0294] The distance from the first insulating layer to the positive principal surface of the laminate is shorter than the distance from the third insulating layer to the positive principal surface of the laminate. (19)

[0296] According to the multilayer substrate described in (17), wherein,

[0297] The multilayer substrate has a first line interval and a second line interval arranged along an X-axis orthogonal to the Z-axis.

[0298] The first insulating layer and the second insulating layer are located in the first line interval and the second line interval, respectively.

[0299] The third insulating layer is located in the first line interval but not in the second line interval.

[0300] The thickness of the first line section on the Z-axis is greater than the thickness of the second line section on the Z-axis. (20)

[0302] An electronic device comprising a multilayer substrate as described in any one of (1) to (19). (twenty one)

[0304] A method for manufacturing a multilayer substrate, comprising:

[0305] Preparation process: Prepare a first insulating layer and a second insulating layer having a positive principal surface and a negative principal surface arranged along the Z-axis;

[0306] The first through-hole forming process forms a first through-hole that penetrates the first insulating layer along the Z-axis;

[0307] The second through-hole forming process forms a second through-hole that penetrates the second insulating layer along the Z-axis; and

[0308] In the first interlayer conductor formation process, the first insulating layer and the second insulating layer are stacked such that the negative principal surface of the first insulating layer and the positive principal surface of the second insulating layer are in contact, and an interlayer conductor extending along the Z-axis is formed within the first through-hole and the second through-hole.

[0309] When viewed in the positive direction of the Z-axis, the area of ​​the end of the second through hole on the positive side of the Z-axis is greater than the area of ​​the end of the first through hole on the negative side of the Z-axis.

[0310] There is a space between the boundary between the first insulating layer and the second insulating layer and the inter-layer connecting conductor.

[0311] The space faces at least a portion of the inner circumferential surface of the first through hole and at least a portion of the inner circumferential surface of the second through hole.

Claims

1. A multilayer substrate, characterized in that, The multilayer substrate comprises a laminate, a first conductor layer, a second conductor layer, and an interlayer interconnection conductor. The laminate has a structure in which multiple insulating layers, including a first insulating layer and a second insulating layer, are stacked along the Z-axis. The first conductor layer and the second conductor layer each have a positive principal plane and a negative principal plane, respectively. The first insulating layer and the second insulating layer each have a positive principal surface and a negative principal surface, respectively. The positive principal surface of the second insulating layer is in contact with the negative principal surface of the first insulating layer. The first conductor layer is located on the positive side of the Z-axis compared to the first insulator layer. The second conductor layer is located on the negative side of the Z-axis compared to the second insulator layer. There is no other conductor layer between the negative principal plane of the first conductor layer and the positive principal plane of the second conductor layer. A first through hole is provided in the first insulating layer, extending through the first insulating layer along the Z-axis. A second through hole is provided in the second insulating layer, extending through the second insulating layer along the Z-axis. When viewed from a downward direction, the second through hole overlaps with the first through hole. When viewed in the positive direction of the Z-axis, the area of ​​the end of the second through hole on the positive side of the Z-axis is greater than the area of ​​the end of the first through hole on the negative side of the Z-axis. The first interlayer connecting conductor extends along the Z-axis within the first through-hole and the second through-hole, and electrically connects the first conductor layer and the second conductor layer. There is a space between the boundary of the first insulating layer and the second insulating layer and the inter-layer connecting conductor.

2. The multilayer substrate according to claim 1, characterized in that, The space faces at least a portion of the inner circumferential surface of the first through hole and at least a portion of the inner circumferential surface of the second through hole.

3. The multilayer substrate according to claim 1 or claim 2, characterized in that, The space exists between the inner circumferential surface of the first through hole or the inner circumferential surface of the second through hole and the center of the Z-axis of the first interlayer connecting conductor.

4. The multilayer substrate according to claim 1 or claim 2, characterized in that, When viewed in the positive direction of the Z-axis, the negative end of the first through hole on the Z-axis is recessed into the positive end of the second through hole on the Z-axis.

5. The multilayer substrate according to claim 1 or claim 2, characterized in that, The first through hole has a tapered shape that tapers towards the positive direction of the Z-axis. The second through hole has a tapered shape that tapers as it moves toward the negative direction of the Z-axis.

6. The multilayer substrate according to claim 1 or claim 2, characterized in that, The first interlayer connecting conductor has a middle portion between the end located on the positive side of the Z-axis and the end located on the negative side of the Z-axis of the first interlayer connecting conductor. The first interlayer connecting conductor has a first section and a second section, the first section having a tapered shape that tapers as it approaches the middle portion from the positive end of the Z-axis, and the second section having a tapered shape that tapers as it approaches the middle portion from the negative end of the Z-axis.

7. The multilayer substrate according to claim 6, characterized in that, When viewed in the negative direction of the Z-axis, at least a portion of the side surface of the first interlayer connecting conductor in the first interval, at least a portion of the side surface of the first interlayer connecting conductor in the second interval, and at least a portion of the space overlap with each other.

8. The multilayer substrate according to claim 1 or claim 2, characterized in that, When viewed in the negative direction of the Z-axis, the area of ​​the first conductor layer is smaller than the area of ​​the end of the first through hole on the positive side of the Z-axis; or, when viewed in the negative direction of the Z-axis, the area of ​​the second conductor layer is smaller than the area of ​​the end of the second through hole on the negative side of the Z-axis.

9. The multilayer substrate according to claim 1 or claim 2, characterized in that, The material of the first interlayer connecting conductor is an alloy containing Sn.

10. The multilayer substrate according to claim 1 or claim 2, characterized in that, The melting point of the material of the first interlayer connecting conductor is below the melting point of the solder used for mounting electronic components.

11. The multilayer substrate according to claim 1 or claim 2, characterized in that, The materials of the first insulating layer and the second insulating layer are flexible resins.

12. The multilayer substrate according to claim 1 or claim 2, characterized in that, The material of the first insulating layer is different from the material of the second insulating layer.

13. The multilayer substrate according to claim 1 or claim 2, characterized in that, At least one of the materials of the first insulating layer and the second insulating layer is a liquid crystal polymer, polyimide, perfluoroalkoxyalkane, or polytetrafluoroethylene.

14. The multilayer substrate according to claim 1 or claim 2, characterized in that, The first insulating layer and the second insulating layer are fused together.

15. The multilayer substrate according to claim 1 or claim 2, characterized in that, The laminate also includes a third insulating layer. The third insulating layer has a positive principal surface and a negative principal surface. The negative principal surface of the third insulating layer is in contact with the positive principal surface of the first insulating layer. The first insulating layer is an adhesive layer that bonds the second insulating layer and the third insulating layer together.

16. The multilayer substrate according to claim 1 or claim 2, characterized in that, A high-frequency signal with a frequency of 1 GHz or higher and 1 THz or lower is transmitted through the first conductor layer, the second conductor layer and the inter-layer connecting conductor, or a ground potential is connected to the first conductor layer, the second conductor layer and the inter-layer connecting conductor.

17. The multilayer substrate according to claim 1 or claim 2, characterized in that, The multilayer substrate also includes a second interlayer interconnect conductor. The plurality of insulating layers further includes a third insulating layer. The second interlayer connecting conductor extends through the third insulating layer along the Z-axis. There is no space between the interlayer conductor in the second layer and the third insulating layer.

18. The multilayer substrate according to claim 17, characterized in that, The laminate has a positive principal plane and a negative principal plane. The distance from the first insulating layer to the positive principal surface of the laminate is shorter than the distance from the third insulating layer to the positive principal surface of the laminate.

19. The multilayer substrate according to claim 17, characterized in that, The multilayer substrate has a first line interval and a second line interval arranged along an X-axis orthogonal to the Z-axis. The first insulating layer is located in the first line interval and the second line interval. The third insulating layer is located in the first line interval but not in the second line interval. The thickness of the first line section on the Z-axis is greater than the thickness of the second line section on the Z-axis.

20. An electronic device, comprising: ， It has the multilayer substrate as described in claim 1 or claim 2.

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