A window wafer, infrared detector and thermal imaging device
By setting an anti-overflow layer on the sidewall of the support wall of the window wafer and providing a vertical climbing channel, the problem of eutectic solder overflow during the bonding process is solved, resulting in smaller chip size and higher detector yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- RUICHUANG MICROELECTRONICS (YANTAI) CO LTD
- Filing Date
- 2025-05-19
- Publication Date
- 2026-07-03
AI Technical Summary
During wafer-level packaging, eutectic solder is prone to horizontal overflow during bonding, affecting the detector's imaging performance and subsequent processes. Existing technologies are unable to effectively prevent overflow.
An anti-overflow layer is provided on the side wall of the support wall of the window wafer. The wettability of the anti-overflow layer surface to the solder layer is greater than that of the solder layer to the device wafer substrate, providing a vertical climbing channel so that excess solder can climb along the side wall of the wall and avoid horizontal overflow.
It effectively prevents overflow problems during eutectic bonding, reduces chip size, and improves detector yield.
Smart Images
Figure CN224460434U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of infrared detection technology, and in particular to a window wafer, an infrared detector, and a thermal imaging device. Background Technology
[0002] With the rapid development of integrated circuit and microelectromechanical systems (MEMS) technologies in recent years, uncooled infrared focal plane array detector technology has matured and has been widely used in military and civilian fields. Wafer-level packaging, due to its inherent advantages of high integration, miniaturization, and low cost, will gradually replace metal and ceramic packaging, becoming the mainstream packaging form for uncooled infrared detectors. In wafer-level packaging technology, the structural design of the window wafer corresponding to the detector wafer is a crucial factor affecting detector performance. In conventional window wafer designs, deep silicon etching is used to fabricate walls to ensure the distance between the window plane and the focal plane. A low-temperature, highly sealing, and particle-resistant eutectic solder is deposited on the wall ring to achieve bonding with the detector wafer, ensuring vacuum encapsulation.
[0003] However, because the eutectic solder is in a molten state during bonding, it is prone to horizontal overflow into the pixel area or dicing track under bonding pressure, forming large overflow balls. This affects the detector's imaging performance and subsequent processes such as dicing, testing, and wire bonding. Therefore, how to provide a window wafer that can prevent overflow is a problem that urgently needs to be solved by those skilled in the art. Utility Model Content
[0004] The purpose of this invention is to provide a windowed wafer that can prevent overflow during bonding; this invention also provides an infrared detector and a thermal imaging device that can prevent overflow during bonding.
[0005] To solve the above-mentioned technical problems, this utility model provides a window wafer, characterized in that it includes:
[0006] Base;
[0007] A supporting wall located on one side surface of the base, the supporting wall forming a cavity on one side of the base;
[0008] At least an anti-overflow layer located on the surface of the supporting wall facing the cavity;
[0009] A solder layer is located on the end face of the supporting wall, and the solder layer is in contact with the anti-overflow layer; the wettability of the surface of the anti-overflow layer with the solder layer is greater than the wettability of the solder layer with the device wafer substrate.
[0010] Optionally, the anti-overflow layer extends to the end face of the supporting wall, and the solder layer covers the anti-overflow layer extending to the end face of the supporting wall.
[0011] Optionally, the anti-overflow layer covers the end face of the supporting wall, and the solder layer covers the anti-overflow layer located on the end face of the supporting wall.
[0012] Optionally, the spill-proof layer extends from the end face of the supporting wall to the bottom where the supporting wall connects to the substrate.
[0013] Optionally, the anti-overflow layer is also disposed on the surface of the supporting wall on the side opposite to the cavity.
[0014] Optionally, the spill-proof layer is a spill-proof metal layer.
[0015] Optionally, the anti-overflow layer includes at least a wetting layer and an adhesion layer, wherein the wetting layer has a greater wettability with the solder layer than the solder layer has with the device wafer substrate, and the solder layer is in contact with the wetting layer;
[0016] The adhesive layer is located on the side of the impregnating layer facing the supporting wall, and the adhesive layer is used to fix the impregnating layer to the surface of the supporting wall.
[0017] Optionally, the anti-spill layer may further include a barrier layer located between the wetting layer and the adhesive layer.
[0018] Optionally, the material of the wetting layer is Au or Cu; and / or the material of the barrier layer is Ni or Pt; and / or the material of the adhesion layer is Cr, Ti, or TiW.
[0019] Optionally, the total thickness of the anti-spill layer is between 50 nm and 20 μm.
[0020] Optional, also includes:
[0021] An anti-reflection structure located in the anti-reflection region of the substrate surface, and / or a getter located in the blank region of the substrate surface.
[0022] This application also provides an infrared detector, including a device wafer and a window wafer as described in any of the preceding claims, the window wafer being bonded to the substrate of the device wafer via the solder layer.
[0023] This application also provides a thermal imaging device, including the infrared detector described above.
[0024] The present invention provides a window wafer comprising: a substrate; a support wall located on one side surface of the substrate, the support wall forming a cavity on one side of the substrate; an anti-overflow layer located at least on the side surface of the support wall facing the cavity; a solder layer located on the end face of the support wall, the solder layer being in contact with the anti-overflow layer; the wettability of the surface of the anti-overflow layer to the solder layer being greater than the wettability of the solder layer to the device wafer substrate.
[0025] By setting an anti-overflow layer on the sidewall of the support wall, since the wettability of the anti-overflow layer surface with the solder layer is greater than that of the solder layer with the device wafer substrate, the surface of the anti-overflow layer is equivalent to the solder climbing channel, providing a vertical climbing channel for the solder. Excess solder can climb along the sidewall of the support wall, thereby solving the overflow problem in the bonding pressure process of eutectic bonding technology. The anti-overflow design in the vertical direction of the window wafer replaces the horizontal anti-overflow structure on the device wafer, which is conducive to further reducing the chip size.
[0026] This utility model also provides an infrared detector and a thermal imaging device, which have the same beneficial effects as described above, and will not be described in detail here. Attached Figure Description
[0027] To more clearly illustrate the technical solutions of the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 This is a front view schematic diagram of a window wafer provided in an embodiment of the present utility model;
[0029] Figure 2 for Figure 1 A schematic diagram of the specific structure of region A in the middle;
[0030] Figure 3 for Figure 1 A top-view structural diagram;
[0031] Figures 4 to 10 This is a process flow diagram of the window wafer fabrication method provided in an embodiment of the present invention.
[0032] In the diagram: 1. Base, 2. Supporting wall, 3. Anti-reflective structure, 4. Anti-overflow layer, 5. Solder layer, 6. Getter. Detailed Implementation
[0033] The core of this invention is to provide a window wafer. In the prior art, because the eutectic solder is in a molten state during the bonding process, it is prone to horizontal overflow to the pixel area or dicing track under the action of bonding pressure, forming large overflow balls, which affect the imaging effect of the detector and subsequent processes such as dicing, testing, and wire bonding.
[0034] The present invention provides a window wafer comprising: a substrate; a support wall located on one side surface of the substrate, the support wall forming a cavity on one side of the substrate; an anti-overflow layer located at least on the side surface of the support wall facing the cavity; a solder layer located on the end face of the support wall, the solder layer being in contact with the anti-overflow layer; the wettability of the surface of the anti-overflow layer to the solder layer being greater than the wettability of the solder layer to the device wafer substrate.
[0035] By setting an anti-overflow layer on the sidewall of the support wall, since the wettability of the anti-overflow layer surface with the solder layer is greater than that of the solder layer with the device wafer substrate, the surface of the anti-overflow layer is equivalent to the solder climbing channel, providing a vertical climbing channel for the solder. Excess solder can climb along the sidewall of the support wall, thereby solving the overflow problem in the bonding pressure process of eutectic bonding technology. The anti-overflow design in the vertical direction of the window wafer replaces the horizontal anti-overflow structure on the device wafer, and is conducive to further reducing the chip size.
[0036] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0037] Example 1
[0038] Please refer to Figures 1 to 3 , Figure 1 This is a front view schematic diagram of a window wafer provided in an embodiment of the present utility model; Figure 2 for Figure 1 A schematic diagram of the specific structure of region A in the middle; Figure 3 for Figure 1 A top-view structural diagram.
[0039] See Figures 1 to 3 In this embodiment, the window wafer includes: a substrate 1; a support wall 2 located on one side surface of the substrate 1, the support wall 2 forming a cavity on one side of the substrate 1; an anti-overflow layer 4 located at least on the side surface of the support wall 2 facing the cavity; a solder layer 5 located on the end face of the support wall 2, the solder layer 5 contacting the anti-overflow layer 4; the wettability of the surface of the anti-overflow layer 4 with the solder layer 5 is greater than the wettability of the solder layer 5 with the device wafer substrate.
[0040] The aforementioned substrate 1 is the substrate of the window wafer. The material of substrate 1 can be Si, etc. The specific material of substrate 1 can be set according to the actual situation and is not specifically limited here. A support wall 2 is usually provided on one side surface of substrate 1. The support wall 2 can be a wall structure formed by etching one side of substrate 1, that is, the support wall 2 and substrate 1 can be an integral structure. The support wall 2 is usually distributed in a ring to form a cavity on one side of substrate 1. The bottom of the cavity is the aforementioned substrate 1, and the sidewall of the cavity is the aforementioned support wall 2. At this time, the support wall 2 has one end face and two sidewalls, wherein the sidewalls are divided into a sidewall facing the center of the cavity and a sidewall facing away from the center of the cavity, and the end face is the surface of the support wall 2 away from the end of substrate 1. In this embodiment, the height of the support wall 2 is usually between 30μm and 150μm, and the position of the support wall 2 should be opposite to the position of the bonding area on the device wafer.
[0041] In this embodiment, the anti-overflow layer 4 is located at least on the surface of the supporting wall 2 facing the cavity, while the solder layer 5 is located on the end face of the supporting wall 2. Specifically, the anti-overflow layer 4 serves as a vertical channel for solder to climb during eutectic bonding, which is typically the extension direction of the supporting wall 2. Therefore, in this embodiment, it is first necessary to ensure that the solder layer 5 is in contact with the anti-overflow layer 4, and secondly, it is necessary to ensure that the wettability between the surface of the anti-overflow layer 4 and the solder layer 5 is greater than the wettability between the solder layer 5 and the device wafer substrate. Only then can excess solder climb along the surface of the anti-overflow layer 4 during eutectic bonding, preventing solder overflow. The aforementioned anti-overflow layer 4 is typically an anti-overflow metal layer, meaning the material of the anti-overflow layer 4 is usually a metal material, to achieve a wettability between the surface of the anti-overflow layer 4 and the solder layer 5 greater than the wettability between the solder layer 5 and the device wafer substrate. The specific material of the anti-overflow layer 4 will be described in detail in the following embodiments and will not be repeated here.
[0042] The aforementioned device wafers are typically equipped with functional structures, such as pixel structures, and are mainly used to implement corresponding functions such as infrared detection. The specific structure of the device wafer can be set according to the actual situation and is not specifically limited here. In this embodiment, the solder layer 5 is typically used to bond the support wall 2 to the substrate of the device wafer. By selecting the material of the anti-overflow layer 4, the wettability between the surface of the anti-overflow layer 4 and the solder layer 5 can be made greater than the wettability between the solder layer 5 and the device wafer substrate. Wetting refers to the bonding ability between the solder and the corresponding material. In the eutectic bonding process, solder overflow refers to the solder detaching from the bond with the device wafer substrate and overflowing. In this embodiment, because the solder has a higher bonding ability with the surface of the anti-overflow layer 4, the overflowing solder will climb along the surface of the anti-overflow layer 4 and will not overflow.
[0043] This embodiment controls the positions of the anti-overflow layer 4 and the solder layer 5. For example, the anti-overflow layer 4 extends from the side wall of the supporting wall 2 to the end face of the supporting wall 2, and the solder layer 5 covers the anti-overflow layer 4 extending to the end face of the supporting wall 2. This ensures contact between the surface of the anti-overflow layer 4 and the solder layer 5, allowing the anti-overflow layer 4 to act as a channel for solder to climb and thus preventing solder overflow. Of course, other structures can also be used in this embodiment to make the anti-overflow layer 4 and the solder layer 5 contact each other; no specific limitation is made here.
[0044] Typically, in this embodiment, an anti-overflow layer 4 is provided to cover the end face of the supporting wall 2, and the solder layer 5 is provided to cover the anti-overflow layer 4 located on the end face of the supporting wall 2 to ensure sufficient contact between the solder layer 5 and the anti-overflow layer 4. Furthermore, in this embodiment, the aforementioned anti-overflow layer 4 is typically provided on both opposite sidewalls of the supporting wall 2, that is, the anti-overflow layer 4 is also provided on the surface of the supporting wall 2 facing away from the cavity. Simultaneously, the aforementioned anti-overflow layer 4 is provided on both the surface of the supporting wall 2 facing the cavity and the surface facing away from the cavity to prevent solder from overflowing in any direction during eutectic bonding.
[0045] Furthermore, in this embodiment, the anti-overflow layer 4 is typically provided to extend from the end face of the supporting wall 2 to the bottom where the supporting wall 2 connects to the substrate 1. The vertical length of the anti-overflow layer 4 is typically the length of the solder climb channel. To minimize solder overflow, in this embodiment, the vertical length of the anti-overflow layer 4 can be maximized. Specifically, the anti-overflow layer 4 can be provided to extend from the end face of the supporting wall 2 to the bottom where the supporting wall 2 connects to the substrate 1, ensuring that the solder has a sufficiently long climb space.
[0046] This embodiment discloses a window wafer. By setting an anti-overflow layer 4 on the side wall of the support wall 2, since the wettability of the surface of the anti-overflow layer 4 with the solder layer 5 is greater than the wettability of the solder layer 5 with the device wafer substrate, the surface of the anti-overflow layer 4 is equivalent to the solder climbing channel, providing a vertical climbing channel for the solder. Excess solder can climb along the side wall of the support wall 2, thereby solving the overflow problem in the bonding pressure process of eutectic bonding technology. The anti-overflow design in the vertical direction of the window wafer replaces the horizontal anti-overflow structure on the device wafer, and is conducive to further reducing the chip size.
[0047] The specific structure of the window wafer provided by this utility model will be described in detail in the following embodiments.
[0048] Example 2
[0049] In this embodiment, the anti-overflow layer 4 includes at least a wetting layer and an adhesive layer. The wetting layer has a greater wettability with the solder layer 5 than the solder layer 5 has a greater wettability with the device wafer substrate. The solder layer 5 is in contact with the wetting layer. The adhesive layer is located on the side of the wetting layer facing the support wall 2. The adhesive layer is used to fix the wetting layer to the surface of the support wall 2.
[0050] The wettability of the aforementioned wetting layer to the solder layer 5 is greater than that to the solder layer 5 to the device wafer substrate, thus allowing the wetting layer to serve as a channel for solder creep and also providing oxidation resistance. The material of this wetting layer can be Au or Cu, or other metals, as long as it achieves the aforementioned effects; no specific limitation is made here. Typically, this wetting layer can also be used as an adhesion structure for the solder layer 5 to ensure the connection between the solder layer 5 and the wetting layer.
[0051] The aforementioned adhesive layer is mainly used to fix the impregnation layer to the surface of the supporting wall 2, that is, to ensure that the impregnation layer can be firmly adhered to the surface of the supporting wall 2. The material of the aforementioned adhesive layer can be Cr, Ti, or TiW, or other metal materials, as long as it can achieve the above-mentioned effect, and no specific limitation is made here.
[0052] Specifically, in this embodiment, the anti-overflow layer 4 typically also includes a barrier layer located between the wetting layer and the adhesive layer. This barrier layer primarily prevents the wetting layer or contaminating ions from diffusing into the adhesive layer or the supporting wall 2, thus affecting its performance. The barrier layer can be made of Ni or Pt, or other metals, as long as it achieves the aforementioned effect; no specific limitation is made here.
[0053] In this embodiment, the aforementioned anti-overflow layer 4 can specifically be composed of a stacked structure such as Cr / Ni / Au, Ti / Ni / Au, Ti / Pt / Au, Cr / Au, Ti / Cu, TiW / Cu, etc., wherein the material of the wetting layer is usually Au or Cu, and / or the material of the barrier layer is usually Ni or Pt, and / or the material of the adhesion layer is usually Cr, Ti or TiW. The total thickness of the aforementioned anti-overflow layer 4 is usually between 50nm and 20μm. The anti-overflow layer 4, including the wetting layer, barrier layer, adhesion layer, etc., can be deposited on the surface of the supporting wall 2 by evaporation coating or magnetron sputtering. The specific preparation process of the anti-overflow layer 4 can be set according to the actual situation and is not specifically limited here.
[0054] Specifically, this embodiment typically includes: an anti-reflection structure 3 located in the anti-reflection region on the surface of the substrate 1, and / or a getter 6 located in the blank region on the surface of the substrate 1. The aforementioned anti-reflection region is the area in the window wafer that needs to be anti-reflected to increase the amount of light entering the wafer, and the aforementioned anti-reflection structure 3 can be disposed on the surface of the anti-reflection region. Specifically, the anti-reflection structure 3 can be disposed on the surface of the substrate 1 facing the device wafer, in which case the anti-reflection structure 3 is located within the aforementioned cavity; the anti-reflection structure 3 can also be disposed on the surface of the substrate 1 facing away from the device wafer, in which case the anti-reflection structure 3 is located outside the aforementioned cavity; of course, the aforementioned anti-reflection structure 3 can also be disposed on both sides of the substrate 1 simultaneously.
[0055] The aforementioned antireflection structure 3 can be an antireflection coating prepared by processes such as PVD (Physical Vapor Deposition), typically composed of ZnS, Ge, or a composite of both, with a thickness usually ranging from 1 μm to 20 μm. Alternatively, the antireflection structure 3 can be a microstructure array prepared by etching processes, with the microstructures having shapes such as cylinders, cones, frustums, pyramids, etc., thereby forming a metasurface with antireflection function on the surface of the substrate 1. The array period can be a single-period structure or a composite-period structure. It should be noted that the antireflection structure 3 needs to be positioned opposite to the pixel structure on the device wafer, and the size of the antireflection structure 3 on the surface of the substrate 1 facing away from the device wafer should be larger than that on the surface facing the device wafer to ensure effective transmission of infrared light.
[0056] The aforementioned blank area refers to the region in substrate 1 located outside the antireflection area. The getter 6 is typically placed in the blank area to prevent it from obscuring the pixel structure. The getter 6 is mainly used to provide a vacuum environment within the cavity and remove residual gas. In this embodiment, the getter 6 can be prepared by evaporation coating or magnetron sputtering. The material of the getter 6 can be one or more of titanium, zirconium, vanadium, chromium, cobalt, iron, manganese, palladium, barium, and aluminum combined in a certain proportion. The thickness of the getter 6 is typically 1 μm to 4 μm.
[0057] In this embodiment, the solder layer 5 can be prepared by evaporation coating or magnetron sputtering, or by electroplating. The main components of the solder layer 5 are usually composed of one or more of Sn, Au, Ag, In, Cu, and Sb in a certain proportion. The thickness of the solder layer 5 can be selected from 3μm to 100μm, and the actual thickness depends on the packaging requirements.
[0058] The window wafer provided in this embodiment has a stacked anti-overflow layer 4 that can ensure that the anti-overflow layer 4 can make firm contact with the supporting wall 2 while having sufficient wettability.
[0059] Example 3
[0060] Please refer to Figures 4 to 10 , Figures 4 to 10 This is a process flow diagram of the window wafer fabrication method provided in an embodiment of the present invention.
[0061] Unlike the above embodiments, this embodiment provides two different window wafer fabrication methods based on the above embodiments. The specific structure of the window wafer has been described in detail in the above embodiments and will not be repeated here.
[0062] The first method for fabricating windowed wafers is as follows:
[0063] S11: Prepare a supporting wall on the inner surface of the substrate.
[0064] See Figure 4 The inner surface of the substrate 1 is specifically the surface of the substrate 1 facing the window wafer. In this step, the substrate 1 can be photolithographically etched to form a cavity in the exposed area after patterning, and the remaining annular portion protected by photoresist forms the support wall 2.
[0065] S12: Prepare an antireflection structure on the surface of the antireflection region of the substrate.
[0066] See Figure 5 In this step, photolithography can be performed on the surface of substrate 1 to expose the antireflection region for subsequent antireflection treatment. Specifically, the antireflection structure 3 can be fabricated on the surface of substrate 1 facing the device wafer and / or the surface facing away from the device wafer. It can be an antireflection film prepared by PVD or a microstructure array prepared by etching process, and no specific limitation is made here.
[0067] S13: Apply an anti-overflow coating to the end face and side wall of the supporting wall.
[0068] See Figure 6 In this step, photolithography can be performed on the end face and side wall of the supporting wall 2 to expose the corresponding positions. Then, an anti-overflow layer 4 can be selectively deposited at specific positions, namely the end face and side wall of the supporting wall 2, using evaporation deposition or magnetron sputtering. The specific structure of the anti-overflow layer 4 has been described in detail in the above embodiments and will not be repeated here.
[0069] S14: A solder layer is plated on the upper surface of the anti-overflow layer.
[0070] See Figure 7In this step, the surface of the anti-overflow layer 4 located on the end face of the supporting wall 2 can be exposed first by photolithography. Then, the solder layer 5 can be prepared by evaporation coating or magnetron sputtering. The specific material of the solder layer 5 has been described in detail in the above embodiments and will not be repeated here.
[0071] S15: Apply getter to the blank area on the inner surface of the substrate.
[0072] See Figure 8 In this step, the blank area on the surface of the substrate 1 facing the window wafer can be exposed first by photolithography, and then the getter 6 can be prepared by evaporation deposition or magnetron sputtering. The specific material of the getter 6 has been described in detail in the above embodiments and will not be repeated here.
[0073] The second method for fabricating windowed wafers is as follows:
[0074] S21: Prepare a supporting wall on the inner surface of the substrate.
[0075] S22: Prepare an antireflection structure on the surface of the antireflection region of the substrate.
[0076] S23: An anti-overflow layer is deposited on the inner surface of the window wafer.
[0077] See Figure 9 In this step, the anti-overflow layer 4 is not selectively deposited at specific locations, but rather the anti-overflow layer 4 is deposited on the entire inner surface of the window wafer, including the surface of the substrate 1 facing the device wafer, the end face of the support wall 2, and the side wall surface of the support wall 2. At this time, the anti-overflow layer 4 will cover the aforementioned anti-reflection structure 3.
[0078] S24: A solder layer is plated on the surface of the anti-overflow layer located on the end face of the supporting wall.
[0079] See Figure 10 In this step, the surface of the anti-overflow layer 4 located on the end face of the support wall 2 can be exposed first by photolithography, and then the solder layer 5 can be prepared by evaporation coating, magnetron sputtering or electroplating.
[0080] S25: Remove the overflow prevention layer outside the side wall of the supporting wall.
[0081] In this step, the entire anti-overflow layer 4, except for the sidewall of the supporting wall 2, can be exposed by photolithography, that is, the anti-overflow layer 4 on the surface of the substrate 1 facing the device wafer is exposed, and then the exposed anti-overflow layer 4 is removed by one or two wet etching processes.
[0082] S26: Apply getter to the blank area on the inner surface of the substrate.
[0083] The parts of the second preparation method that overlap with the first preparation method can be found in the specific content of the first preparation method, and will not be repeated here.
[0084] The two window wafer fabrication methods provided in this embodiment both involve setting an anti-overflow layer 4 on the side wall of the support wall 2. Since the wettability between the surface of the anti-overflow layer 4 and the solder layer 5 is greater than the wettability between the solder layer 5 and the device wafer substrate, the surface of the anti-overflow layer 4 is equivalent to a solder climbing channel, providing a vertical climbing channel for the solder. Excess solder can climb along the side wall of the support wall 2, thereby solving the overflow problem in the bonding pressure process of eutectic bonding technology.
[0085] Example 4
[0086] This embodiment also provides an infrared detector, which includes a window wafer and a device wafer provided in any of the above embodiments, wherein the window wafer is bonded to the substrate of the device wafer. The specific structure of the window wafer has been described in detail in the above embodiments and will not be repeated here. The specific structure of the device wafer, such as the specific details of its pixel structure, can be found in the prior art and will not be repeated here. Typically, in this embodiment, the surface of the anti-overflow layer 4 may have a climbing structure formed by overflowing solder climbing up the surface of the anti-overflow layer 4.
[0087] Since the infrared detector provided in this embodiment uses the window wafer provided in the above embodiment, the infrared detector will have a higher yield.
[0088] Example 5
[0089] This embodiment also provides a thermal imaging device, which includes the infrared detector provided in any of the above embodiments. The specific structure of the infrared detector has been described in detail in the above embodiments and will not be repeated here. For the specific details of the remaining structure of the thermal imaging device, please refer to the prior art, which will not be repeated here.
[0090] Since the thermal imaging device provided in this embodiment uses the infrared detector provided in the above embodiment, the thermal imaging device will have a higher yield rate.
[0091] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0092] The present invention provides a detailed description of a window wafer, an infrared detector, and a thermal imaging device. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of these embodiments are merely illustrative and are intended to aid in understanding the method and core concepts of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.
Claims
1. A window wafer, characterized by, include: Base (1); A supporting wall (2) located on one side surface of the base (1), the supporting wall (2) forming a cavity on one side of the base (1); At least an anti-overflow layer (4) on the surface of the supporting wall (2) facing the cavity; The solder layer (5) is located on the end face of the supporting wall (2), and the solder layer (5) is in contact with the anti-overflow layer (4); the wettability of the surface of the anti-overflow layer (4) to the solder layer (5) is greater than the wettability of the solder layer (5) to the device wafer substrate.
2. The window wafer of claim 1, wherein, The anti-overflow layer (4) extends to the end face of the supporting wall (2), and the solder layer (5) covers the anti-overflow layer (4) extending to the end face of the supporting wall (2).
3. The window wafer of claim 2, wherein, The anti-overflow layer (4) covers the end face of the supporting wall (2), and the solder layer (5) covers the anti-overflow layer (4) located on the end face of the supporting wall (2).
4. The window wafer of claim 2, wherein, The spill-proof layer (4) extends from the end face of the supporting wall (2) to the bottom where the supporting wall (2) connects with the base (1).
5. The window wafer of claim 1, wherein, The anti-overflow layer (4) is also provided on the surface of the supporting wall (2) on the side opposite to the cavity.
6. The window wafer according to claim 1, characterized in that, The spill-proof layer (4) is a spill-proof metal layer.
7. The window wafer of claim 1, wherein, The anti-overflow layer (4) includes at least a wetting layer and an adhesion layer. The wetting layer has a greater wettability with the solder layer (5) than the solder layer (5) has a greater wettability with the device wafer substrate. The solder layer (5) is in contact with the wetting layer. The adhesive layer is located on the side of the impregnating layer facing the supporting wall (2), and the adhesive layer is used to fix the impregnating layer to the surface of the supporting wall (2).
8. The window wafer of claim 7, wherein, The anti-overflow layer (4) also includes a barrier layer located between the impregnation layer and the adhesion layer.
9. The window wafer according to claim 7 or 8, characterized in that The material of the wetting layer is Au or Cu; and / or the material of the barrier layer is Ni or Pt; and / or the material of the adhesion layer is Cr, Ti, or TiW.
10. The window wafer of claim 1, wherein, The total thickness of the anti-overflow layer (4) is between 50 nm and 20 μm.
11. The window wafer of claim 1, wherein, Also includes: An anti-reflection structure (3) located in the anti-reflection region of the substrate (1) surface, and / or a getter (6) located in the blank region of the substrate (1) surface.
12. An infrared detector, characterized by It includes a device wafer and a window wafer as described in any one of claims 1 to 11, wherein the window wafer is bonded to the substrate of the device wafer through the solder layer (5).
13. A thermal imaging apparatus characterized by comprising: Including the infrared detector as described in claim 12.