LED integrated chip and display device
By using a common cathode structure and homogeneous metal bonding technology, the problem of N and P electrodes occupying space in the light-emitting body was solved, achieving high integration and stable electrical performance of LED micro-display devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- YUANXU SEMICONDUCTOR TECHNOLOGY (WUXI) CO LTD
- Filing Date
- 2025-06-25
- Publication Date
- 2026-07-03
AI Technical Summary
In existing LED microdisplays, the N and P electrodes occupy a large area of the light-emitting body, which limits the reduction of the light-emitting body size and affects the integration of LED microdisplay devices.
A common cathode structure design is adopted, in which the N electrode is electrically connected to the first N-type GaN layer of the light emitter through a connecting layer, and a pad layer and an insulating layer are set in the electrode region to keep the electrode surface flush. Combined with flip-chip interconnect technology and homogeneous metal bonding structure, a stable connection between the N electrode and the P electrode is achieved.
This effectively reduces the space occupied by the electrodes in the light emitter, improves the integration of the light emitter, and enhances electrical performance and production efficiency through optimized bonding processes.
Smart Images
Figure CN224460463U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of LED integrated chip technology, and in particular to an LED integrated chip and display device. Background Technology
[0002] LED microdisplays are small, high-resolution display devices based on light-emitting diode (LED) technology. They are typically used in near-eye displays (such as AR / VR), wearable devices, medical imaging, and other applications where size, brightness, and energy efficiency are extremely critical.
[0003] Currently, LED microdisplays mainly consist of LED integrated chips and driving units. The LED integrated chip includes several arrayed light emitters, and the driving unit is electrically connected to the light emitters to control the on or off of the light emitters. For example, the prior art provides a Micro LED microdisplay and its fabrication method (application number 202310475901.5). In this LED microdisplay device, N-electrodes and P-electrodes need to be made on each light emitter, and then the N-electrodes and P-electrodes are connected to the negative and positive pads of the driving unit. However, the N-electrodes and P-electrodes occupy a large area of the light emitters, which limits the further reduction of the size of the light emitters, thereby affecting the further improvement of the integration of LED microdisplay devices. Summary of the Invention
[0004] In view of the technical problem that the N-electrode and P-electrode in the prior art occupy a large area of the light-emitting element, which limits the further reduction of the size of the light-emitting element, this application provides an LED integrated chip, and the technical solution adopted is as follows:
[0005] An LED integrated chip, characterized in that the LED integrated chip comprises:
[0006] A substrate for supporting light emitters, each of which includes a first N-type GaN layer, a first light-emitting layer, and a first P-type GaN layer arranged sequentially, with the surface of the first N-type GaN layer being the light-emitting surface;
[0007] The light-emitting region is located in the middle of the substrate, and the array of light-emitting elements is distributed in the light-emitting region;
[0008] A plurality of P electrodes, wherein at least one P electrode is disposed in each of the light emitters, and the P electrode is electrically connected to the first P-type GaN layer;
[0009] The electrode region includes a plurality of N electrodes distributed in a lattice and a connecting layer. The N electrodes are electrically connected to the first N-type GaN layer in the light emitter through the connecting layer to form a common cathode structure.
[0010] Its further feature is that,
[0011] Each of the light emitters further includes a current spreading layer, a reflective layer, and an insulating layer. The current spreading layer, the reflective layer, and the insulating layer are distributed sequentially from bottom to top on the surface of the first P-type GaN layer. The bottom end of the P electrode penetrates through the insulating layer and is electrically connected to the first P-type GaN layer through the reflective layer and the current spreading layer.
[0012] Preferably, the electrode region further includes a padding layer disposed below the connecting layer. Each padding layer includes a second N-type GaN layer, a second light-emitting layer, and a second P-type GaN layer. The insulating layer extends from the light-emitting region to the electrode region. The connecting layer is located between the insulating layer and the padding layer. The bottom end of the N-electrode penetrates the insulating layer and is electrically connected to the second N-type GaN layer through the connecting layer. The first N-type GaN layer is connected to the second N-type GaN layer.
[0013] Preferably, the light-emitting area further includes a plurality of first padding layers, which are disposed between the P electrode and the insulating layer. The first padding layers and the padding layers are used to keep the surfaces of the P electrode and the N electrode flush.
[0014] Preferably, the thickness of the connecting layer is equal to that of the first padding layer.
[0015] Preferably, an isolation groove is provided between the light-emitting area and the electrode area, and the insulating layer is partially filled in the isolation groove.
[0016] Another objective of this application is to provide a display device comprising the aforementioned LED integrated chip and a driving unit, wherein the driving unit is used to control the operating state of the light-emitting element in the LED integrated chip, characterized in that the driving unit comprises a substrate, a positive electrode region distributed in the middle of the substrate, and a negative electrode region located on the outer periphery of the positive electrode region, the positive electrode region comprising a plurality of arrayed positive electrode pads, the negative electrode region comprising a plurality of arrayed negative electrode pads, and the driving unit and the LED integrated chip being interconnected via a flip-chip bonding structure: the positive electrode pads are correspondingly connected to the P electrode in the LED integrated chip, and the negative electrode pads are correspondingly connected to the N electrode in the LED integrated chip.
[0017] Its further feature is that,
[0018] The bonding structure includes protrusions and grooves. The surfaces where the P and N electrodes of the LED integrated chip are located are the first bonding surfaces, and the surfaces where the positive and negative pads of the driving unit are located are the second bonding surfaces. The first and second bonding surfaces are aligned and bonded through the bonding structure, that is, the protrusions and the grooves are bonded one-to-one. The P and N electrodes are the protrusions, and the positive and negative pads are the grooves, or the P and N electrodes are the grooves, and the positive and negative pads are the protrusions.
[0019] Preferably, the protrusions and grooves are made of copper.
[0020] Preferably, the cross-sectional shape of the protrusion is circular, square, triangular or cross-shaped, and the shape of the groove matches the shape of the protrusion. When bonded, the protrusion and the groove engage accordingly to form a tenon and mortise structure.
[0021] Preferably, the display device further includes a color filter, which includes a color conversion area that corresponds one-to-one with the light-emitting surface of the light-emitting body, and is used to convert the light emitted by the light-emitting body into at least three primary colors: red, green, and blue, which are respectively the red light region, the green light region, and the blue light region.
[0022] Preferably, the light emitted by the LED integrated chip is blue.
[0023] Preferably, the color filter further includes a contrast enhancement area, which is located in the gap between two adjacent color conversion areas and is used to enhance the display contrast.
[0024] Preferably, the contrast enhancement area is a black material layer or a gray material layer.
[0025] The above-mentioned solution of this utility model can achieve the following beneficial effects: The LED integrated chip of this application is provided with a light-emitting area and an electrode area. The electrode area is provided with an N electrode and a connection layer. The N electrode is connected in series through the connection layer and electrically connected to the first N-type GaN layer of the light-emitting body in the light-emitting area to form a common cathode structure. In this distribution structure, the N electrode does not occupy the space of the light-emitting body, which is conducive to further reduction of the size of the light-emitting body. Attached Figure Description
[0026] Figure 1 This is a cross-sectional view of the LED integrated chip in this application.
[0027] Figure 2 This is a cross-sectional structural diagram of the epitaxial layer formed during the LED integrated chip fabrication process of this application.
[0028] Figure 3This is a schematic cross-sectional view of the LED integrated chip fabrication process of this application after the light-emitting body and the padding layer are formed.
[0029] Figure 4 This is a schematic cross-sectional view of the LED integrated chip fabrication process of this application after the formation of the ITO current spreading layer and the DBR reflective layer.
[0030] Figure 5 This is a cross-sectional view of the structure after the interconnect layer is formed in the LED integrated chip fabrication process of this application.
[0031] Figure 6 This is a schematic cross-sectional view of the LED integrated chip fabrication process after the insulating layer is formed.
[0032] Figure 7 This is a schematic cross-sectional view of the structure after the first padding layer is formed in the LED integrated chip fabrication process of this application.
[0033] Figure 8 This is a schematic cross-sectional view of the structure after the first seed layer is formed in the LED integrated chip fabrication process of this application.
[0034] Figure 9 This is a schematic cross-sectional view of the LED integrated chip fabrication process after the first photoresist is coated.
[0035] Figure 10 This is a schematic cross-sectional view of the first photoresist after development in the LED integrated chip fabrication process of this application.
[0036] Figure 11 This is a schematic cross-sectional view of the LED integrated chip fabrication process of this application after the formation of P-electrodes and N-electrodes.
[0037] Figure 12 This is a schematic cross-sectional view of the LED integrated chip fabrication process of this application after removing excess first seed layer;
[0038] Figure 13 This is a cross-sectional view of the substrate surface after the second seed layer is electroplated in the fabrication process of the drive unit in this application.
[0039] Figure 14 This is a schematic cross-sectional view of the structure after the second photoresist is coated during the fabrication process of the driving unit in this application.
[0040] Figure 15 This is a schematic cross-sectional view of the second photoresist after development during the fabrication process of the driving unit in this application.
[0041] Figure 16 This is a schematic cross-sectional view of the structure after the positive electrode pad and negative electrode pad are formed in the fabrication process of the drive unit of this application.
[0042] Figure 17 This is a schematic cross-sectional view of the structure after removing the excess second seed layer in the fabrication process of the driving unit of this application.
[0043] Figure 18 This is a top view of the first bonding surface of the LED integrated chip in this application (including the substrate).
[0044] Figure 19 This is a top view of the second bonding surface of the driving unit in this application.
[0045] Figure 20 This is a cross-sectional view of the structure after the N electrode is bonded to the negative electrode pad and the P electrode is bonded to the positive electrode pad in this application.
[0046] Reference numerals: 1. Substrate; 1a. Light-emitting area; 1b. Electrode area; 2. Light-emitting body; 3. First pad layer; 4. Pad layer; 5. Color filter; 6. First seed layer; 7. First photoresist; 8. Second seed layer; 9. Substrate; 10. Second photoresist.
[0047] First N-type GaN layer 201, first light-emitting layer 202, first P-type GaN layer 203, P electrode 204, N electrode 205, connecting layer 206, current spreading layer 207, reflective layer 208, insulating layer 209;
[0048] Type I GaN material 2001, luminescent material 2002, Type II GaN material 2003;
[0049] Second N-type GaN layer 401, second light-emitting layer 402, second P-type GaN layer;
[0050] Positive electrode region 9a, negative electrode region 9b, positive electrode pad 901, negative electrode pad 902. Detailed Implementation
[0051] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.
[0052] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims and accompanying drawings of this utility model are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such processes, methods, products or devices.
[0053] An LED integrated chip, reference Figure 1 The LED integrated chip includes: a substrate 1, a light-emitting region 1a located in the center of the substrate 1, and an electrode region 1b located on the outer periphery of the light-emitting region. The light-emitting region 1a includes a plurality of arrayed light-emitting elements 2. Each light-emitting element 2 includes a first N-type GaN layer 201, a first light-emitting layer 202, and a first P-type GaN layer 203 arranged sequentially, with the surface of the first N-type GaN layer 201 serving as the light-emitting surface. Each light-emitting element 2 has at least one P-electrode 204, which is electrically connected to the P-type GaN layer 203. The electrode region 1b includes a plurality of arrayed N-electrodes 205 and a connecting layer 206. The connecting layer 206 connects the N-electrodes 205 in series and electrically connects the N-electrodes 205 to the N-type GaN layer 201 in the light-emitting element 2, forming a common cathode structure.
[0054] Each light emitter 2 further includes a current spreading layer 207, a reflective layer 208, and an insulating layer 209. The current spreading layer 207, reflective layer 208, and insulating layer 209 are distributed sequentially from bottom to top on the surface of the first P-type GaN layer 203. The bottom end of the P-electrode 204 penetrates the insulating layer 209 and is electrically connected to the first P-type GaN layer 203 through the reflective layer 208 and the current spreading layer 207. In this embodiment, the current spreading layer 207 is an ITO current spreading layer, the reflective layer 208 is a DBR reflective layer or a metal reflective layer, and the insulating layer 209 includes, but is not limited to, a SiO2 layer.
[0055] In the LED integrated chip structure design, the surfaces of the P electrode 204 and the N electrode 205 are kept flush to ensure a stable connection when the LED integrated chip and the driving unit are flip-chip interconnected. To achieve this purpose, this application provides a plurality of first padding layers 3 in the light-emitting area 1a and a plurality of second padding layers in the electrode area 1b. In this embodiment, the first padding layers 3 are made of conductive metal material and are disposed between the P electrode 204 and the corresponding insulating layer 209, and the second padding layers are disposed below the N electrode 205.
[0056] The specific structure of the second padding layer is as follows: Each second padding layer includes a padding layer 4 and a connecting layer 206. The structure of the padding layer 4 is consistent with the structure of the light emitter 2, including: a second N-type GaN layer 401, a second light-emitting layer 402, and a second P-type GaN layer 403. The insulating layer 209 extends from the light-emitting region 1a to the electrode region 1b. The connecting layer 206 is located between the insulating layer 209 and the padding layer 4. The bottom end of the N electrode 205 penetrates the insulating layer 209 and is electrically connected to the second N-type GaN layer 401 through the connecting layer 206. The first N-type GaN layer 201 and the second N-type GaN layer 401 are connected to form a continuous region. The setting of this continuous region facilitates the electrical connection between the N electrode and the first N-type GaN layer 201 in the light emitter 2, forming a common cathode structure.
[0057] The distance from the surface of P electrode 204 to substrate 1 is the sum of the height of P electrode 204, the height of light emitter 2, and the thickness of the first padding layer 3. Similarly, the distance from the surface of N electrode 205 to substrate 1 is the sum of the height of N electrode 205, the height of padding layer 4, and the thickness of connecting layer 206. The height of light emitter 2 is the same as the height of padding layer 4, and the thickness of connecting layer 206 is the same as the thickness of the first padding layer 3. The heights of P electrode and N electrode are the same, ensuring that the distance from the surface of P electrode 204 to substrate 1 is equal to the distance from the surface of N electrode 205 to substrate 1, thus guaranteeing that the surfaces of P electrode 204 and N electrode 205 remain flush. In this embodiment, padding layer 4 serves a supporting and elevating function but does not have a light-emitting effect. In practical applications, the surfaces of the positive electrode pad 901 and negative electrode pad 902 in the driving unit are usually flush. The surfaces of the P electrode 204 and N electrode 205 are also flush, which is beneficial for the P electrode 204 and N electrode 205 to be firmly bonded to the positive electrode pad 901 and negative electrode pad 902 in subsequent processes, thereby ensuring the stability of the electrical performance of the display device.
[0058] The following provides a method for fabricating the above-mentioned LED integrated chip, the method comprising: S1, providing a substrate 1; the substrate is preferably a sapphire substrate or a silicon substrate.
[0059] S2. Using metal-organic chemical vapor deposition (MOCVD), a type I GaN material 2001, a luminescent material 2002, and a type II GaN material 2003 are sequentially deposited on the front side of substrate 1 to form an epitaxial layer. (Ref) Figure 2 The first type of GaN material is an N-type GaN material, the second type of GaN material is a P-type GaN material, and the luminescent material is a quantum well material.
[0060] S3. The epitaxial layer is divided into a light-emitting region 1a and an electrode region 1b. The light-emitting region 1a is located in the middle of the epitaxial layer, and the electrode region 1b is located on the outer periphery of the light-emitting region 1a. An isolation groove is provided between the light-emitting region 1a and the electrode region 1b, which is beneficial to further realize the electrical isolation between the N electrode and the P electrode.
[0061] S4. Using photolithography etching, the epitaxial layer is etched to the interior of the N-type GaN material, forming several frustums. The frustum located in the light-emitting region 1a is the light emitter 2, and the frustum located in the electrode region 1b is the padding layer 4. (Reference) Figure 3 Each light emitter 2 includes a first N-type GaN layer 201, a first light-emitting layer 202, and a first P-type GaN layer 203, distributed sequentially from bottom to top. During the etching process, a portion of the N-type GaN material at the bottom of the light emitter 2 and a portion of the N-type GaN material at the bottom of the padding layer 4 are not etched, forming a continuous region, so that the N electrode 204 can be connected to the first N-type GaN layer 201 in the light emitter 2 through the connecting layer and the second N-type GaN layer 401.
[0062] S5. Using photolithography, deposition, and lift-off processes, a current spreading layer 207 and a reflective layer 208 are sequentially prepared on the surfaces of the light source 2 and the padding layer 4. Specifically, firstly, the third photoresist on the surfaces of the first P-type GaN layer 203 and the second P-type GaN layer 403 is exposed and developed; then, ITO conductive material is deposited on the surface of the third photoresist using electron gun evaporation or magnetron sputtering. The ITO conductive material and the P-type GaN material can form good ohmic contact and have high light transmittance; based on the developed pattern, the ITO conductive material is lifted to form the ITO current spreading layer.
[0063] Similarly, a reflective layer 208 is formed on the surface of the ITO current spreading layer using photolithography, deposition, and lift-off processes, as referenced. Figure 4 The reflective layer 208 is a DBR reflective layer or a metal reflective layer, which has the function of light reflection. The light emitted by the light source 2 is reflected by the reflective layer 208, and the light emission efficiency is further improved.
[0064] S6. To facilitate the electrical connection between the second N-type GaN layer 401 in the padding layer 4 and the subsequently fabricated N-electrode 205, this application fabricates a connecting layer 206 in the electrode region 1b where the padding layer 4 is located, see... Figure 5 The connecting layer 206 is a metal connecting layer, and the metal material includes, but is not limited to, Al, Ti, Au, Cu, Cr, Ni, or at least two of Al, Ti, Au, Cu, Cr, Ni are stacked sequentially from bottom to top.
[0065] The connection layer 206 is specifically fabricated as follows: A connection layer 206 is formed on the surface of the second P-type GaN layer 403 and the etched surface of the second N-type GaN layer 401 using photolithography, deposition, and lift-off processes. The connection layer 206 facilitates the connection between the second N-type GaN layer 401 and the N-electrode 205 in the padding layer 4. Furthermore, since the second N-type GaN layer 401 and the first N-type GaN layer 201 are continuous interconnected regions, the connection layer 206 can electrically connect the N-electrode to the first N-type GaN layer 201, forming a common cathode structure.
[0066] S7. Using chemical vapor deposition or atomic layer deposition, insulating material is deposited on the surface of the reflective layer 208 and the surface of the connecting layer 206 to form the insulating layer 209. (See below) Figure 6 .
[0067] S8. Using photolithography etching process, the insulating layer 209 is etched to form a first etching hole and a second etching hole above the light source 2 and above the padding layer 4. The bottom ends of the first etching hole and the second etching hole penetrate the insulating layer 209.
[0068] S9. Using photolithography and electroplating processes, a first pad layer 3 is formed inside and above the first etched hole, as shown in the reference. Figure 7 The first padding layer is made of conductive metal material, which facilitates the subsequent electrical connection between the P electrode 204 and the reflective layer 208. In addition, the thickness of the first padding layer 3 is the same as the thickness of the connecting layer 206, which has a certain padding effect, which helps to keep the surfaces of the P electrode and the N electrode flush, so that the P electrode and the N electrode can be stably connected to the corresponding positive and negative electrode pads during subsequent flip bonding.
[0069] S10. Using photolithography and electroplating processes, a P electrode 204 and an N electrode 205 are formed above the first and second etched holes. The bottom end of the P electrode 204 passes through the first etched hole and contacts the reflective layer 208. It is electrically connected to the first P-type GaN layer 203 in the light emitter 4 through the reflective layer 208 and the current spreading layer 207. The bottom end of the N electrode 205 passes through the second etched hole and contacts the connecting layer 206. It is electrically connected to the second N-type GaN layer 401 at the bottom of the padding layer 4 through the connecting layer 206.
[0070] The specific preparation steps for P electrode 204 and N electrode 205 include: S101, depositing a first seed layer 6 on the entire surface including the surface of the first pad layer 3 and the surface of the insulating layer 209 using magnetron sputtering or electron beam evaporation. (Refer to...) Figure 8 ;
[0071] S102, Coat the surface of the first seed layer 6 with the first photoresist 7, as reference Figure 9 ;
[0072] S103. Expose and develop the first photoresist 7 to form the first photoresist etching holes, referencing... Figure 10 This exposes the regions above the first seed layer corresponding to the first and second etched holes.
[0073] S104. Based on the developed pattern, an electroplating process is used to electroplat a metal material, copper, into the first photoresist etched hole to form P electrode 204 and N electrode 205. The middle of P electrode 204 and N electrode 205 is a groove, for reference. Figure 11 , Figure 18 ;
[0074] S105, Clean and remove residual first photoresist 7;
[0075] S106. Remove excess first seed layer 6 by wet etching or plasma etching. (Refer to...) Figure 12 .
[0076] Through the above steps S1~S10, an LED integrated chip is prepared. In this LED integrated chip, the N electrode 205 is located on the outer periphery of the light-emitting area and does not occupy the space of the light-emitting body, which is conducive to further reduction of the size of the light-emitting body. In this embodiment, the size of the light-emitting body is 1μm~50μm, and the distance between the two light-emitting bodies is less than or equal to 20μm, which significantly improves the integration of the LED integrated chip.
[0077] The above-mentioned LED integrated chip is applied to a display device, which includes the above-mentioned LED integrated chip, a driving unit, and a color filter. The specific structure of the LED integrated chip is as described above and will not be repeated here.
[0078] The driving unit is used to control the working state of the light-emitting element in the LED integrated chip. The driving unit includes a substrate 9, a positive electrode region 9a distributed in the middle of the substrate 9, a negative electrode region 9b located on the outer periphery of the positive electrode region 9a, and a driving IC (not shown in the figure) located on the back of the substrate 9. The positive electrode region 9a includes a plurality of arrayed positive electrode pads 901, and the negative electrode region 9b includes a plurality of arrayed negative electrode pads 902. In this embodiment, a driving circuit is provided in the substrate 9, and the driving IC is electrically connected to the positive electrode pads 901 of the positive electrode region and the negative electrode pads 902 of the negative electrode region through the driving circuit in the substrate 9.
[0079] The driving unit and the LED integrated chip are flip-chip interconnected through a bonding structure: the positive electrode pad 901 is connected to the P electrode 204 in the LED integrated chip, and the negative electrode pad 902 is connected to the N electrode 205 in the LED integrated chip.
[0080] Flip-chip bonding is a common process for fabricating display devices. It generally uses metal bonding. Currently, most common metal bonding is heterogeneous metal bonding, such as gold (Au) bonding with indium (In), or gold (Au) bonding with tin (Sn). The characteristics of the metals in this type of bonding structure are that one of the metals is a low-melting-point metal or a soft metal, which has a lower bonding temperature and bonding time, which is beneficial for bonding. However, it is prone to risks such as high-temperature thermal expansion and surface oxidation.
[0081] Currently, homogeneous bonding in metal bonding generally uses gold (Au) to gold (Au) bonding. Gold (Au) has a high melting point of 1064.43℃ and is hard. However, in order to achieve diffusion connection between gold (Au) metals in the bonding process, the commonly used bonding temperature is 320℃ and the bonding time is 30 minutes. This bonding temperature is relatively high, which may affect the performance of the driver chip. In addition, the bonding time is relatively long, which affects the improvement of production efficiency.
[0082] To address the risks of high-temperature thermal expansion and surface oxidation associated with heterogeneous metal bonding in existing technologies, and the technical problems of high bonding temperatures affecting chip performance and long bonding times affecting production efficiency when bonding homogeneous metals (gold to gold), this application proposes a homogeneous metal bonding structure. This bonding structure specifically includes protrusions and grooves. The surface containing the active area of the LED integrated chip is the first bonding surface, and the surfaces containing the positive electrode pad 901 and negative electrode pad 902 of the driving unit are the second bonding surfaces. The first and second bonding surfaces are aligned and bonded through the bonding structure, meaning the protrusions and grooves are bonded one-to-one. The P electrode 204 and N electrode 205 are protrusions, and the middle portion of the positive electrode pad 901 and negative electrode pad 902 is a groove; or, the middle portion of the P electrode 204 and N electrode 205 is a groove, and the positive electrode pad 901 and negative electrode pad 902 are protrusions. In this embodiment, the protrusions and grooves are made of the same material, copper. During bonding, the copper diffuses to form a stable bonding structure.
[0083] In this embodiment, the protrusion is nail-shaped. During bonding, the nail-shaped protrusion engages with the corresponding groove to form a tenon-and-mortise structure. The cross-sectional shape of the protrusion includes, but is not limited to, a circle, a square, a triangle, or a cross. For example, the middle part of the N electrode 205 and the P electrode 204 is a groove, and the positive electrode pad 901 and the negative electrode pad 902 are nail-shaped. The cross-sectional area of the protruding part of the nail-shaped protrusion is smaller than the cross-sectional area of the groove, which facilitates the alignment and installation of the protrusion and the groove. In addition, the protruding part of the nail-shaped protrusion has a certain height. During bonding, the end of the protruding part is easily deformed under the action of extrusion force, thereby filling the groove, ensuring that the N electrode 205 and the P electrode 204 are in full contact and diffuse with the corresponding positive electrode pad 901 and negative electrode pad 902, thereby ensuring stable electrical performance.
[0084] In the bonding structure of this application, the bonding metal used is copper. Compared with heterogeneous bonding metals such as gold (Au) and indium (In) bonding, or gold (Au) and tin (Sn) bonding, copper has a higher melting point of 1083.4℃, which reduces the risks of high-temperature thermal expansion and surface oxidation. Moreover, compared with homogeneous bonding metals such as gold (Au) and gold (Au), copper to copper bonding temperature is lower and bonding time is shorter, with a bonding temperature of 120℃ and a bonding time of 100s to 600s, which can reduce the impact of high temperature on chip performance and production efficiency.
[0085] The light emitted by the LED integrated chip is blue. To achieve color display of the display device, the substrate 1 is peeled off, and a color filter 5 is covered on the light-emitting surface of the LED integrated chip. The color filter 5 includes a color conversion area, which corresponds one-to-one with the light-emitting surface of the light emitter. It is used to convert the light emitted by the light emitter into at least three primary colors: red, green, and blue, which are the red light region, green light region, and blue light region, respectively. The light colors of the red light region, green light region, and blue light region are mixed to form the desired display color.
[0086] It should be noted that, in another embodiment, the light emitted by the LED integrated chip can be green. The color filter 5 converts the green light into at least three primary colors: red, green, and blue, representing the red light region, green light region, and blue light region, respectively. The light colors from the red light region, green light region, and blue light region are then mixed.
[0087] In addition, to improve the display contrast of the display device, the color filter 5 also includes a contrast enhancement area, which is located in the gap between two adjacent light color conversion areas. The material used in the contrast enhancement area is a black material layer or a gray material layer, including but not limited to Cr, Al, and Ti.
[0088] The following provides a method for preparing the above-mentioned display device. The specific steps of the method include: A1, providing an LED integrated chip, which is prepared by the above steps S1 to S10.
[0089] A2. A driving unit is provided, the driving unit including a substrate 9, the second bonding surface of the substrate 9 is divided into a positive electrode region 9a and a negative electrode region 9b, the positive electrode region 9a is located in the middle of the substrate 9, the negative electrode region 9b is located on the outer periphery of the positive electrode region 9a, and a driving circuit is arranged in the substrate 9; a positive electrode pad 901 and a negative electrode pad 902 are respectively prepared in the positive electrode region 9a and the negative electrode region 9b, specifically including:
[0090] A21. A second seed layer 8 is deposited on the front side of the substrate using magnetron sputtering or electron beam evaporation. (Refer to...) Figure 13 ;
[0091] A22. Coat the surface of the second seed layer 8 with the second photoresist 10, as referenced. Figure 14;
[0092] A23. Expose and develop the second photoresist 10 to form the second photoresist etching holes, refer to... Figure 15 ;
[0093] A24. Based on the developed pattern, an electroplating process is used to electroplat a metal material, copper, into the second photoresist etched hole to form the positive electrode pad 901 and the negative electrode pad 902. (Refer to...) Figure 16 , Figure 19 The positive electrode pad 901 and the negative electrode pad 902 are nail-shaped protrusions, and the shape of the protrusions matches the shape of the grooves.
[0094] A25. Clean and remove residual second photoresist 10;
[0095] A26. Remove excess second seed layer 8 by wet etching or plasma etching. (Refer to...) Figure 17 .
[0096] A3. The surface where the active area (i.e., P electrode 204 and N electrode 205) of the LED integrated chip is located is the first bonding surface. The surface where the positive electrode pad 901 and negative electrode pad 902 in the driving unit are located is the second bonding surface. The first bonding surface and the second bonding surface correspond to each other, that is, the protrusion and the groove correspond to each other.
[0097] A4. Align the protrusions with the grooves to form a mortise and tenon structure. (Refer to...) Figure 20 Using a bonding machine, based on this mortise and tenon structure, the alignment and bonding of the LED integrated chip and the driver unit are achieved. The mortise and tenon structure with corresponding protrusions and grooves improves the alignment accuracy and bonding strength during bonding. Through the bonding structure, vertical transmission of electrical signals between the LED integrated chip and the driver unit is achieved.
[0098] This application uses a copper electroplating process to form a tenon-and-mortise structure with Cu and Cu as the mat bonded together. During the bonding process, there is no oxide layer on the surface of the Cu metal on both sides, which helps the diffusion connection between the metal materials. In addition, Cu is a hard metal, and the difference in thermal expansion between Cu and Cu is small, which ensures the stability of electrical and mechanical properties after bonding.
[0099] It is understood that the above detailed description of this utility model is for illustrative purposes only and is not intended to limit the technical solutions described in the embodiments of this utility model. Those skilled in the art should understand that modifications or equivalent substitutions can still be made to this utility model to achieve the same technical effects; as long as the usage requirements are met, they are all within the protection scope of this utility model.
Claims
1. An LED integrated chip, characterized in that, LED integrated chips include: The substrate (1) is used to support the light emitter. Each light emitter (2) includes a first N-type GaN layer (201), a first light-emitting layer (202), and a first P-type GaN layer (203) arranged in sequence. The surface where the first N-type GaN layer (201) is located is the light-emitting surface. The light-emitting region (1a) is located in the middle of the substrate (1), and the light-emitting bodies (2) are arrayed in the light-emitting region (1a). A plurality of P electrodes (204), each of the light emitters (2) is provided with at least one of the P electrodes (204), and the P electrodes (204) are electrically connected to the first P-type GaN layer (203); Electrode region (1b) includes a plurality of N electrodes (205) distributed in a lattice and a connecting layer (206). The N electrodes (205) are electrically connected to the first N-type GaN layer (201) in the light emitter (2) through the connecting layer (206) to form a common cathode structure.
2. The LED integrated chip according to claim 1, characterized in that, Each of the light emitters (2) further includes a current spreading layer (207), a reflective layer (208), and an insulating layer (209). The current spreading layer (207), the reflective layer (208), and the insulating layer (209) are distributed sequentially from bottom to top on the surface of the first P-type GaN layer (203). The bottom end of the P electrode (204) penetrates the insulating layer (209) and is electrically connected to the first P-type GaN layer (203) through the reflective layer (208) and the current spreading layer (207).
3. The LED integrated chip according to claim 2, characterized in that, The electrode region (1b) further includes a padding layer (4), which is disposed below the connecting layer (206). Each padding layer (4) includes a second N-type GaN layer (401), a second light-emitting layer (402), and a second P-type GaN layer (403). The insulating layer (209) extends from the light-emitting region (1a) to the electrode region (1b). The connecting layer (206) is located between the insulating layer (209) and the padding layer (4). The bottom end of the N-electrode (205) penetrates the insulating layer (209) and is electrically connected to the second N-type GaN layer (401) through the connecting layer (206). The first N-type GaN layer (201) is connected to the second N-type GaN layer (401).
4. The LED integrated chip according to claim 3, characterized in that, The light-emitting area (1a) further includes a plurality of first padding layers (3), which are disposed between the P electrode (204) and the insulating layer (209). The first padding layers (3) and padding layers (4) are used to keep the surfaces of the P electrode (204) and the N electrode (205) flush.
5. The LED integrated chip according to claim 4, characterized in that, The connecting layer (206) has the same thickness as the first padding layer (3).
6. The LED integrated chip according to claim 5, characterized in that, An isolation groove is provided between the light-emitting area (1a) and the electrode area (1b), and a portion of the insulating layer (209) is filled in the isolation groove.
7. A display device comprising an LED integrated chip as described in claim 1 and a driving unit, wherein the driving unit is used to control the operating state of the light-emitting element in the LED integrated chip, characterized in that, The driving unit includes a substrate (9), a positive electrode region (9a) distributed in the middle of the substrate (9), and a negative electrode region (9b) located on the outer periphery of the positive electrode region (9a). The positive electrode region (9a) includes a plurality of arrayed positive electrode pads (901), and the negative electrode region (9b) includes a plurality of arrayed negative electrode pads (902). The driving unit and the LED integrated chip are interconnected by a bonding structure via flip-chip interconnection: the positive electrode pads (901) are correspondingly connected to the P electrode (204) in the LED integrated chip, and the negative electrode pads (902) are correspondingly connected to the N electrode (205) in the LED integrated chip.
8. The display device according to claim 7, characterized in that, The bonding structure includes protrusions and grooves. The surfaces where the P electrode (204) and N electrode (205) of the LED integrated chip are located are the first bonding surfaces, and the surfaces where the positive electrode pad (901) and negative electrode pad (902) of the driving unit are located are the second bonding surfaces. The first bonding surfaces and the second bonding surfaces are aligned and bonded through the bonding structure, that is, the protrusions and the grooves are bonded one-to-one. The P electrode (204) and N electrode (205) are the protrusions, and the positive electrode pad (901) and negative electrode pad (902) are the grooves, or the P electrode (204) and N electrode (205) are the grooves, and the positive electrode pad (901) and negative electrode pad (902) are the protrusions.
9. The display device according to claim 8, characterized in that, Both the protrusions and grooves are made of copper.
10. The display device according to claim 8 or 9, characterized in that, The cross-sectional shape of the protrusion is circular, square, triangular or cross-shaped, and the shape of the groove matches the shape of the protrusion. When bonded, the protrusion and the groove engage to form a mortise and tenon structure.