Low internal resistance high energy efficiency field effect transistor

Abstract

This application relates to the technical field of field-effect transistors (FETs), and more particularly to a low-resistance, high-efficiency FET, comprising a copper-based island, a semiconductor chip, a gate pin, a source pin, and a package. The semiconductor chip has a drain, a gate, and a source. Its drain is fixedly connected to the copper-based island by a solder paste sintering process. It also includes a first conductive sheet and multiple second conductive sheets. Multiple interconnected and uniformly arranged connection regions are pre-fabricated on the source metallization layer of the semiconductor chip. One end of each of the multiple second conductive sheets is connected to one of the multiple connection regions, and the other end of each is connected to the source pin. One end of the first conductive sheet is connected to the gate of the semiconductor chip, and the other end of each first conductive sheet is connected to the gate pin. This application achieves low internal resistance and high efficiency in the FET and reduces local overheating of the chip.

Description

Technical Field

[0001] This application relates to the technical field of field-effect transistors, and more specifically, to a low-resistance, high-efficiency field-effect transistor. Background Technology

[0002] Field-effect transistors (FETs), as a core power semiconductor device, are widely used in modern electronic devices such as switching power supplies, motor drives, and power converters due to their advantages such as fast switching speed and low drive power. With technological advancements, electronic devices are placing increasingly higher demands on the power density and energy efficiency of power devices. Therefore, reducing the on-resistance of devices and improving their energy conversion efficiency has become a key research direction for those skilled in the art.

[0003] Currently, the mainstream power MOSFET package structure typically includes: a copper-based island serving as the foundation for heat dissipation and electrical connection; a semiconductor chip flip-chip fixed to the copper-based island via solder paste sintering, with the drain of the chip electrically interconnected with the copper-based island; a gate pin and a source pin. The gate of the chip is connected to the gate pin via a single bonded copper wire; while, due to its source potential and the need to carry a large output current, the source of the chip is electrically connected to the source pin via multiple parallel bonded copper wires, thereby reducing the current carrying capacity of a single wire and thus lowering the on-resistance of the circuit.

[0004] However, because the source of a power MOSFET chip is typically designed as a large metallization layer covering most of the chip surface, this area is flat and lacks effective physical features as precise positioning reference points. During the soldering of multiple source bonding wires, operators or automated equipment find it difficult to accurately and consistently position the solder joints of each bonding wire using a vision system. This "referenceless" soldering process is highly random, easily leading to uneven distribution of the bonding wires on the chip's source surface. This uneven distribution manifests in two main ways: first, some bonding wires are too close together, potentially even overlapping, while other areas have excessively large gaps and are not effectively utilized; second, the contact points between the bonding wires and the chip cannot form an optimal geometric layout along the current flow path. Uneven distribution of bonding wires leads to a severe imbalance in the current distribution along the vast parallel conductive path from the chip source to the pins. Some densely packed bonding wires may overheat due to current congestion, while sparsely packed bonding wires fail to fully utilize their current-carrying capacity. This not only reduces the effective cross-sectional area of ​​the overall parallel conductive path, increasing the contact resistance and interconnection resistance of the source circuit, thus resulting in a persistently high overall on-resistance of the device; but also causes uneven current distribution to generate local hot spots inside the chip, exacerbating the performance degradation of the device at high temperatures and severely affecting its long-term reliability. High internal resistance means higher conduction losses, directly reducing the energy conversion efficiency of the device and even the entire power supply system. Utility Model Content

[0005] To address the issues of high internal resistance, high power consumption, and the tendency for localized hot spots in current mainstream field-effect transistors (FETs), this application provides a low-internal-resistance, high-efficiency FET.

[0006] A low-resistance, high-efficiency field-effect transistor includes a copper-based island, a semiconductor chip, a gate pin, a source pin, and a package. The semiconductor chip has a drain, a gate, and a source. The drain is fixedly connected to the copper-based island by a solder paste sintering process. The transistor also includes a first conductive sheet and multiple second conductive sheets. Multiple spaced and uniformly arranged connection regions are pre-formed on the source metallization layer of the semiconductor chip. One end of each of the multiple second conductive sheets is connected to one of the multiple connection regions, and the other end of each second conductive sheet is connected to the source pin. One end of the first conductive sheet is connected to the gate of the semiconductor chip, and the other end of the first conductive sheet is connected to the gate pin.

[0007] Preferably, both the first conductive sheet and the second conductive sheet are copper sheet conductors.

[0008] Preferably, a first pad is provided at both ends of the first conductive sheet, and the two first pads are respectively soldered to the gate of the semiconductor chip and the gate pin through solder paste.

[0009] Preferably, a second pad is provided at both ends of the second conductive sheet, and the two second pads are respectively soldered to the connection area on the source electrode of the semiconductor chip and the source electrode pin through solder paste.

[0010] Preferably, the welding surface of the first gasket is plated with a silver layer.

[0011] Preferably, the welding surface of the second gasket is plated with a silver layer.

[0012] Preferably, the multiple connection regions on the source metallization layer of the semiconductor chip are defined by multiple spaced shadow lines formed simultaneously during the doping process in its fabrication.

[0013] Preferably, the package is composed of epoxy resin and a plastic shell covering the outside of it, wherein the epoxy resin covers the copper-based island, the semiconductor chip, the first conductive sheet, the plurality of second conductive sheets, and a portion of the gate pin and source pin.

[0014] The beneficial technical effects of this application are as follows: By employing multiple independent sheet-like second conductive sheets and welding them one-to-one onto a pre-fabricated uniform connection area at the chip source, multiple parallel current channels with large cross-sectional areas, short paths, and uniform distribution are constructed. This design eliminates the current congestion effect caused by the random distribution of traditional bonding copper wires, allowing the current to be distributed uniformly, maximizing the current-carrying capacity of all conductors, significantly reducing the contact resistance and interconnect resistance of the source circuit, thereby greatly reducing the overall on-resistance of the device. Low internal resistance directly means lower conduction losses, effectively improving the energy conversion efficiency of the device itself and even the entire power system. Uniform current distribution avoids "hot spots" caused by excessively high local current density. Each second conductive sheet evenly shares the current and heat generation, making the temperature distribution of the chip and interconnect structure more uniform and avoiding local overheating. This effectively slows down the performance degradation and material aging caused by thermal stress and high temperature acceleration, greatly improving the long-term operational reliability and service life of the device under high temperature and high power operating conditions. The pre-fabricated, regularly distributed connection areas during chip manufacturing provide a precise and fixed positioning reference for the subsequent soldering of the second conductive sheet. This solves the problem of random and uneven solder joint positioning caused by the flat and featureless source metal layer in traditional processes. This design enables high consistency and repeatability of solder joint positions in automated production, significantly improving the controllability, yield, and production efficiency of the manufacturing process, while reducing reliance on manual experience. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the overall structure of a low internal resistance, high energy efficiency field-effect transistor according to this embodiment.

[0016] Figure 2 This is a schematic diagram of the structure of a low internal resistance, high energy efficiency field-effect transistor after removing the package in this embodiment.

[0017] Reference numerals: 1. Copper-based island; 2. Semiconductor chip; 3. Gate pin; 4. Source pin; 5. Package; 6. First conductive sheet; 7. Second conductive sheet; 8. Shaded line; 9. Connection area; 10. First pad; 11. Second pad. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] Reference Figure 1 and Figure 2 A low-resistance, high-efficiency field-effect transistor comprises a copper-based island 1, a semiconductor chip 2, a gate pin 3, a source pin 4, a package 5, a first conductive plate 6, and multiple second conductive plates 7. The semiconductor chip 2, as the core component, has its back drain securely soldered and electrically connected to the flat upper surface of the copper-based island 1 using a highly reliable solder paste sintering process. The copper-based island 1 also serves as the main heat dissipation channel and the electrical lead-out terminal for the drain. Both the gate pin 3 and the source pin 4 are made of copper. The gate on the front of the semiconductor chip 2 is connected via the first conductive plate 6. One end of the first conductive plate 6 is soldered to the metal pad of the gate of the semiconductor chip 2 using solder paste, and the other end is similarly soldered to the inner portion of the gate pin 3 using solder paste, thus forming a low-inductive gate control signal path.

[0020] Reference Figure 1 and Figure 2 The source region on the front side of semiconductor chip 2 serves as its high-current output channel. To address the inherent defect of uneven distribution in traditional bonding wires, multiple finely spaced shadow lines 8 are simultaneously formed on its large-area source metallization layer during the semiconductor chip 2 fabrication stage through a doping process. These shadow lines 8 clearly define multiple electrically isolated square or circular connection areas 9 arranged in a regular matrix. Each connection area 9 has one end of an independent second conductive sheet 7 soldered to it using solder paste. These second conductive sheets 7 are all copper sheet conductors with a larger cross-sectional area and better thermal conductivity. The other ends of all the second conductive sheets 7 converge and are soldered to the wide inner platform of the source pin 4, thus forming multiple parallel source current channels with large cross-sectional areas, short paths, uniform distribution, and extremely low resistance, ensuring that current flows uniformly and efficiently from the chip source to the pin.

[0021] Reference Figure 1 and Figure 2 To further optimize soldering reliability and conductivity, rectangular first pads 10, wider and thicker than the conductive sheet body, are provided at both ends of the first conductive sheet 6, and rectangular second pads 11, wider and thicker than the conductive sheet body, are provided at both ends of the second conductive sheet 7. The soldering surfaces of these pads are also plated with a high-quality silver layer to enhance the wettability and soldering strength of the solder paste and reduce contact resistance. The package 5 includes epoxy resin and a plastic shell. The entire assembly structure includes a copper-based island 1, a chip, all conductive sheets, and the inner portions of the gate pins 3 and source pins 4. The epoxy resin is filled and encapsulated in the mold cavity, and a robust plastic shell is formed outside the epoxy resin through injection molding, thus completing the device encapsulation and giving it good mechanical strength, insulation, and environmental protection capabilities.

[0022] Although embodiments of this application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A low-resistance, high-efficiency field-effect transistor, comprising a copper-based island, a semiconductor chip, a gate pin, a source pin, and a package, wherein the semiconductor chip has a drain, a gate, and a source, and its drain is fixedly connected to the copper-based island by a solder paste sintering process, characterized in that: It also includes a first conductive sheet and a plurality of second conductive sheets. The source metallization layer of the semiconductor chip has a plurality of interconnected regions that are spaced apart and uniformly arranged. One end of each of the plurality of second conductive sheets is connected to one of the plurality of interconnected regions, and the other end of each of them is connected to the source pin. One end of the first conductive sheet is connected to the gate of the semiconductor chip, and the other end of each of them is connected to the gate pin.

2. A low-internal-resistance high-energy-efficiency field-effect tube according to claim 1, characterized in that: Both the first conductive sheet and the second conductive sheet are sheet conductors made of copper.

3. A low-internal-resistance high-energy-efficiency field-effect tube according to claim 1 or 2, characterized in that: The first conductive sheet has a first pad at both ends, and the two first pads are soldered to the gate and the gate pin of the semiconductor chip respectively through solder paste.

4. A low-internal-resistance high-energy-efficiency field-effect transistor according to claim 1 or 2, characterized in that: The second conductive sheet has a second pad at both ends, and the two second pads are soldered to the connection area on the source of the semiconductor chip and the source pin respectively through solder paste.

5. A low-internal-resistance high-energy-efficiency field-effect transistor according to claim 3, characterized in that: The welding surface of the first gasket is plated with a silver layer.

6. A low-internal-resistance high-energy-efficiency field-effect transistor according to claim 4, characterized in that: The welding surface of the second gasket is plated with a silver layer.

7. A low internal resistance, high energy efficiency field-effect transistor according to claim 1, characterized in that: The multiple connection regions on the source metallization layer of the semiconductor chip are defined by multiple spaced shadow lines formed simultaneously during the doping process in its fabrication.

8. A low-internal-resistance high-energy-efficiency field-effect transistor according to claim 1, characterized in that: The package is composed of epoxy resin and a plastic shell covering the outside of it. The epoxy resin covers the copper-based island, the semiconductor chip, the first conductive sheet, the plurality of second conductive sheets, and a portion of the gate pin and source pin.

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