A quartz crystal oscillator electrical performance parameter evaluation test circuit board
By designing a clock signal trace impedance of 50Ω±5% and an impedance matching resistor of 20Ω~25Ω on the quartz crystal oscillator evaluation test board, combined with load simulation and power supply purification, the signal reflection problem was solved, ensuring the accuracy of the test results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HEYUAN XINGTONG TIME FREQUENCY ELECTRONICS CO LTD
- Filing Date
- 2025-07-08
- Publication Date
- 2026-07-07
AI Technical Summary
The trace impedance design of existing quartz crystal oscillator evaluation test boards lacks specificity, leading to energy loss and reflection during signal transmission, which affects the accuracy of test results.
The clock signal trace impedance is designed to be 50Ω±5%, and an impedance matching resistor of 20Ω~25Ω is connected in series between the output pin of the oscillator under test and the clock signal trace. Combined with the load simulation module and the power purification module, impedance matching of signal transmission and reduction of reflected waves are ensured.
It significantly reduces the reflection coefficient during signal transmission, ensures that the waveform quality of the clock signal meets the CMOS level standard, and improves the accuracy of test results.
Smart Images
Figure CN224471791U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electronic component testing technology, specifically to a test circuit board for evaluating the electrical performance parameters of a quartz crystal oscillator. Background Technology
[0002] Against the backdrop of the rapid development of the electronic information industry, clock signals, as the core synchronization reference for various electronic devices, are widely used in core components such as digital chips, microcontrollers, and communication modules. Their performance directly affects the operational accuracy and stability of electronic systems. Among them, CMOS level clock signals, due to their advantages such as low power consumption and strong anti-interference capabilities, have become one of the most mainstream clock signal level standards in the field of digital chips. CMOS level clock signals have strict requirements for quality: the high level must be greater than 90% of the power supply voltage (VDD), the low level must be less than 10% of VDD, and the rise and fall times must be controlled in the nanosecond range to meet the timing requirements of high-speed digital circuits. Therefore, accurate electrical performance parameter evaluation and testing of quartz crystal oscillators (as the core source of clock signals) is a crucial step in ensuring that they meet the CMOS level standard in practical applications.
[0003] Currently, the industry's evaluation and testing of quartz crystal oscillators mainly relies on dedicated test circuit boards. However, the trace impedance design of these evaluation circuit boards lacks specificity and fails to strictly match the output characteristics of the quartz crystal oscillator with the input requirements of subsequent test equipment. For example, some evaluation boards do not perform impedance control on the clock signal traces, causing the trace impedance to deviate from the standard value, resulting in energy loss and reflection during signal transmission. In addition, the output impedance of the quartz crystal oscillator usually differs from the characteristic impedance of the traces on the evaluation board. If the two are not effectively connected through matching resistors, the signal will be reflected at the interface. The superposition of the reflected wave and the incident wave will cause high and low level shifts and edge distortion of the clock signal, seriously affecting the accuracy of the test results. Utility Model Content
[0004] In view of the above problems, this utility model provides a test circuit board for evaluating the electrical performance parameters of a quartz crystal oscillator. The test circuit board includes a substrate, on which a clock signal trace is provided, the impedance of which is 50Ω±5%.
[0005] The device under test (DUT) mounting position is located on the substrate, and the signal output terminal of the DUT mounting position is connected to the clock signal trace.
[0006] An impedance matching resistor is connected in series between the output pin of the oscillator under test and the clock signal trace. The resistance value of the impedance matching resistor is in the range of 20Ω to 25Ω.
[0007] The test interface group includes a first test interface and a second test interface, which are set at different locations on the clock signal trace.
[0008] In one possible implementation, the quartz crystal oscillator electrical performance parameter evaluation test circuit board further includes:
[0009] The load simulation module includes at least three load branches connected in parallel. The load simulation module is connected to the clock signal trace via a switching unit, which is used to selectively connect one or more of the load branches to the clock signal trace.
[0010] In one possible implementation, each of the load branches includes capacitors with different capacitance values, which are combined by the switching unit to form different load capacitance values.
[0011] In one possible implementation, the first test interface is a test pad connected between the impedance matching resistor and the load simulation module.
[0012] In one possible implementation, the quartz crystal oscillator electrical performance parameter evaluation test circuit board further includes:
[0013] A power socket is connected to the power input pin of the mounting position of the component under test via a power purification module, which is used to filter out power noise.
[0014] In one possible implementation, the power purification module includes an inductor connected in series with the power input pin of the device under test mounting location and at least one decoupling capacitor connected in parallel with the power input pin of the device under test mounting location.
[0015] In one possible implementation, the quartz crystal oscillator electrical performance parameter evaluation test circuit board further includes:
[0016] An enable control unit is connected to the control terminal of the mounting position of the device under test (DUT). The enable control unit is used to control the enable state of the DUT to evaluate its startup time, shutdown characteristics, or enable voltage threshold.
[0017] In one possible implementation, the enable control unit includes a single-channel DIP switch.
[0018] In one possible implementation, the substrate includes a top signal layer, an internal ground layer, an internal power layer, and a bottom signal layer, wherein the internal ground layer is disposed below the top signal layer to form a complete reference ground plane, and the clock signal trace is disposed on the top signal layer.
[0019] In one possible implementation, the second test interface is an RF coaxial interface, which is directly connected to the end of the clock signal trace and is used to connect an RF coaxial cable.
[0020] The above-described one or more technical solutions in the embodiments of this application have at least one or more of the following technical effects:
[0021] The quartz crystal oscillator electrical performance parameter evaluation test circuit board provided in this embodiment of the invention uses a 50Ω±5% impedance control for the clock signal trace to strictly match the input impedance requirements of digital chips under the CMOS level standard. Simultaneously, by connecting a 20Ω~25Ω impedance matching resistor in series between the output pin of the oscillator under test and the clock signal trace, the consistency between the output impedance of the tested component and the characteristic impedance of the trace is further adjusted. This design significantly reduces the reflection coefficient during signal transmission, effectively avoids the superposition of reflected and incident waves, thereby suppressing the high and low level offset and edge distortion of the clock signal, and ensuring that the waveform quality of the clock signal meets the CMOS level standard during the test.
[0022] The above description is merely an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this utility model more obvious and understandable, specific embodiments of this utility model are given below. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a schematic diagram of the structure of the quartz crystal oscillator electrical performance parameter evaluation test circuit board in an embodiment of this utility model;
[0025] Figure 2 This is a schematic diagram of the circuit principle of the quartz crystal oscillator electrical performance parameter evaluation and testing circuit board in the embodiment of this utility model;
[0026] Figure 3 This is a schematic diagram of the layered structure of the test circuit board for evaluating the electrical performance parameters of the quartz crystal oscillator in this embodiment of the present invention.
[0027] Explanation of reference numerals in the attached figures: 100, substrate; 101, top signal layer; 102, internal ground layer; 103, internal power layer; 104, bottom signal layer; 110, clock signal trace; 120, mounting position of the component under test; 130, impedance matching resistor; 140, first test interface; 150, second test interface; 160, load simulation module; 161, switching unit; 170, power socket; 180, power purification module; 190, enable control unit. Detailed Implementation
[0028] To make the objectives, technical solutions, and advantages of this utility model clearer, the embodiments of this utility model will be described in further detail below with reference to the accompanying drawings.
[0029] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. In the following description, when referring to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this invention as detailed in the appended claims.
[0030] The overall concept of the technical solution provided by this utility model is as follows:
[0031] Please see Figure 1 The quartz crystal oscillator electrical performance parameter evaluation test circuit board includes:
[0032] The substrate has clock signal traces with an impedance of 50Ω ± 5%. The main function of these traces is to transmit the clock signal generated by the quartz crystal oscillator to subsequent test equipment or digital chips. In digital circuits, especially under CMOS level standards, the input impedance of digital chips is typically designed to be 50Ω. Controlling the impedance of the clock signal traces to 50Ω ± 5% ensures good matching with the input impedance of the digital chip, thereby reducing signal reflection. The ± 5% tolerance means that the actual impedance of the clock signal traces can vary between 47.5Ω and 52.5Ω.
[0033] Understandably, the width and thickness of traces are key factors affecting impedance. By adjusting the width and thickness of the traces, the impedance can be controlled. Impedance calculation software, such as Polar Si9000 or JLCPCB's impedance calculation tool, can be used to calculate the required PCB characteristic impedance of 50Ω, including trace width, trace spacing, PCB board type, and lamination structure. After the PCB is manufactured, the impedance of the clock trace section is actually tested. If it does not meet the requirements, the design parameters are adjusted again until the impedance design meets the design requirements.
[0034] The component under test (DUT) mounting position is located on the substrate. The signal output terminal of the DUT mounting position is connected to the clock signal trace. The DUT mounting position is a specific location for mounting the quartz crystal oscillator under test. The signal output terminal of the DUT is connected to the clock signal trace of the test circuit board through this position to ensure that the signal can be accurately and completely transmitted to the subsequent test equipment or analysis instruments. Common types of DUT mounting positions include DIP (Dual In-line Package) slots, SMD (Surface Mount Device) slots, or other dedicated slots. The type of DUT mounting position can be selected according to actual needs.
[0035] Impedance matching resistors are connected in series between the output pin of the oscillator under test and the clock signal trace. The resistance value of the impedance matching resistor ranges from 20Ω to 25Ω. When a signal is transmitted through a point of impedance discontinuity, reflected waves are generated. The superposition of the reflected waves and the incident waves will cause signal distortion. By connecting an impedance matching resistor in series between the oscillator output pin and the clock signal trace, impedance matching can be adjusted to reduce reflections. In addition, the output impedance of a quartz crystal oscillator usually differs from the characteristic impedance of the clock signal trace. By selecting an appropriate impedance matching resistor, the output impedance of the oscillator can be adjusted to be closer to the characteristic impedance of the trace. In practical applications, the optimal impedance matching resistor value needs to be determined through calculation and experimentation based on the output impedance of the oscillator under test and the characteristic impedance of the clock signal trace.
[0036] The test interface group includes a first test interface and a second test interface, which are located at different positions on the clock signal trace. Tests can be performed by touching the first test interface with an oscilloscope probe, or by directly inputting the signal to the oscilloscope terminal via a cable through the second test interface. The testing method can be adjusted and optimized according to specific needs and the testing environment to achieve the best test results. It is important to note that during testing, only one of the first and second test interfaces can be used at a time; simultaneous testing is prohibited to avoid signal reflection, crosstalk, or load effects that may affect the accuracy of the test results.
[0037] By employing an impedance control of 50Ω±5% for the clock signal trace, the input impedance requirements of digital chips under the CMOS level standard are strictly matched. Simultaneously, by connecting a 20Ω~25Ω impedance matching resistor in series between the output pin of the oscillator under test and the clock signal trace, the consistency between the output impedance of the device under test and the characteristic impedance of the trace is further adjusted. This design significantly reduces the reflection coefficient during signal transmission, effectively avoids the superposition of reflected waves and incident waves, thereby suppressing the offset of high and low levels of the clock signal and edge distortion, and ensuring that the waveform quality of the clock signal meets the CMOS level standard during the test.
[0038] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0039] Please see Figure 1 The quartz crystal oscillator electrical performance parameter evaluation test circuit board also includes:
[0040] The load simulation module includes at least three load branches connected in parallel. It is connected to the clock signal trace via a switching unit, which selectively connects one or more load branches to the clock signal trace. By using at least three parallel load branches, different load conditions can be simulated, such as different load impedances and capacitances. By testing the output characteristics of the quartz crystal oscillator under different load conditions, its driving capability, stability, noise, and other performance parameters can be comprehensively evaluated. The switching unit allows for flexible selection of the number and combination of connected load branches to adapt to different testing needs.
[0041] More specifically, the types of load branches can include resistive loads, capacitive loads, inductive loads, and composite loads. Resistive loads simulate purely resistive loads and are often used to evaluate the driving capability and power consumption of oscillators. Capacitive loads simulate capacitive loads and are often used to evaluate the frequency stability and phase noise of oscillators. Inductive loads simulate inductive loads and are often used to evaluate the resonant characteristics and anti-interference capability of oscillators. Composite loads combine resistors, capacitors, and inductors to simulate more complex real-world application scenarios. Different types of load branches can be selected or more load branches can be added as needed.
[0042] Furthermore, each load branch contains capacitors with different capacitance values, which are combined by switching units to form different load capacitance values. For example, please refer to [link to relevant documentation]. Figure 2The first load branch includes a 15pF capacitor CL1, the second load branch includes a 30pF capacitor CL2, and the third load branch includes a 50pF capacitor CL3. The switching unit includes a DIP switch SW2. When only switch 1 of the DIP switch SW2 is closed, a load capacitance of 15pF is achieved; when only switch 2 of the DIP switch SW2 is closed, a load capacitance of 30pF is achieved; and when only switch 3 of the DIP switch SW2 is closed, a load capacitance of 50pF is achieved. The load capacitance value can be 45pF when only switches 1 and 2 of the multiplex switch SW2 are closed, 65pF when only switches 1 and 3 of the multiplex switch SW2 are closed, and 80pF when only switches 2 and 3 of the multiplex switch SW2 are closed. By designing load branches containing capacitors of different values and using switching units to form different load capacitance values, various load conditions can be flexibly simulated, and the electrical performance of the quartz crystal oscillator can be comprehensively evaluated.
[0043] Furthermore, the first test interface is test pad TP1, which is connected between the impedance matching resistor and the load simulation module. As a signal monitoring point, the test pad allows signal measurements to be performed on the signal path between the impedance matching resistor and the load simulation module. The test pad TP1 should be large enough to facilitate contact with an oscilloscope probe.
[0044] Please see Figure 1 The quartz crystal oscillator electrical performance parameter evaluation test circuit board also includes:
[0045] The power socket connects to the power input pins of the device under test (DUT) mounting location via a power purification module. The power purification module filters out power supply noise. As the interface between the external power supply and the test circuit board, the power socket provides power connection to transmit external power to various modules on the board, including the power input pins of the DUT mounting location. The power purification module filters out noise in the power supply, ensuring a clean and stable power supply to the DUT. The power purification module may include common filters, voltage regulators, decoupling capacitors, etc.
[0046] Furthermore, the power purification module includes an inductor connected in series with the power input pin of the device under test (DUT) mounting location and at least one decoupling capacitor connected in parallel with the power input pin of the DUT mounting location. For example, please refer to... Figure 2The power purification module includes capacitors C1, C2, C3, and C4 connected in parallel to the power input pin of the device under test (DUT) mounting position, and a ferrite bead L1 connected in series at the power input pin of the DUT mounting position. These capacitors, connected in parallel at the power input pin of the DUT, form a low-pass filter to filter out power noise of different frequencies. The ferrite bead L1, connected in series at the power input pin of the DUT, forms a high-frequency filter to prevent high-frequency noise from entering the DUT.
[0047] Please see Figure 1 The quartz crystal oscillator electrical performance parameter evaluation test circuit board also includes:
[0048] The enable control unit connects to the control terminal of the mounting position of the device under test (DUT). It controls the enable state of the DUT to evaluate its startup time, shutdown characteristics, or enable voltage threshold. Through the enable control unit, the enable and disable states of the DUT can be precisely controlled. It can measure the startup time from when the enable signal is valid to when the output signal stabilizes, the shutdown time from when the enable signal is invalid to when the output signal is completely turned off, and determine the effective voltage range of the enable signal—that is, the minimum and maximum enable voltages required for the DUT to begin normal operation.
[0049] For further details, please refer to Figure 2 The enable control unit includes a single-channel DIP switch SW1. One terminal of the single-channel DIP switch SW1 is grounded, and the other terminal is connected to the enable pin of the device under test (DUT). When the single-channel DIP switch SW1 is in the enabled position, the enable pin is connected to ground through the single-channel DIP switch SW1, achieving a low-level enable. When the single-channel DIP switch SW1 is in the off position, the enable pin is floating. For example, by setting the single-channel DIP switch SW1 to the enable position and then using an oscilloscope to monitor the output signal of the DUT, the time from when the single-channel DIP switch SW1 is set to the enable position can be recorded. The delay time until the output signal stabilizes is the start-up time. Set the single-channel DIP switch SW1 to the disabled position, use an oscilloscope to monitor the output signal of the component under test, and record the delay time from when the single-channel DIP switch SW1 is set to the disabled position until the output signal is completely turned off. This is the turn-off time. Set the single-channel DIP switch SW1 to the open position, gradually adjust the enable voltage, starting from 0V and gradually increasing it. Use an oscilloscope to monitor the output signal of the component under test, and record the transition point of the enable signal voltage from invalid to valid. This is the enable voltage threshold.
[0050] Please see Figure 3The substrate comprises a top signal layer, an internal ground layer, an internal power layer, and a bottom signal layer. The internal ground layer is located below the top signal layer, forming a complete reference ground plane. Clock signal traces are located on the top signal layer. The top signal layer is used to route high-frequency, high-speed signal lines, such as clock signal traces. The internal ground layer, located below the top signal layer, forms a complete reference ground plane, providing a low-impedance signal return path and reducing signal reflection and noise. The internal power layer, located below the internal ground layer, forms a power distribution network, providing power to components on the circuit board. The bottom signal layer is used to route low-speed signal lines, power lines, and other auxiliary signal lines. The power layer provides isolation between the bottom signal layer and the internal ground layer, reducing signal interference. By placing the clock signal traces on the top signal layer, the internal ground layer can be used as a reference ground plane, forming a good signal return path. On the top signal layer, the impedance of the clock signal traces can be controlled by adjusting the trace width, trace spacing, and dielectric thickness.
[0051] Please see Figure 2 The second test interface is the RF coaxial interface RF2, which is directly connected to the end of the clock signal trace. RF2 is used to connect the RF coaxial cable. RF2 transmits high-frequency clock signals, ensuring low loss and good signal integrity during transmission. Its direct connection to the clock signal trace ensures the continuity and integrity of the signal path. RF2 allows for easy connection and disconnection of the RF coaxial cable, facilitating testing and debugging. Furthermore, the RF coaxial interface has an impedance of 50Ω, matched to the clock signal trace impedance to reduce signal reflection and distortion.
[0052] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.
[0053] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this utility model without departing from the spirit and scope of the embodiments of this utility model. Therefore, if these modifications and variations to the embodiments of this utility model fall within the scope of the claims of this utility model and their equivalents, then this utility model also intends to include these modifications and variations.
Claims
1. A circuit board for evaluating and testing the electrical performance parameters of a quartz crystal oscillator, characterized in that, include: A substrate having clock signal traces provided thereon, the impedance of which is 50Ω±5%; The device under test (DUT) mounting position is located on the substrate, and the signal output terminal of the DUT mounting position is connected to the clock signal trace. An impedance matching resistor is connected in series between the output pin of the oscillator under test and the clock signal trace. The resistance value of the impedance matching resistor is in the range of 20Ω to 25Ω. The test interface group includes a first test interface and a second test interface, which are set at different locations on the clock signal trace.
2. The quartz crystal oscillator electrical performance parameter evaluation and testing circuit board according to claim 1, characterized in that, Also includes: The load simulation module includes at least three load branches connected in parallel. The load simulation module is connected to the clock signal trace via a switching unit, which is used to selectively connect one or more of the load branches to the clock signal trace.
3. The quartz crystal oscillator electrical performance parameter evaluation and testing circuit board according to claim 2, characterized in that, Each of the load branches contains capacitors with different capacitance values, which are combined by the switching unit to form different load capacitance values.
4. The quartz crystal oscillator electrical performance parameter evaluation and testing circuit board according to claim 2, characterized in that, The first test interface is a test pad, which is connected between the impedance matching resistor and the load simulation module.
5. The quartz crystal oscillator electrical performance parameter evaluation and testing circuit board according to claim 1, characterized in that, Also includes: A power socket is connected to the power input pin of the mounting position of the component under test via a power purification module, which is used to filter out power noise.
6. The quartz crystal oscillator electrical performance parameter evaluation and testing circuit board according to claim 5, characterized in that, The power purification module includes an inductor connected in series with the power input pin of the mounting position of the component under test and at least one decoupling capacitor connected in parallel with the power input pin of the mounting position of the component under test.
7. The quartz crystal oscillator electrical performance parameter evaluation and testing circuit board according to claim 1, characterized in that, Also includes: An enable control unit is connected to the control terminal of the mounting position of the device under test (DUT). The enable control unit is used to control the enable state of the DUT to evaluate its startup time, shutdown characteristics, or enable voltage threshold.
8. The quartz crystal oscillator electrical performance parameter evaluation and testing circuit board according to claim 7, characterized in that, The enable control unit includes a single-channel DIP switch.
9. A test circuit board for evaluating electrical performance parameters of a quartz crystal oscillator according to any one of claims 1-8, characterized in that, The substrate includes a top signal layer, an internal ground layer, an internal power layer, and a bottom signal layer, wherein the internal ground layer is disposed below the top signal layer to form a complete reference ground plane, and the clock signal trace is disposed on the top signal layer.
10. A test circuit board for evaluating electrical performance parameters of a quartz crystal oscillator according to any one of claims 1-8, characterized in that, The second test interface is an RF coaxial interface, which is directly connected to the end of the clock signal trace and is used to connect an RF coaxial cable.