Memory circuit and memory system

Abstract

A memory circuit and a memory system. The memory circuit includes a plurality of memory cells commonly coupled to a word line, a word line driver, an overvoltage generator, and a memory controller. The word line driver is selectively coupled to the word line to cause the word line to attain a first voltage. The memory controller couples the word line driver to the word line to cause the word line to attain the first voltage. The memory controller decouples the word line driver from the word line to maintain the word line at the first voltage. The memory controller couples the overvoltage generator to a capacitor to charge the capacitor to a second voltage. The memory controller couples the capacitor to the word line to cause the word line to attain the second voltage. The memory controller writes a data value to the memory cells while the word line is driven to the second voltage.

Description

Technical Field

[0001] This disclosure relates to memory circuits and memory systems. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to a series of improvements in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). These improvements in integration density primarily stem from the continuous reduction in the size of the smallest feature, allowing more components to be integrated into a given area. Utility Model Content

[0003] This disclosure provides a memory circuit comprising a plurality of memory cells, a word line driver, an overvoltage generator, and a memory controller. The plurality of memory cells are commonly coupled to a word line. The word line driver is selectively coupled to the word line and configured to bring the word line to a first voltage when coupled to the word line. The overvoltage generator is configured to charge a capacitor. The memory controller is configured to: couple the word line driver to the word line to bring the word line to the first voltage; decouple the word line driver from the word line to maintain the word line at the first voltage; couple the overvoltage generator to the capacitor to charge the capacitor to a voltage exceeding the first voltage; couple the capacitor to the word line to bring the word line to the voltage exceeding the first voltage; and write a data value to one of the plurality of memory cells when the word line is driven to the voltage exceeding the first voltage.

[0004] This disclosure provides a memory system comprising a plurality of memory cells, a first driver, a second driver, and a controller. The plurality of memory cells are commonly coupled to a word line. The first driver is configured to bring the word line to a first voltage when coupled to the word line. The second driver is configured to bring the word line to a second voltage, the second voltage being greater than the first voltage. The controller is configured to activate either the first driver or the second driver based on a time interval of a write cycle and an operating condition of the plurality of memory cells.

[0005] This disclosure provides a memory circuit including a word line driver and a first overvoltage generator. The word line driver drives the word line to a first voltage. The first overvoltage generator charges a capacitor to a second voltage greater than the first voltage. When the word line is decoupled from the word line driver and the capacitor is coupled to the word line, the word line reaches a third voltage greater than the first voltage. When the word line reaches the third voltage, a first memory cell coupled to the word line stores a data value. Attached Figure Description

[0006] The embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation.

[0007] Figure 1 A block diagram of a memory circuit according to some embodiments is shown;

[0008] Figure 2 The illustration depicts the operation according to some embodiments. Figure 1 The memory circuit is a combination of waveforms of various signals;

[0009] Figure 3 Illustrations based on some embodiments Figure 1 A schematic diagram of a portion of the memory circuitry;

[0010] Figure 4 A schematic diagram of voltage lines and capacitor electrodes according to some embodiments is shown;

[0011] Figure 5 Illustrations based on some embodiments Figure 4 A physical implementation method for voltage lines and capacitor electrodes;

[0012] Figure 6 Another block diagram of a memory circuit according to some embodiments is shown;

[0013] Figure 7 Illustrations based on some embodiments Figure 6 A schematic diagram of a portion of the memory circuitry;

[0014] Figure 8 A schematic diagram of a memory circuit according to some embodiments is shown;

[0015] Figure 9 A block diagram of a portion of a memory circuit according to some embodiments is shown;

[0016] Figure 10 Illustrations based on some embodiments Figure 9 A schematic diagram of a portion of the memory circuitry; and

[0017] Figure 11 A flowchart illustrating a memory circuit operation method according to some embodiments is shown.

[0018] [Symbol Explanation]

[0019] 100: Memory System / Memory Circuit

[0020] 110: Controller / Memory Controller

[0021] 120: Memory Array

[0022] 122: Character Line

[0023] 130: Character line driver

[0024] 132: VDDHD line / VDDHD structure / First VDDHD line

[0025] 134: Second VDDHD line / VDDHD line

[0026] 140: Overvoltage generator (OVG) / First OVG / Second OVG

[0027] 142: Electrode / Capacitor Electrode / First Electrode Section

[0028] 144: Capacitor Electrode / Second Electrode Section

[0029] 146: First capacitor / capacitor electrode / capacitor

[0030] 148: Second capacitor

[0031] 200: Waveform Combination

[0032] 202: First waveform

[0033] 204: Second Waveform

[0034] 206: Third waveform

[0035] 208: Fourth Waveform

[0036] 210: Fifth Waveform

[0037] 220: First Time

[0038] 222: Second Time

[0039] 224: Third Time

[0040] 226: Fourth Time

[0041] 302: Memory Unit

[0042] 304: Transistor

[0043] 306: Select Input

[0044] 502: Reference Voltage Line / VSS Line

[0045] 504: Power cord

[0046] 506: Signal line

[0047] 602: Address line

[0048] 702: First address input

[0049] 704: Second address input

[0050] 706: Third address input

[0051] 708: Output

[0052] 802: Electrode / First Capacitor Electrode

[0053] 804: Electrode / Second Capacitor Electrode

[0054] 806: First Choice Line

[0055] 808: Second Choice Line

[0056] 902: Address line

[0057] 904: Auxiliary Enable Line (ASTE) signal

[0058] 906: BSTE signal

[0059] 1100: Method

[0060] 1110: Operation

[0061] 1120: Operation

[0062] 1130: Operation

[0063] 1140: Operation

[0064] 1150: Operation

[0065] BL: Bitline

[0066] CAP: Capacitor

[0067] VDD: Voltage

[0068] VSS: Ground Reference / Reference Voltage

[0069] WL: Character Line

[0070] WL0: Character Line

[0071] WL1: Character Line

[0072] WLJ: Character Line

[0073] XU: Address Input Detailed Implementation

[0074] The following disclosure provides numerous different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the embodiments of this disclosure may repeat element symbols and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0075] Furthermore, for ease of description, this document uses spatially relative terms (such as "below," "under," "lower," "above," "upper," "top," "bottom," and similar) to describe the relationship between one element or feature illustrated in the figures and another element (or features) or feature (or features). In addition to the orientations depicted in the figures, spatially relative terms are intended to encompass different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations) and therefore the spatially relative descriptive terms used herein can be interpreted similarly.

[0076] A reference to "or" can be interpreted as inclusive, meaning any term described using "or" can represent a single descriptive term, multiple descriptive terms, or any one of all descriptive terms. When at least one conjunction is referenced, it can be interpreted as including "or" to represent a single descriptive term, multiple descriptive terms, or any one of all descriptive terms. For example, "at least one of 'A' and 'B'" can include only "A", only "B", or both "A" and "B". Such references used with "comprising" or other open-ended terms can include additional items.

[0077] Static random-access memory (SRAM) is a type of semiconductor memory typically used in computing applications requiring high-speed data access. For example, cache memory applications use SRAM to store frequently accessed data, such as data accessed by the central processing unit (CPU). SRAM memory consumes power depending on its operation and the lossy charging and discharging of the bit lines, word lines, and similar elements used to select, read, or write SRAM memory cells. Write assistance circuitry can extend the operating range by increasing the voltage, but this increase raises the overall power consumption. For example, write assistance circuitry can extend the range by decreasing the "off" state voltage of the bit lines, but this change increases power consumption, which is proportional to the length of the bit lines (e.g., corresponding to parasitic capacitance) and the number of input or output (I / O) pins coupled to the bit lines.

[0078] Generally, write assist circuitry can overdrive word lines connected to one or more memory cells in a memory cell array. Write assist circuitry may include a first driver to drive selected word lines to a first voltage, and then decouple the first driver from the word line to allow the word line to float at the first voltage. Write assist circuitry may include a second driver to charge a capacitor to a second voltage greater than the first voltage and couple the capacitor to the (floating) word line to allow the word line to reach the second voltage. The capacitor may be implemented via metal lines in the metallization layer of the memory device. Some write assist circuitry includes multiple capacitor electrodes to selectively allow word lines to reach different voltages exceeding the first voltage. (A single electrode may also be referred to as a single capacitor, but this is not limiting). Write assist circuitry may select the voltage based on operating conditions (e.g., operating voltage or temperature, or selected memory timing). In some embodiments, write assist circuitry may sequence the coupling of multiple capacitor electrodes to rotate the voltage of the word line.

[0079] Figure 1A block diagram of a memory system 100 (or memory circuit 100) according to some embodiments is shown. A memory array 120 is a hardware component for storing data. In various embodiments, the memory array 120 is implemented as a semiconductor memory device. The memory array 120 includes a plurality of storage circuits or memory cells. In some embodiments, the memory array 120 includes word lines 122 (e.g., word lines WL0, WL1, ..., WLJ) extending in a first direction and bit lines extending in a second direction (e.g., a second direction perpendicular to the first direction). The word lines 122 and bit lines may be conductive metal or conductive rails. Each memory cell is connected to one or more corresponding word lines 122 and one or more corresponding bit lines BL, and can operate according to the voltage or current flowing through the corresponding word line 122 and the corresponding bit line. In some embodiments, the memory array 120 includes additional lines (e.g., sensing lines, reference lines, reference control lines, power rails, etc.).

[0080] Controller 110 can induce operation of various lines via one or more line drivers. For example, controller 110 can control the timing of signal assertion or de-assertion of various lines, thereby providing signals to memory cells to store or transfer previously stored information. In some instances, controller 110 can operate based on multiple timing parameters such as set time, hold time, restore time, and access time. For example, longer times may correspond to low-power or low-temperature operation, while shorter times may correspond to high-power or high-temperature operation. Controller 110 can determine timing parameters locally or receive timing parameters based on communication with additional controllers (such as via registers or other communication couplings). For example, timing parameters may include configurable settings that can be accessed by controller 110 via a timing register and written to the register via a second controller (e.g., another controller communicating with memory controller 110).

[0081] The lines of memory array 120 are driven by line drivers. For example, word line driver 130 can selectively connect to selected word lines 122 to bring the selected word lines 122 to an operating voltage (e.g., to perform read or write operations). A second line driver can bring the word lines 122 to a second operating voltage. The second line driver can operate at a voltage exceeding the word line driver voltage and may be referred to as an overvoltage generator (OVG) 140. The overvoltage generator can charge a capacitor to the second operating voltage and couple the capacitor to the word line 122. The second operating voltage can increase the voltage operating range of the individual memory cells of memory array 120. The operating voltage range of the memory cells can vary depending on the operating voltage (e.g., during sleep), high operating frequency / low latency, or high temperature, such that the voltage range for successful read or write operations may be compressed or become negative, leading to memory errors.

[0082] The character line driver 130 enables the character line 122 to reach a positive voltage VDD. For example, the character line driver 130 can activate a first VDDHD line 132 positioned perpendicular to the character line 122 and a second VDDHD line 134 positioned parallel to the character line 122. Various VDDHD lines are so named to emphasize that they are not limited to the received voltage VDD. Although VDDHD lines are sometimes referred to as VDD header lines or VDD high-drain lines, these reverse abbreviations should not be construed as limitations on this disclosure. The combination of the first VDDHD line 132 and the second VDDHD line 134 increases the linear distance of the VDDHD lines. Therefore, the capacitor electrodes of the first electrode portion 142 and the second electrode portion 144 (described as including those corresponding to the first VDDHD line 132 and the second VDDHD line 134) can increase the capacitance proportional to the linear distance (proportional to a first approximate order of magnitude, as the implementation capacitance can be adjusted by layout details). That is, a first capacitor 146 is formed between the first VDDHD line 132 and the first electrode portion 142, and a second capacitor 148 is formed between the second VDDHD line 134 and the second electrode portion 144. One or more lines or other portions of the capacitor electrode may generally be referred to as electrode 142. One or more lines or other portions of the conductive structure may generally be referred to as VDDHD line 132 or VDDHD structure 132.

[0083] Controller 110 may activate OVG 140 to prevent memory errors. In some embodiments, controller 110 may activate OVG 140 by writing to or activating all word lines 122. In some embodiments, controller 110 may activate OVG 140 based on operating conditions. For example, controller 110 may be coupled to a diode or other thermal sensor to receive an operating temperature command for the semiconductor die containing memory array 120 and activate OVG 140 based on temperature. Furthermore, controller 110 may activate OVG 140 based on timing parameters or voltage. The voltage may correspond to a sensed voltage or a nominal command operating voltage, such as a startup or sleep state voltage.

[0084] In some embodiments, OVG 140 may include more than one driver to activate word line 122. For example, each of the first, second, and third drivers may bring word line 122 to a different voltage. The first, second, and third drivers may include different drivers or share one or more components. In other words, OVG 140 may include selectable output voltages. Controller 110 may select the output voltage of OVG 140 based on operating conditions or a predetermined slew rate (e.g., two or more output voltages may be sorted). OVG 140 may charge different capacitor electrodes to different values.

[0085] Figure 2 The illustration depicts the operation according to some embodiments. Figure 1 The memory circuit 100 is composed of waveforms 200 of various signals. A first waveform 202 corresponds to the selection of a bit line. For example, a bit line is selected based on the active low selection depicted to write a low value (e.g., corresponding to logic zero). Although depicted as extending to a ground reference VSS, some embodiments may additionally underdrive the bit line to achieve a greater range. However, as mentioned above, such operation can significantly increase power consumption. Therefore, in various embodiments, the overdrive word line 122 is overdrive rather than underdrive (or, in limited cases, such as extremely tight time constraints or excessively high temperatures, a combination of overdrive and underdrive is used).

[0086] The second waveform 204 corresponds to the selection of character line 122. The third waveform 206 corresponds to the overload of VDDHD lines 132 and 134. The fourth waveform 208 corresponds to the charging of capacitor electrodes 144 and 146. The fifth waveform 210 corresponds to auxiliary circuits (such as...) Figure 1The assist enable line (ASTE) of the OVG 140 is received from the memory controller 110. The driving of various signals depicted according to the waveform combination 200 may include various offsets, slew rates, or other implementation details to aid deterministic operation (e.g., avoiding race conditions). The reference to signal timing is not intended to limit the transmission or arrival of these signals to exactly the same timeframe. In fact, the layout, drive strength, or other similar designs of the memory circuitry 100 may be implemented to avoid such a situation. Rather, the timing provided herein is abstract and may aid in understanding this disclosure.

[0087] At the first time 220, word line 122 and the bit line become active (e.g., word line 122 is driven to a high active state, and the bit line is driven to a write bit state). After word line 122 and the bit line become active, word line driver 130 can decouple from word line 122, making word line 122, coupled to VDDHD lines 132, 134, a floating node. In some instances, this decoupling can be performed immediately before the second time to reduce leakage from the floating node.

[0088] At the second time 222, the capacitor electrodes can be charged to a level exceeding VDD. For example, OVG 140 may include a charge pump or other circuitry to generate a larger voltage, or OVG 140 may generate a voltage relative to another ground reference to achieve a higher voltage. The charging of capacitor electrodes 144, 146 (as shown in the fourth waveform 208) can cause the voltage on VDDHD lines 132, 134 to increase beyond the voltage VDD shown in the third waveform 206. This voltage, in turn, overloads the second waveform 204. The overload voltage can increase the operating voltage range of the various memory cells coupled to word line 122. The voltage on word line 122 measured at the memory cell may differ from (e.g., be less than) the voltage described in the second waveform 204. For example, depending on resistive losses or other losses, the word line voltage measured at the cell may be equal to or less than voltage VDD, even if the word line voltage exceeds voltage VDD when it is close to the driver.

[0089] At a third time 224 (e.g., when word line 122 is driven to a voltage exceeding VDD), controller 110 may write data values ​​to or read data values ​​from memory cells. At a fourth time 226, the valid states of various signals may be invalidated to return memory circuitry 100 to the state prior to the first time 220, except for the stored or retrieved data values.

[0090] Figure 3 Illustrations based on some embodiments Figure 1A schematic diagram of a portion of memory circuitry 100. Referring to memory array 120, the array includes a column of memory cells 302 (e.g., bit cells). Each word line 122 is connected to a plurality of memory cells 302 (such as dozens or hundreds of memory cells 302). Each memory cell 302 may be a static random access memory (SRAM) cell. For example, the memory cell 302 may be implemented as a six-transistor (6T) or eight-transistor (8T) SRAM cell. However, it should be understood that the memory cell 302 may be implemented in any of a variety of other memory configurations (e.g., DRAM) while remaining within the scope of this disclosure.

[0091] Referring to OVG 140, transistor 304 couples VDDHD line 132 to voltage VDD. The gate of transistor 304 is coupled to a control signal (ASTE) from memory controller 110. The gate is further connected to a capacitor, allowing the ASTE signal to store charge on the capacitor. Each word line 122 can be selected via select input 306, such that VDDHD line 132 is coupled only to the memory cell 302 of the selected word line 122.

[0092] Now refer to Figure 4 and Figure 5 The voltage lines and capacitor electrodes are depicted based on schematic diagrams and perspective views, respectively. In particular, Figure 4 A schematic diagram of a voltage line, VDDHD line 132, and capacitor electrode 142 according to some embodiments is shown. Figure 5 Illustrations based on some embodiments Figure 4 A physical implementation method for voltage lines and capacitor electrodes.

[0093] VDDHD structure 132 extends parallel to capacitor electrode 142 in one or more directions. VDDHD structure 132 includes a first portion (e.g., a first VDDHD line 132 depicted as part of or disposed on word line driver 130). For example, VDDHD structure 132 may be disposed in a metallization layer on the active surface of memory circuit 100. Specifically, VDDHD structure 132 includes a first VDDHD line 132 on word line driver 130, perpendicularly spaced from the active surface (e.g., transistor) of word line driver 130. VDDHD structure 132 includes a second VDDHD line 134 on memory array 120, perpendicularly spaced from the active surface (e.g., transistor) of memory cell 302 of memory array 120. Vertical spacing refers to a direction perpendicular to the plane or substantially plane of the semiconductor device containing the active surface (e.g., from the active surface upwards into the metallization layer formed on the semiconductor die). In some embodiments, lateral spacing may further exist, thereby extending the various lines to the transistor in a laterally offset manner. Similarly, the capacitor includes metal lines disposed in the metallization layer of the memory circuit 100. For example, capacitor electrode 142 includes a portion (e.g., second electrode portion 144) disposed parallel to the lines of VDDHD structure 132 (e.g., second VDDHD line 134).

[0094] like Figure 5 As depicted, the VDDHD structure 132 and capacitor electrode 142 may include lines extending parallel to each other disposed in the same metallization layer to increase the capacitance between them. For example, the lines may include a first VDDHD line 132 and a first electrode portion 142, or a second VDDHD line 134 and a second electrode portion 144. In some embodiments, the VDDHD structure 132 and capacitor electrode 142 may include lines in adjacent metallization layers that extend parallel to achieve total capacitance. Furthermore, the VDDHD structure 132 and capacitor electrode 142 may extend in different directions (e.g., vertical) to increase the linear extension associated with increased capacitance.

[0095] Continue to refer to Figure 5The word line 122 or reference voltage (VSS) line 502 may be disposed in a different metallization layer than the lines of the VDDHD structure 132 and capacitor electrode 142. This arrangement helps to isolate signals between them. For example, a power line 504 or other signal line 506 may separate the lines of the VDDHD structure 132 and capacitor electrode 142 from the word line 122 or VSS line 502. In some embodiments, the power line 504 or other signal line 506 may include lines extending substantially perpendicular to the lines of the VDDHD structure 132 and capacitor electrode 142 to manage parasitic capacitances therebetween. For example, this separation helps to manage parasitic values ​​or other signal interference when the lines of the VDDHD structure 132 and capacitor electrode 142 extend substantially parallel to the lines of the word line 122 or VSS line 502. However, this wiring (e.g., as depicted) is not intended to limit this disclosure. In fact, this disclosure may contemplate the use of any of various capacitor embodiments, such as transistor gate capacitors.

[0096] Figure 6 Another block diagram of a memory circuit 100 according to some embodiments is illustrated. The memory circuit 100 includes a memory array 120 having a first group of memory cells 302 for receiving voltages exceeding voltage VDD from a first overvoltage generator 140 (e.g., memory cells 302 connected to the upper four word lines 122). Each upper word line 122 may be connected to multiple memory cells 302 (e.g., dozens or hundreds of memory cells 302). The memory array 120 also includes a second group of memory arrays 302 for receiving voltages exceeding voltage VDD from a second overvoltage generator 140 (e.g., memory cells 302 connected to the lower four word lines 122). Each lower word line 122 may be connected to multiple memory cells 302 (e.g., dozens or hundreds of memory cells 302). For example, each upper and lower character line 122 can be connected to the same number of cells, equal to the number of columns in the memory array 120.

[0097] Including multiple OVGs 140 can reduce the vertical extension of the VDDHD structure 132 and the capacitor electrode structure 142 for charging and discharging. This configuration can reduce power consumption based on the energy loss associated with the capacitor charge and discharge cycle.

[0098] Each group of memory cells can be divided according to address lines 602. Therefore, the same address lines 602 can be used to control the selection of each of the word line drivers 130 and the overvoltage generator 140. For example, the first group of memory cells in memory array 120 (e.g., the upper half) can be addressed according to a first state of address lines 602. The first state may include addressing the uppermost part of memory array 120; thus, for an array with eight word lines 122, the word line address of [0XX] may correspond to the first four word lines 122 of the upper half, which corresponds to the first OVG 140. The word line address of [1XX] may correspond to the first four word lines 122 of the lower half, which corresponds to the second OVG 140. Therefore, the second group of memory cells can be referred to as addressable according to a second state of address lines 602, the opposite of the first state. While in the preceding examples, the opposite state may correspond to a single bit of a specific address of word line 122, the opposite state may refer to other addressing modes used to address individual memory cells of memory array 120. For example, in some embodiments, word line driver 130 may be segmented according to multiple bits of the address or an even / odd partition. Furthermore, in some embodiments, additional (e.g., four) overvoltage generators 140 may be used to optimize the various word lines 122.

[0099] Figure 7 Illustrations based on some embodiments Figure 6 A schematic diagram of a portion of the memory circuitry 100. More specifically, each word line 122 is shown as being driven by an output 708 of a word line driver 130. The output 708 is activated based on addressable inputs (address bits of address lines). For example, a first address input 702 and a second address input 704 address word lines 122 within a portion (e.g., the upper or lower portion) of the memory array 120. A topmost third address input 706 can be selected between the upper and lower portions of the memory array 120, corresponding to the first and second groups of memory cells discussed above, respectively. The topmost third address input 706 can further be used as the select line for the first OVG 140 and the second OVG 140. In particular, the address lines can be logically ANDed with the auxiliary enable lines (ASTE) of auxiliary circuitry.

[0100] Some memory cells 302, such as the top two cells, are coupled to word line 122 (e.g., continuing the previous example, the topmost word line 122). A word line driver 130 can be selectively coupled to word line 122 to bring word line 122 to a voltage, such as voltage VDD. An upper OVG 140 can charge capacitor 146 to a voltage exceeding a first voltage, such as VDDHD. Other memory cells 302, such as the bottom two cells, are coupled to another word line 122 (e.g., continuing the previous example, the bottommost word line 122). A word line driver 130 can be selectively connected to other word lines 122 to bring word line 122 to a voltage, such as voltage VDD. A lower OVG 140 can charge another capacitor 712 to a voltage exceeding a first voltage, such as VDDHD.

[0101] Figure 8 A schematic diagram of a memory circuit 100 according to some embodiments is illustrated. The capacitor includes a plurality of electrodes that can be coupled to word lines 122 to achieve a plurality of voltages corresponding to the number of electrodes. For example, the depicted example includes two such electrodes. A first capacitor electrode 802 may include... Figure 1 and Figure 2 The first capacitor electrode 802 may contain any of the features of the first capacitor electrode 142. The second capacitor electrode 804 may contain similar features or may differ from the first capacitor electrode 802. In some embodiments, the circuit 100 may include additional capacitor electrodes. Each capacitor electrode may be charged to a different voltage or have a different voltage applied to the word line 122 coupled thereto. The first capacitor electrode 802 and the second capacitor electrode 804 (and other electrodes) may store similar or different charges.

[0102] The memory controller 110 can select one or more electrodes based on operating conditions. For example, the memory controller 110 can select a first capacitor electrode 802, a second capacitor electrode 804, or both the first capacitor electrode 802 and the second capacitor electrode 804. The memory controller 110 can select electrodes 802 and 804 according to respective first selection lines 806 and second selection lines 808. Depending on the selection, the memory controller 110 can connect the selected electrodes to word lines 122 to bring the word lines 122 to a selected voltage. When more than one word line 122 is selected, the memory controller 110 can couple the selected lines to word lines 122 simultaneously (e.g., by increasing drive strength) or sequentially (e.g., by controlling rotation). For example, the memory controller 110 can couple the first capacitor electrode 802 to word lines 122 according to a predetermined timing or rotation rate, then decouple the first capacitor electrode 802, and then couple the second electrode 804 to word lines 122.

[0103] Figure 9A block diagram of a portion of a memory circuit 100 according to some embodiments is shown. A memory controller 110 can generate control signals to control the operation of a word line driver 130, another (remote) word line driver 130, and an OVG 140. The control signals can cause various memory cells 302 of the memory array 120 to store or retrieve data values.

[0104] Word line 122 is coupled to each word line driver 130. Specifically, one end of word line 122 is coupled to the near-end word line driver 130, and the second end of word line 122 is coupled to the far-end word line driver 130 at the opposite end. The replication of word line drivers 130 can manage the voltage of word line 122. For example, this replication can manage the accumulation of resistive losses or increase the overall drive strength to improve the slope of the line capacitance rotation along word line 122.

[0105] In some embodiments, controller 110 may selectively operate the remote word line driver 130 based on operating conditions. For example, during low-speed or low-temperature operation, where the voltage range is not compressed to prevent memory errors, controller 110 may disable the remote word line driver 130 to reduce power consumption and omit the control signals providing control over the operation of OVG 140. Under other operating conditions (e.g., time constraints, high-temperature operation), controller 110 may activate the remote word line driver 130 and OVG 140 (e.g., charging multiple electrodes). Under other operating conditions, controller 110 may activate any subset of the system described herein. For example, controller 110 may include a lookup table that maps operating conditions to the activation of various functions provided herein.

[0106] Referring again to the control signals, such signals may include (for example, address lines 902 including first address input 702, second address input 704, and third address input 706). The control signals may further include an ASTE signal 904 and control signals for the remote word line driver 130, which may be referred to as boost enable or BSTE signal 906.

[0107] Figure 10 Illustrations based on some embodiments Figure 9 A schematic diagram of a portion of the memory circuit 100. Further detailed, the remote word line driver 130 is depicted having an input for receiving the VDDHD structure 132 and outputting an enable signal in response to the input of the BSTE signal 906 and the detection of the word line enablement (e.g., its logical AND).

[0108] Figure 11A flowchart illustrating an operation method 1100 of a memory circuit 100 according to some embodiments is provided. For example, at least a portion of the operation (or steps) of method 1100 may be used to store data in the memory circuit 100 discussed above, or to retrieve data from the memory circuit 100. Furthermore, any operation may be controlled, managed, or timed by a memory controller 110. It should be noted that method 1100 is merely an example and is not intended to limit this disclosure. Therefore, it should be understood that... Figure 11 Additional operations may be available before, during, and / or after Method 1100, and some other operations may be briefly described here.

[0109] Method 1100 includes, during operation 1110, driving word line 122 to a first voltage via word line driver 130. For example, the first voltage may be the memory system voltage VDD. In some instances, the first voltage may be an operating voltage (e.g., causing data values ​​to be read from or written to memory cells along with the driven control line). However, in some instances, the first voltage may result in a voltage range below a threshold, potentially leading to memory errors. In some embodiments, controller 110 may predict (e.g., determine) the state of the memory cell (e.g., via a temperature or voltage input associated with the memory cell, such as from a sensor or register disposed on the same die or package). Controller 110 may enter operation 1120 or perform another operation or sub-operation based on this condition, such as selecting the electrode of a capacitor and coupling the selected electrode to word line 122 to bring word line 122 to a selected voltage.

[0110] Method 1100 includes charging the capacitor to a second voltage greater than a first voltage via a first overvoltage generator during operation 1120. In some embodiments, the capacitor may include multiple electrodes coupled to word line 122. For example, the electrodes may include an electrode coupled to a reference voltage VSS, where voltage VDD refers to the reference voltage VSS. In some embodiments, the electrode coupled to the reference voltage may reference another voltage, such as voltage VDD, such that the voltage at which the capacitor is charged will exceed voltage VDD. The capacitor includes at least one electrode spaced apart from the electrode charged at the reference voltage. For example, at least one electrode may be spaced apart from the reference voltage according to the spacing of the metallization layers of the semiconductor device. Some capacitors may include multiple such electrodes (also referred to as separate capacitors, but without limiting effect). For example, each of the first, second, and third electrodes may be charged to a different voltage. The capacitor is charged prior to operation 1140, but may also be charged at different points in the sequence of other operations provided herein.

[0111] Method 1100 includes decoupling word line 122 from word line driver 130 during operation 1130. Decoupling allows one line of word line driver 130 (e.g., VDDHD) to act as a floating node. The floating node can float at or near voltage VDD without any leakage or other interactions with adjacent signals.

[0112] Method 1100 includes, during operation 1140, coupling a capacitor to word line 122 such that word line 122 reaches a third voltage greater than the first voltage. The coupling may include electrical coupling (e.g., via switching of OVG 140) or other coupling to raise the voltage of word line 122 above the voltage VDD level.

[0113] Method 1100 includes, during operation 1150, writing a data value to a first memory cell coupled to word line 122 at a third voltage. For example, controller 110 may synchronize other bit lines, select lines, etc., with the increased voltage of overload word line 122 to perform memory operations such as reading data values ​​from memory cells or writing data values ​​to memory cells.

[0114] In one embodiment of this disclosure, a memory circuit is disclosed. The memory circuit includes a plurality of memory cells, a word line driver, an overvoltage generator, and a memory controller. The plurality of memory cells are commonly coupled to a word line. The word line driver is selectively coupled to the word line and is used to bring the word line to a first voltage when coupled to the word line. The overvoltage generator is used to charge a capacitor. The memory controller is used to: couple the word line driver to the word line to bring the word line to the first voltage; decouple the word line driver from the word line to maintain the word line at the first voltage; couple the overvoltage generator to the capacitor to charge the capacitor to a voltage exceeding the first voltage; couple the capacitor to the word line to bring the word line to the voltage exceeding the first voltage; and write a data value to one of the plurality of memory cells when the word line is driven to the voltage exceeding the first voltage.

[0115] In some embodiments of this type of memory circuit, the memory circuit is used to: receive instructions regarding operating conditions, including operating temperature, operating voltage, or timing parameters; select a voltage exceeding a first voltage based on the operating conditions; and, in response to selecting the voltage, couple a capacitor to a word line.

[0116] In some embodiments of this type of memory circuit, the capacitor includes multiple electrodes that can be coupled to the word line to bring the word line to multiple voltages.

[0117] In some embodiments of this type of memory circuit, the memory controller is used to: select a first electrode from a plurality of electrodes based on the operating conditions of the memory circuit; and couple the first electrode to a word line.

[0118] In some embodiments of this type of memory circuit, the memory controller is used to perform the following operations according to a predetermined timing or a slew rate: coupling a first electrode of a plurality of electrodes to a word line; and coupling a second electrode of a plurality of electrodes to a word line.

[0119] In some embodiments of this type of memory circuit, the capacitor includes metal lines disposed in the metallization layer of the memory circuit.

[0120] In some embodiments of this type of memory circuit, the memory circuit further includes a second group of memory cells and a second overvoltage generator. The second group of memory cells can be coupled to a second word line, and a word line driver is selectively coupled to the second word line to bring the second word line to a first voltage. The second overvoltage generator is used to charge a second capacitor to a voltage exceeding the first voltage.

[0121] In some embodiments of this type of memory circuit, a plurality of memory cells can be addressed according to a first state of the address lines, and a second group of memory cells can be addressed according to a second state of the address lines, the second state being the opposite of the first state.

[0122] In some embodiments of this type of memory circuit, the second end of the word line is coupled to a second word line driver, which is opposite to the first end of the word line, which is driven by the word line driver.

[0123] In another embodiment of this disclosure, a memory system is disclosed. The memory system includes a plurality of memory cells, a first driver, a second driver, and a controller. The plurality of memory cells are commonly coupled to a word line. The first driver is used to bring the word line to a first voltage when coupled to the word line. The second driver is used to bring the word line to a second voltage, which is greater than the first voltage. The controller is used to activate either the first driver or the second driver according to a time of a write cycle and an operating condition of the plurality of memory cells.

[0124] In some embodiments of this alternative memory system, operating conditions include the operating temperature, operating voltage, or timing parameters of the semiconductor device, which includes multiple memory cells and a controller.

[0125] In some embodiments of this alternative memory system, the timing parameters are configurable settings that can be accessed by the controller via a timing register.

[0126] In some embodiments of this alternative memory system, the controller is configured to perform the following operations to bring the word line to a second voltage: couple a first driver to the word line and activate the first driver to bring the word line to a first voltage; decouple the first driver from the word line; charge the capacitor to the second voltage; and couple one electrode of the capacitor to the word line via a second driver.

[0127] In some embodiments of this alternative memory system, a capacitor includes multiple electrodes that can be coupled to word lines. A controller selects one electrode from the multiple electrodes based on the operating conditions of the multiple memory cells and activates the word lines originating from the capacitor via a second driver.

[0128] In another embodiment of this disclosure, a method for storing a data value is disclosed. The method includes the following steps: driving a word line to a first voltage via a word line driver; charging a capacitor to a second voltage greater than the first voltage via a first overvoltage generator; decoupling the word line from the word line driver; coupling the capacitor to the word line so that the word line reaches a third voltage greater than the first voltage; and writing a data value to a first memory cell coupled to the word line at the third voltage.

[0129] In some embodiments of this alternative operating method, the capacitor includes metal lines disposed in a metallization layer, the metallization layer being perpendicularly spaced from a transistor of the first memory cell.

[0130] In some embodiments of this alternative operating method, the method further includes the following steps: charging a second capacitor to a second voltage via a second overvoltage generator; coupling the second capacitor to a second word line to bring the second word line to a third voltage; and writing a second data value to a second memory cell coupled to the word line at the third voltage. The first and second memory cells are multiple cells in the same array. A word line is coupled to a group of first memory cells in the array, the first memory cell group containing first memory cells, and the word line is connected to a first address line but not to a second address line. A second word line is coupled to a group of second memory cells in the array, the second memory cell group containing second memory cells, and the second word line is connected to a second address line but not to a first address line.

[0131] In some embodiments of this alternative operating method, the capacitor includes a first electrode and a second electrode. The first electrode is subjected to a third voltage. The second electrode is subjected to a fourth voltage. The fourth voltage is higher than the third voltage.

[0132] In some embodiments of the other-state operation method, the operation method further includes the following steps: determining that the condition of the first memory cell corresponds to a voltage, a temperature, or a configurable timing parameter; selecting a third voltage based on the condition and not selecting a fourth voltage; and in response to selecting the third voltage, coupling the first electrode of the capacitor to the word line so that the word line reaches the third voltage.

[0133] In some embodiments of this alternative operating method, the operating method further includes the following steps: driving the character line through a second character line driver located at a second end of the character line, the second end being opposite to a first end of the character line, the first end of the character line being driven by the character line driver.

[0134] In another embodiment of this disclosure, a memory circuit is disclosed. The memory circuit includes a word line driver and a first overvoltage generator. The word line driver drives the word line to a first voltage. The first overvoltage generator charges a capacitor to a second voltage greater than the first voltage. When the word line is decoupled from the word line driver and the capacitor is coupled to the word line, the word line reaches a third voltage greater than the first voltage. When the word line reaches the third voltage, a first memory cell coupled to the word line stores a data value.

[0135] As used herein, the terms “about” and “approximately” generally indicate the value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term “about” may indicate the value of a given quantity that varies from, for example, 10% to 30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0136] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can at any time design or modify other programs and structures based on the content of this disclosure to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A memory circuit, characterized in that, Include: Multiple memory cells are coupled to a single word line; A word line driver, selectively coupled to the word line and used to bring the word line to a first voltage when coupled to the word line; An overvoltage generator is used to charge a capacitor; as well as A memory controller, used to: The character line driver is coupled to the character line so that the character line reaches the first voltage; Decouple the character line driver from the character line to maintain the character line at the first voltage; The overvoltage generator is coupled to the capacitor to charge the capacitor to a voltage exceeding the first voltage; The capacitor is coupled to the character line so that the character line reaches a voltage exceeding the first voltage; as well as When the character line is driven to a voltage exceeding the first voltage, a data value is written to one of the plurality of memory cells.

2. The memory circuit as described in claim 1, characterized in that, The memory circuit is used for: Receive a command regarding an operating condition, which includes an operating temperature, an operating voltage, or a timing parameter; Based on the operating conditions, a voltage exceeding the first voltage is selected; and In response to selecting the voltage, the capacitor is coupled to the character line.

3. The memory circuit as described in claim 1, characterized in that, The capacitor includes multiple electrodes that can be coupled to the word line to bring the word line to multiple voltages.

4. The memory circuit as described in claim 3, characterized in that, The memory controller is used for: Based on an operating condition of the memory circuit, a first electrode is selected from the plurality of electrodes; and The first electrode is coupled to the character line.

5. The memory circuit as described in claim 3, characterized in that, The memory controller is used to perform the following operations according to a predetermined timing sequence or a slew rate: A first electrode of the plurality of electrodes is coupled to the character line; and A second electrode of the plurality of electrodes is coupled to the character line.

6. The memory circuit as described in claim 1, characterized in that, Further includes: A second memory cell group, the second memory cell group being coupled to a second word line, the word line driver being selectively coupled to the second word line and used to bring the second word line to the first voltage; as well as A second overvoltage generator is used to charge a second capacitor to a voltage exceeding the first voltage.

7. The memory circuit as described in claim 6, characterized in that, The plurality of memory cells can be addressed according to a first state of an address line, and the second group of memory cells can be addressed according to a second state of the address line, the second state being the opposite of the first state.

8. The memory circuit as described in claim 1, characterized in that, A second end of the character line is coupled to a second character line driver, the second end being opposite to a first end of the character line, the first end of the character line being driven by the character line driver.

9. A memory system, characterized in that, Include: Multiple memory cells are coupled to a single word line; A first driver is used to bring a first voltage to the word line when coupled to the word line; A second driver is used to bring the character line to a second voltage, the second voltage being greater than the first voltage; as well as A controller is configured to start either the first drive or the second drive based on a time of a write cycle and an operating condition of the plurality of memory cells.

10. A memory circuit, characterized in that, Include: A word line driver for driving a word line to a first voltage; and A first overvoltage generator is used to charge a capacitor to a second voltage greater than the first voltage. When the character line is decoupled from the character line driver and the capacitor is coupled to the character line, the character line reaches a third voltage greater than the first voltage, and When the character line reaches the third voltage, a first memory cell coupled to the character line is used to store a data value.

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