An isolated IGBT overcurrent protection system

Abstract

The utility model relates to overcurrent protection, especially isolating type IGBT overcurrent protection system. Including singlechip, isolation power supply and isolating type IGBT overcurrent protection circuit, wherein, the singlechip is used for output PWM signal, the isolation power supply is used for providing the positive power supply and negative power supply of isolation, one end of isolating type IGBT overcurrent protection circuit with PWM signal of singlechip is connected, and the other end of isolating type IGBT overcurrent protection circuit with isolation power supply is connected, isolating type IGBT overcurrent protection circuit is used for realizing the isolation drive and overcurrent detection of IGBT, and when detecting overcurrent, forcibly closes IGBT through hardware logic, realizes the hardware interlock of singlechip PWM signal, the utility model discloses the overcurrent detection and protection of IGBT are all by hardware real -time response, can be in any one time point instantaneous closing in overcurrent state's IGBT power transistor, thereby protects the safety of hardware device.

Description

Technical Field

[0001] This utility model relates to overcurrent protection, and more particularly to an isolated IGBT overcurrent protection system. Background Technology

[0002] IGBTs (Insulated Gate Bipolar Transistors) are core power control devices in the field of power electronics, widely used in uninterruptible power supplies (UPS), photovoltaic power generation, frequency converters, motor drives, electric vehicles, and many other areas. Due to their ability to withstand high voltage, high current, and high switching frequencies, IGBTs have become the preferred device for high-power power conversion and control, with applications ranging from small circuit board-level designs to large power module-level systems, covering most scenarios involving high-power energy conversion.

[0003] However, despite their powerful power handling capabilities, IGBTs have relatively weak overload resistance due to limitations in their materials and structure. When an overload or short-circuit fault occurs, causing the actual operating parameters to exceed the IGBT's rated limits, excessive current will flow between the collector and emitter, resulting in significant conduction losses. This loss will rapidly accumulate heat inside the device, causing the chip temperature to rise sharply. If the generated heat cannot be dissipated through the cooling system in time, the chip junction temperature may exceed its maximum allowable value, leading to thermal breakdown or permanent short-circuit damage to the IGBT. Such damage is usually irreversible and will cause the device to fail completely. Summary of the Invention

[0004] This utility model addresses the shortcomings of existing technologies by providing an isolated IGBT overcurrent protection system.

[0005] To achieve the above objectives, this utility model adopts the following technical solution: an isolated IGBT overcurrent protection system, comprising a microcontroller, an isolated power supply, and an isolated IGBT overcurrent protection circuit; wherein,

[0006] The microcontroller is used to output PWM signals;

[0007] The isolated power supply is used to provide isolated positive power (DC+15V) and negative power (DC-15V).

[0008] One end of the isolated IGBT overcurrent protection circuit is connected to the PWM signal of the microcontroller, and the other end of the isolated IGBT overcurrent protection circuit is connected to the isolated power supply.

[0009] The isolated IGBT overcurrent protection circuit is used to realize the isolated driving and overcurrent detection of the IGBT, and to forcibly shut down the IGBT through hardware logic when overcurrent is detected, thereby realizing hardware interlock with the microcontroller PWM signal.

[0010] Furthermore, the isolated IGBT overcurrent protection circuit includes a logic control unit, a drive isolation unit, a totem-pole output unit, a current detection unit, a comparison and judgment unit, and a feedback isolation unit. The logic control unit includes a first NAND gate chip (NAND1) and a first NOT gate chip (NOT1) for hardware interlocking of the overcurrent signal and the PWM signal. The drive isolation unit includes a first optocoupler (PT1) for converting the PWM control signal on the low-voltage side into an isolated drive signal on the high-voltage side. The totem-pole output unit includes a first NPN transistor (QN1) and a first PNP transistor (QP1) for enhancing the drive capability to control the fast switching of the IGBT (QT1). The current detection unit is used to collect the voltage drop across the IGBT (QT1) when it is turned on. The comparison and judgment unit includes a first comparator (COM1) for comparing the voltage drop across the IGBT with a reference voltage to determine whether there is an overcurrent. The feedback isolation unit includes a second optocoupler (PT2) for isolating and feeding back the overcurrent judgment signal to the logic control unit.

[0011] Furthermore, in the logic control unit: the first input terminal (pin 1) of the first NAND gate chip (NAND1) is connected to the PWM signal of the microcontroller; the second input terminal (pin 2) of the first NAND gate chip (NAND1) is connected to the output terminal (pin 4) of the first NOT gate chip (NOT1); the output terminal (pin 4) of the first NAND gate chip (NAND1) is connected to the input terminal (pin 3) of the first optocoupler (PT1) through the second resistor (R2); the input terminal (pin 2) of the first NOT gate chip (NOT1) is connected to the output terminal (pin 6) of the second optocoupler (PT2).

[0012] Furthermore, in the drive isolation unit: the anode (pin 2) of the input terminal of the first optocoupler (PT1) is connected to the low-voltage side power supply (+5V) through the first resistor (R1); the cathode (pin 3) of the input terminal of the first optocoupler (PT1) is connected to the output terminal (pin 4) of the first NAND gate chip (NAND1) through the second resistor (R2); the collector (pin 8) of the output terminal of the first optocoupler (PT1) is connected to the isolation positive power supply (DC+15V); and the emitter (pin 6) of the output terminal of the first optocoupler (PT1) is connected to the control terminal of the totem pole output unit through the third resistor (R3).

[0013] Furthermore, in the totem pole output unit: the bases (pin 1) of the first NPN transistor (QN1) and the first PNP transistor (QP1) are connected to the output terminal of the drive isolation unit (i.e., the other end of the third resistor (R3); the collector (pin 2) of the first NPN transistor (QN1) is connected to the isolation positive power supply (DC+15V), and the collector (pin 2) of the first PNP transistor (QP1) is connected to the isolation negative power supply (DC-15V); the emitters (pin 3) of the first NPN transistor (QN1) and the first PNP transistor (QP1) are connected to the gate (G terminal) of the IGBT (QT1) through the fourth resistor (R4).

[0014] Furthermore, the totem pole output unit also includes a sixth resistor (R6), which is connected in parallel between the gate (G terminal) and emitter (E terminal) of the IGBT (QT1) to release the gate charge when turned off, thereby accelerating the IGBT turn-off.

[0015] Furthermore, the current detection unit includes a first diode (D1), a twelfth resistor (R12), and a third capacitor (C3); the cathode of the first diode (D1) is connected to the collector (C terminal) of the IGBT (QT1), and the anode of the first diode (D1) is connected to the negative input terminal (pin 3) of the first comparator (COM1) through the twelfth resistor (R12); one end of the third capacitor (C3) is connected between the twelfth resistor (R12) and the negative input terminal (pin 3) of the first comparator (COM1), and the other end of the third capacitor (C3) is connected to isolation ground (DCGND).

[0016] Furthermore, the comparison and judgment unit also includes a voltage divider network consisting of an eighth resistor (R8), a ninth resistor (R9), and an eleventh resistor (R11) connected in series, and a first Zener diode (ZD1); the voltage divider network is connected between the isolated positive power supply (DC+15V) and the isolated ground (DCGND), and the positive input terminal (pin 2) of the first comparator (COM1) is connected between the eighth resistor (R8) and the eleventh resistor (R11) to obtain a reference voltage; the cathode and anode of the first Zener diode (ZD1) are respectively connected across the eighth resistor (R8) to clamp the reference voltage.

[0017] Furthermore, the comparison and judgment unit also includes a hysteresis circuit composed of a second diode (D2) and a seventh resistor (R7); the cathode of the second diode (D2) is connected to the output terminal (pin 7) of the first comparator (COM1), and the anode of the second diode (D2) is connected to the positive input terminal (pin 2) of the first comparator (COM1) through the seventh resistor (R7).

[0018] Furthermore, in the feedback isolation unit: the anode (pin 2) of the input terminal of the second optocoupler (PT2) is connected to the output terminal of the drive isolation unit through the fifth resistor (R5); (i.e., the other end of the third resistor (R3);) the cathode (pin 3) of the input terminal of the second optocoupler (PT2) is connected to the output terminal (pin 7) of the first comparator (COM1); the collector (pin 8) of the output terminal of the second optocoupler (PT2) is connected to the low-voltage side power supply (+5V) through the tenth resistor (R10); and the emitter (pin 6) of the output terminal of the second optocoupler (PT2) is connected to the input terminal (pin 2) of the first NOT gate chip (NOT1).

[0019] When an overcurrent condition is detected, the isolated IGBT overcurrent protection circuit uses the interlocking logic of the logic control unit to lock the second input terminal (pin 2) of the first NAND gate chip (NAND1) to a low level, thereby ignoring the level state of the microcontroller's PWM signal and forcing its output terminal (pin 4) to a high level, and then turning off the IGBT (QT1) through subsequent circuits.

[0020] Compared with the prior art, this utility model has the following advantages.

[0021] This utility model relates to an isolated IGBT overcurrent protection system. The overcurrent detection and protection of the IGBTs are handled in real-time by hardware. It can instantly shut down the IGBT power transistor in an overcurrent state at any point in time, thereby protecting the hardware device. In other words, it can forcibly shut down the device in a very short time before overcurrent occurs and heat accumulates to a dangerous level, effectively preventing the IGBT from burning out due to overheating. Attached Figure Description

[0022] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. The scope of protection of the present invention is not limited to the following description.

[0023] Figure 1 This is a structural block diagram of the utility model;

[0024] Figure 2 This is a schematic diagram of an isolated IGBT overcurrent protection circuit, which is a specific embodiment of the utility model. Detailed Implementation

[0025] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0026] The terminology used in the embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The singular forms “a,” “the,” and “the” as used in the embodiments of this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0027] Depending on the context, words such as “if” or “suppose” used here can be interpreted as “when”, “in response to determination”, or “in response to detection”.

[0028] For ease of understanding, the embodiments of this disclosure will be described in detail first.

[0029] An isolated IGBT overcurrent protection system, such as Figure 1 As shown, the microcontroller's PWM signal is connected to one end of an isolated IGBT overcurrent protection circuit, and the other end of the isolated IGBT overcurrent protection circuit is connected to an isolated power supply. The isolated IGBT overcurrent protection circuit is used to isolate the rapid turn-on and turn-off of the IGBT, while simultaneously acquiring the current flow when the IGBT is on. It outputs an overcurrent detection signal in an isolated manner, forming an interlock relationship with the microcontroller's PWM signal, thus enabling hardware-level overcurrent shutdown of the IGBT and protecting the circuit and load.

[0030] like Figure 2 As shown, the isolated IGBT overcurrent protection system includes: a first NAND gate chip NAND1, a first NOT gate chip NOT1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a first optocoupler PT1, a second optocoupler PT2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first NPN transistor QN1, a first PNP transistor QP1, a first IGBT transistor QT1, a first diode D1, a second diode D2, a first Zener diode ZD1, a first comparator COM1, and a load.

[0031] Pin 1 of the first NAND gate chip NAND1 is connected to the microcontroller's PWM signal. Pin 2 of the first NAND gate chip NAND1 is connected to pin 4 of the first NOT gate chip NOT1. Pin 3 of the first NAND gate chip NAND1 is connected to ground signal GND. Pin 4 of the first NAND gate chip NAND1 is connected to one end of the second resistor R2. Pin 5 of the first NAND gate chip NAND1 is connected to the +5V power supply and one end of the first resistor R1. The other end of the first resistor R1 is connected to pin 2 of the first optocoupler PT1. The other end of the second resistor R2 is connected to pin 3 of the first optocoupler PT1. Pin 5 of the first optocoupler PT1 is connected to the isolated negative power supply DC-15V. Pin 6 of the first optocoupler PT1 is connected to one end of the third resistor R3. Pin 8 of optocoupler PT1 is connected to the isolation positive power supply DC+15V. The other end of the third resistor R3 is connected to one end of the fifth resistor R5, pin 1 of the first NPN transistor QN1, and pin 1 of the first PNP transistor QP1. The other end of the fifth resistor R5 is connected to pin 2 of the second optocoupler PT2. Pin 2 of the first NPN transistor QN1 is connected to the isolation positive power supply DC+15V and one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the isolation negative power supply DC-15V and pin 2 of the first PNP transistor QP1. Pin 3 of the first NPN transistor QN1 is connected to pin 3 of the first PNP transistor QP1 and one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the sixth resistor R... One end of resistor R6 is connected to the gate (G) terminal of the first IGBT QT1. The collector (C) terminal of the first IGBT QT1 is connected to the positive terminal of the DC bus (+BUS) and the cathode of the first diode D1. The emitter (E) terminal of the first IGBT QT1 is connected to one end of the load, the other end of the sixth resistor R6, and the isolation ground signal DCGND. The other end of the load is connected to the negative terminal of the DC bus (-BUS). The anode of the first diode D1 is connected to one end of the twelfth resistor R12. The other end of the twelfth resistor R12 is connected to signal V2, one end of the third capacitor C3, and pin 3 of the first comparator COM1. The other end of the third capacitor C3 is connected to the isolation ground signal DCGND. Pin 2 of the first comparator COM1 is connected to signal V1 and the eighth resistor R... One end of resistor R8, one end of resistor R11, and one end of resistor R7 are connected. The other end of resistor R8 is connected to the cathode of the first Zener diode ZD1, one end of the second capacitor C2, and one end of resistor R9. The other end of resistor R9 is connected to the isolated positive power supply DC+15V. The other end of resistor R11 is connected to the anode of the first Zener diode ZD1, the other end of the second capacitor C2, and the isolated ground signal DCGND. Pin 1 of the first comparator COM1 is connected to pin 4 of the first comparator COM1, the isolated negative power supply DC-15V, and one end of capacitor C4. Pin 8 of the first comparator COM1 is connected to the isolated positive power supply DC+15V and the other end of capacitor C4.Pin 5 of the first comparator COM1 is connected to pin 6 of the first comparator COM1. Pin 7 of the first comparator COM1 is connected to pin 3 of the second optocoupler PT2 and the cathode of the second diode D2. The anode of the second diode D2 is connected to the other end of the seventh resistor R7. Pin 8 of the second optocoupler PT2 is connected to the +5V power supply and one end of the tenth resistor R10. Pin 6 of the second optocoupler PT2 is connected to the other end of the tenth resistor R10 and pin 2 of the first NOT gate chip NOT1. Pin 5 of the second optocoupler PT2 is connected to the ground signal GND and pin 3 of the first NOT gate chip NOT1. Pin 5 of the first NOT gate chip NOT1 is connected to the +5V power supply.

[0032] In this embodiment, the first NAND gate chip NAND1 and the first NOT gate chip NOT1 are used to prioritize the overcurrent detection signal, thereby shielding the microcontroller's PWM output signal and achieving hardware interlocking during overcurrent. The first resistor R1 limits the current supplied to pin 2 of the first optocoupler PT1 via the +5V power supply. The second resistor R2 limits the current supplied to pin 4 of the first NAND gate chip NAND1 via the output of pin 3 of the first optocoupler PT1. The first optocoupler PT1 provides low-voltage to high-voltage isolation drive through its internal LED, and its internal drive terminal is a push-pull circuit with strong pull-up and pull-down of two MOSFETs, enabling a fast switching process. The third resistor R3 limits the current. The output from pin 6 of the first optocoupler PT1 is current-limited by the third resistor R3, thus simultaneously controlling pins 1 of the first NPN transistor and pin 1 of the first PNP transistor to prevent excessive current from damaging the transistors. The fifth resistor R5 limits current to prevent excessive current from entering pin 2 of the second optocoupler PT2, which could damage the device. The first NPN transistor QN1 and the first PNP transistor QP1 form a totem pole structure, mainly to increase the output capability and quickly control the switching frequency of the first IGBT transistor QT1. The first capacitor C1 filters out high-frequency interference to the isolation positive and negative power supplies during the switching of the first NPN transistor QN1 and the first PNP transistor QP1, stabilizing the voltage of the isolation positive and negative power supplies. The fourth resistor R4 limits current to prevent excessive output current from the totem pole from damaging the first IGBT QT1. The sixth resistor R6 releases the parasitic capacitance on the G and E pins of the first IGBT QT1 when it is turned off, achieving rapid turn-off of the first IGBT QT1. The first IGBT QT1 acts as a switch; when it is on, it transmits the DC bus voltage to the load; when it is off, it stops supplying power to the load. The first diode D1 prevents the high voltage DC at the positive terminal +BUS of the DC bus from entering the input of the first comparator COM1 in series. The twelfth resistor R12 limits current to prevent... The current at pin 3 of the first comparator COM1 is too high; the function of the third capacitor C3 is to filter the acquired voltage and perform a small delay to prevent frequent fluctuations when detecting nearby points, so the capacitance value of the third capacitor C3 should be in the picofarad range; the ninth resistor R9, the eighth resistor R8, and the eleventh resistor R11 are connected in series to perform a voltage divider. The isolated positive power supply DC+15V passes through the ninth resistor R9, the eighth resistor R8, and the eleventh resistor R11 and is finally connected to the isolated ground signal DCGND, forming a loop. According to the voltage divider resistor, the voltage at pin 2 of the first comparator COM1 is the voltage across the eleventh resistor R11, which serves as a standard source for voltage reference;The first Zener diode ZD1 clamps the voltage across resistors R8 and R11. When the voltage across these two resistors exceeds the voltage withstand value of the first Zener diode ZD1, it discharges the isolation ground signal to protect the circuit from overvoltage. The second capacitor C2 filters the voltage across resistors R8 and R11, reducing ripple. The first comparator COM1 performs hardware verification of the overcurrent detection signal. It uses the positive input terminal of pin 2 to confirm the standard source for voltage comparison and determines the change in the input voltage at pin 3, thus outputting a high or low voltage at pin 7. The voltage level; the second diode D2 and the seventh resistor R7 form a hysteresis circuit, which delays the transition of the output level at pin 7 of the first comparator COM1, preventing frequent back-and-forth transitions at the critical point of voltage comparison; the fourth capacitor C4 filters the power supply to the first comparator COM1 to ensure stable operation; the second optocoupler PT2 outputs the current detection signal to the microcontroller control circuit in an isolated manner for logic control, and the tenth resistor R10 pulls up the voltage at pin 6 of the second optocoupler PT2, making its pin default state high.

[0033] The above describes the hardware connection structure of the isolated IGBT overcurrent protection circuit and the function of each hardware component. The following describes the operating logic of this circuit.

[0034] In the isolated IGBT overcurrent protection circuit, under normal operating conditions, the microcontroller's PWM signal is output according to the design frequency. When the microcontroller's PWM signal is high, pin 1 of the first NAND gate NAND1 is high, and pin 2 is high in the default non-overcurrent state. According to the logic characteristics of the NAND gate, pin 4 outputs low. The +5V power supply passes through the first resistor R1 and is connected to pin 2 of the first optocoupler PT1, and is output from pin 3. It then passes through the second resistor R2 and is connected to pin 4 of the first NAND gate NAND1. Because pin 4 of the first NAND gate NAND1 is low at this time, a closed loop is formed, turning on the internal LED of the first optocoupler PT1. Therefore, the output of pin 6 of the first optocoupler PT1 outputs... An isolated positive 15V voltage, through the third resistor R3, is connected to pin 1 of the totem pole formed by the first NPN transistor QN1 and the first PNP transistor QP1. An isolated positive 15V output is pulled up at pin 3, and then connected to the first IGBT QT1 through the fourth resistor R4, turning it on. The positive terminal of the DC bus +BUS is connected to the negative terminal of the DC bus -BUS through the load, forming a loop to power the load. When the first IGBT QT1 is on, the isolated ground signal DCGND passes through the third capacitor C3, the twelfth resistor R12, the first diode D1, the collector (C) terminal of the first IGBT QT1, the emitter (E) terminal of the first IGBT QT1, and finally returns to DCGND, forming a loop. At this time, the voltage of signal V2 is similar to that of the first IGBT QT1. The voltage drop across IGBT QT1 is the same as that across IGBT QT1's collector (C) to emitter (E) terminals. This voltage is connected to the negative input of pin 3 of the first comparator COM1. The isolated positive power supply DC+15V passes through resistors R9, R8, and R11 before returning to the isolated ground signal DCGND. Based on the voltage divider principle, the voltage at pin 2 (positive input) of the first comparator COM1 is the voltage across resistor R11, which is the voltage of signal V1. This is a fixed voltage reference. Under normal operating conditions without overcurrent, the voltage of signal V1 must be higher than the voltage of signal V2. According to the comparator principle, the output of pin 7 of the first comparator COM1 is low. Furthermore, because the first IGBT QT1... At this time, the output of pin 6 of the optocoupler PT1 outputs an isolated positive 15V voltage. This voltage passes through the third resistor R3, the fifth resistor R5, pin 2 of the second optocoupler PT2, and pin 3 of the second optocoupler PT2, finally returning to pin 7 of the first comparator COM1, which is at a low level, forming a loop. This causes the internal LED of the second optocoupler PT2 to conduct, so pin 6 of the second optocoupler PT2 outputs a low level. Pin 6 of the second optocoupler PT2 passes through pin 2 of the first NOT gate chip. According to the characteristics of the NOT gate, pin 4 of the first NOT gate chip outputs a high level, which is connected to the first NAND gate chip NAND1. This, along with pin 2 of the first NAND gate NAND1 (which is at a default high level without overcurrent), forms a closed-loop control logic.When the microcontroller's PWM signal is low, pin 4 of the first NAND gate (NAND1) is high, and pins 2 and 3 of the first optocoupler (PT1) are also high and not conducting. Therefore, the first IGBT (QT1) is off, and its collector (C) and emitter (E) terminals are open. The voltage of signal V2 is 0V, lower than the voltage of signal V1. Pin 7 of the first comparator (COM1) outputs a low level. Since the first optocoupler (PT1) is not conducting, pin 6 of it is also 0V. Therefore, the second optocoupler (PT2) is also not conducting. When the circuit is on, the output of pin 6 of the second optocoupler PT2 is high after being pulled up by the tenth resistor R10. After passing through pin 2 of the first NOT gate, pin 4 of the first NOT gate outputs a low level, which is connected to pin 2 of the first NAND gate chip NAND1. Therefore, pins 1 and 2 of the first NAND gate chip NAND1 are both low. According to the characteristics of the NAND gate, as long as one input port is low, the output is high. The two input voltages are both low to shield against noise interference from the microcontroller's output PWM signal and prevent accidental triggering of the first IGBT QT1.

[0035] During overcurrent operation, the first IGBT QT1 is first driven to turn on according to the logic of normal operation. At the instant of turn-on, because it is in overcurrent operation, the voltage drop of the first IGBT QT1 will rapidly increase beyond the maximum allowable operating voltage. That is, the voltage from the collector (C) to the emitter (E) of the first IGBT QT1 will increase instantaneously, and the voltage of signal V2 will also increase rapidly. At this time, the voltage of signal V1 is less than the voltage of signal V2, and the output of pin 7 of the first comparator COM1 is high. The output of pin 3 of the second optocoupler PT2 connected to it is also high. Since the output of pin 6 of the first optocoupler PT1 is currently outputting an isolated positive 15V voltage, the output of pin 2 of the second optocoupler PT2 is also high. Therefore, the second optocoupler PT2 is not conducting, and the output of pin 6 of the second optocoupler PT2 is at a high level. Pin 2 of the first NOT gate chip NOT1 connected to it is also at a high level. Therefore, pin 4 of the first NOT gate chip NOT1 is at a low level, and pin 2 of the first NAND gate chip NAND1 connected to it is at a low level. According to the characteristics of NAND gates, as long as one input port is at a low level, the output will be high. Since pin 2 of the first NAND gate chip NAND1 is always at a low level, no matter what level the microcontroller PWM signal is, the output of pin 4 of the first NAND gate chip NAND1 is always at a high level, thereby turning off the first IGBT QT1. The hardware interlocking logic protects the load and subsequent circuits from being burned out in time.

[0036] As one embodiment, the first NAND gate chip is SN74LVC1G00DCKR, the first NOT gate chip is SN74LVC1G14DCKR, the first optocoupler is TLP250, the second optocoupler is 6N137, the first NPN transistor is S9013, the first PNP transistor is S9012, the first IGBT is 1KW40N120CS6, the first diode is US1M, the second diode is 1N4148, the first Zener diode is MMSZ5233BT1G, and the first comparator is LM211.

[0037] In this invention, the overcurrent detection and protection of the IGBT are handled by hardware in real time. The IGBT power transistor in an overcurrent state can be shut down instantly at any point in time, thereby protecting the safety of the hardware device. Since both the collector and emitter of the IGBT are high-voltage circuits, the control of the IGBT and the results of overcurrent detection are isolated. This can better avoid high-frequency interference from the high-voltage part of the main circuit to the low-voltage drive control part. High-low voltage isolation of the circuit enables safer and more stable logic control.

[0038] Compared with traditional microcontroller logic control and protection algorithms, this system uses hardware logic chips for priority closed-loop control. The microcontroller only needs to output a single PWM signal, with the overcurrent signal having high priority. AND, OR, and NOT gate logic chips are used for interlocking. When the IGBT is in an overcurrent situation, the IGBT cannot be turned on regardless of whether the microcontroller's PWM signal is high or low. When it returns to normal operation, the PWM signal output by the microcontroller remains unchanged to drive the circuit. This simplifies the algorithm processing, improves the circuit's response speed, and allows for a faster response in overcurrent situations.

[0039] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "preferred embodiment," "detailed description," or "preferred embodiment," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0040] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Therefore, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope defined by the claims of this utility model.

Claims

1. An isolated IGBT overcurrent protection system, characterized in that, Includes a microcontroller, an isolated power supply, and an isolated IGBT overcurrent protection circuit: among which, The microcontroller is used to output PWM signals; The isolated power supply is used to provide isolated positive and negative power supplies; One end of the isolated IGBT overcurrent protection circuit is connected to the PWM signal of the microcontroller, and the other end of the isolated IGBT overcurrent protection circuit is connected to the isolated power supply. The isolated IGBT overcurrent protection circuit is used to realize the isolated driving and overcurrent detection of the IGBT, and to forcibly shut down the IGBT through hardware logic when overcurrent is detected, thereby realizing hardware interlock with the microcontroller PWM signal.

2. The isolated IGBT overcurrent protection system according to claim 1, characterized in that, The isolated IGBT overcurrent protection circuit includes a logic control unit, a drive isolation unit, a totem pole output unit, a current detection unit, a comparison and judgment unit, and a feedback isolation unit. The logic control unit includes a first NAND gate chip and a first NOT gate chip, used to implement hardware interlocking between the overcurrent signal and the PWM signal; the drive isolation unit includes a first optocoupler, used to convert the PWM control signal on the low-voltage side into an isolated drive signal on the high-voltage side; the totem pole output unit includes a first NPN transistor and a first PNP transistor, used to enhance the drive capability to control the fast switching of the IGBT; the current detection unit is used to collect the voltage drop across the IGBT when it is turned on; the comparison and judgment unit includes a first comparator, used to compare the voltage drop across the IGBT with a reference voltage to determine whether there is an overcurrent; the feedback isolation unit includes a second optocoupler, used to isolate and feed back the overcurrent judgment signal to the logic control unit.

3. The isolated IGBT overcurrent protection system according to claim 2, characterized in that, In the logic control unit: the first input terminal of the first NAND gate chip is connected to the PWM signal of the microcontroller; the second input terminal of the first NAND gate chip is connected to the output terminal of the first NOT gate chip; the output terminal of the first NAND gate chip is connected to the input terminal of the first optocoupler through the second resistor; and the input terminal of the first NOT gate chip is connected to the output terminal of the second optocoupler.

4. The isolated IGBT overcurrent protection system according to claim 2, characterized in that, In the drive isolation unit: the anode of the first optocoupler is connected to the low-voltage side power supply through a first resistor, and the cathode of the first optocoupler is connected to the output terminal of the first NAND gate chip through a second resistor; the collector of the first optocoupler is connected to the isolation positive power supply, and the emitter of the first optocoupler is connected to the control terminal of the totem pole output unit through a third resistor.

5. The isolated IGBT overcurrent protection system according to claim 2, characterized in that, In the totem pole output unit: the bases of the first NPN transistor and the first PNP transistor are connected to the output terminal of the drive isolation unit; the collector of the first NPN transistor is connected to the isolation positive power supply, and the collector of the first PNP transistor is connected to the isolation negative power supply; the emitters of the first NPN transistor and the first PNP transistor are connected to the gate of the IGBT through a fourth resistor.

6. The isolated IGBT overcurrent protection system according to claim 5, characterized in that, It also includes a sixth resistor, which is connected in parallel between the gate and emitter of the IGBT to release the gate charge during turn-off and accelerate the IGBT turn-off.

7. The isolated IGBT overcurrent protection system according to claim 2, characterized in that, The current detection unit includes a first diode, a twelfth resistor, and a third capacitor; the cathode of the first diode is connected to the collector of the IGBT, and the anode of the first diode is connected to the negative input terminal of the first comparator through the twelfth resistor; one end of the third capacitor is connected between the twelfth resistor and the negative input terminal of the first comparator, and the other end of the third capacitor is connected to isolation ground.

8. The isolated IGBT overcurrent protection system according to claim 2, characterized in that, The comparison and judgment unit further includes a voltage divider network consisting of an eighth resistor, a ninth resistor, and an eleventh resistor connected in series, and a first Zener diode; the voltage divider network is connected between the isolated positive power supply and the isolated ground, and the positive input terminal of the first comparator is connected between the eighth resistor and the eleventh resistor to obtain a reference voltage; the cathode and anode of the first Zener diode are respectively connected to the two ends of the eighth resistor to clamp the reference voltage.

9. The isolated IGBT overcurrent protection system according to claim 8, characterized in that, The comparison and judgment unit further includes a hysteresis circuit composed of a second diode and a seventh resistor; the cathode of the second diode is connected to the output terminal of the first comparator, and the anode of the second diode is connected to the positive input terminal of the first comparator through the seventh resistor.

10. The isolated IGBT overcurrent protection system according to claim 2, characterized in that, In the feedback isolation unit: the anode of the input terminal of the second optocoupler is connected to the output terminal of the drive isolation unit through the fifth resistor; the cathode of the input terminal of the second optocoupler is connected to the output terminal of the first comparator; the collector of the output terminal of the second optocoupler is connected to the low-voltage side power supply through the tenth resistor; and the emitter of the output terminal of the second optocoupler is connected to the input terminal of the first NOT gate chip.

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