A back-to-back protection ESD structure with a resistive bleed path
By introducing a reverse-connection protection ESD structure with a resistor discharge path into the chip, and using a current-limiting resistor and a Zener diode to discharge ESD current, the problems of complex reverse-connection protection structures and insufficient protection capabilities in existing technologies are solved, and efficient ESD protection of the chip is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANGHAI XINYAN MICROELECTRONICS CO LTD
- Filing Date
- 2025-08-26
- Publication Date
- 2026-07-07
AI Technical Summary
Existing reverse connection protection structures for chips are complex and have limited protection capabilities, and they cannot effectively protect chips when faced with large ESD impacts or high voltage surges.
The reverse connection protection ESD structure adopts a resistor discharge path, which includes two diodes with connected cathodes and a P-type LDMOS transistor. Through the discharge path composed of a current-limiting resistor and a Zener diode, the early discharge of ESD current and reverse connection protection are realized.
It achieves a simple and easy-to-implement reverse connection protection for chips, effectively dissipates ESD current, improves chip reliability and protection capabilities, and prevents metal interconnects from melting.
Smart Images
Figure CN224473656U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of microelectronics technology, specifically to a reverse connection protection ESD structure with a resistor discharge path. Background Technology
[0002] Considering that users might accidentally reverse the power supply ground wire during chip operation, an appropriate reverse connection protection structure needs to be added to the circuit design to improve chip reliability. Reverse connection refers to connecting the chip's high potential VCC to the external power supply's low potential 'GND', and vice versa. This causes parasitic diodes present in the chip's internal Psub and PMOS N-well, or Psub and NMOS source / drain terminals, to conduct forward, generating a large current and potentially burning out the chip. Electrostatic discharge (ESD) also poses a serious threat to the chip's internal circuitry; integrating an ESD module significantly improves chip reliability.
[0003] Commonly used reverse connection structures are relatively complex and have a narrow range of applications. Common ESD protection methods generally have limited capabilities and occupy a large area. The structure described in this article, when faced with large ESD impacts or high-voltage surges, allows the chip to simultaneously provide reverse connection protection and symmetrical high ESD protection by pre-discharging a portion of the high-voltage surge. Utility Model Content
[0004] To help solve the above-mentioned technical problems, this application provides a reverse connection protection ESD structure with a resistor discharge path, adopting the following technical solution:
[0005] A reverse-connection protection ESD structure with a resistive discharge path, comprising:
[0006] The ESD module consists of two diodes with their cathodes connected together. The anodes of the two diodes are connected to the first power supply terminal and the second power supply terminal, respectively. The first power supply terminal is connected to GND, and the second power supply terminal is connected to the power supply VCC.
[0007] The P-type LDMOS transistor M1 has its substrate connected to the second power supply terminal through a first current-limiting resistor, its drain connected to the second power supply terminal, its source connected to the third power supply terminal, and its gate connected between the anode of the Zener transistor and the second current-limiting resistor.
[0008] The P-type LDMOS transistor M2 has its substrate end connected to the source, and the source end connected to the gate of the P-type LDMOS transistor M1 through a Zener diode. The drain end is connected to the second power supply terminal, and the gate of the P-type LDMOS transistor M2 is connected between the cathode of the Zener diode and the source of the P-type LDMOS transistor M2.
[0009] In the case where the first power supply terminal and the second power supply terminal are reversed, the P-type LDMOS transistor M1 is equivalent to a parasitic diode module. The parasitic diode module includes a parasitic diode D1. The anode of the parasitic diode D1 is connected to the third power supply terminal, and the cathode is connected in series with the first current-limiting resistor to form a surge discharge path before the ESD structure is turned on.
[0010] Preferably, the parasitic diode module includes parasitic diode D2 and parasitic diode D3, the cathodes of parasitic diodes D1, D2 and D3 are connected to each other, the anode of parasitic diode D2 is connected to the second power supply terminal, and the anode of parasitic diode D3 is connected to the first power supply terminal.
[0011] Preferably, when the first power supply terminal and the second power supply terminal are reverse connected, the P-type LDMOS transistor M2 is reverse cut off, which is equivalent to the parasitic diode D4. The cathode of the parasitic diode D4 is connected to the cathode of the Zener diode, and the anode is connected to the second power supply terminal.
[0012] Preferably, the P-type LDMOS transistor M2 is connected to the first power supply terminal through a second current-limiting resistor.
[0013] Preferably, the gate of the P-type LDMOS transistor M1 is connected to the anode of the Zener diode, and the gate of the P-type LDMOS transistor M2 is connected to the cathode of the Zener diode.
[0014] Preferably, the gate of the P-type LDMOS transistor M1 is connected to the anode of the Zener diode, and the gate of the P-type LDMOS transistor M2 is connected to the anode of the Zener diode.
[0015] Preferably, the ESD module includes:
[0016] Deep N-well, connected to reference ground.
[0017] The first N-well is located in the deep N-well and connected to the first power supply terminal.
[0018] The second N-well is located within the deep N-well and connected to the second power supply terminal.
[0019] The N-well and deep N-well intersect to form a diode with two connected cathodes.
[0020] In summary, the reverse-connection protection ESD structure with a resistive discharge path proposed in this application has a clear structure that is easy to implement, which is conducive to building and transferring it between different processes. It also has the advantages of low forward conduction voltage, high reverse-connection protection voltage, an additional discharge path before the ESD protection tube is turned on, and fast ESD current discharge. Attached Figure Description
[0021] Figure 1 This is a schematic diagram of the structure of a first embodiment of a reverse connection protection ESD structure with a resistive discharge path according to this application;
[0022] Figure 2 This is a schematic diagram of a second embodiment of a reverse connection protection ESD structure with a resistive discharge path according to this application;
[0023] Figure 3 This is a schematic diagram of the equivalent circuit structure when the first power supply terminal and the second power supply terminal are reversed.
[0024] Figure 4 This is an equivalent cross-sectional view of the P-type LDMOS transistor M1 in the reverse connection state of the first power supply terminal and the second power supply terminal of this application.
[0025] Figure 5 This is a schematic diagram of the ESD junction module of this application. Detailed Implementation
[0026] The present application will be further described below with reference to the accompanying drawings. The structure and principle of the present application are very clear to those skilled in the art. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
[0027] Figure 1 This is a schematic diagram of the first embodiment of a reverse connection protection ESD structure with a resistive discharge path according to this application. Figure 2 This is a schematic diagram of a second embodiment of a reverse connection protection ESD structure with a resistive discharge path according to this application. Figure 3 This is a schematic diagram of the equivalent circuit structure when the first and second power supply terminals are reversed.
[0028] Combination Figures 1 to 3 It is understood that the reverse connection protection ESD structure with a resistive discharge path in this application includes:
[0029] The ESD module consists of two diodes with their cathodes connected together. The anodes of the two diodes are connected to the first power supply terminal and the second power supply terminal, respectively. The first power supply terminal is connected to GND, and the second power supply terminal is connected to the power supply VCC.
[0030] The P-type LDMOS transistor M1 has its substrate connected to the second power supply terminal through the first current-limiting resistor R1, its drain connected to the second power supply terminal, its source connected to the third power supply terminal, and its gate connected between the anode of the Zener transistor and the second current-limiting resistor.
[0031] P-type LDMOS transistor M2 has its substrate connected to its source, and its source connected to the gate of P-type LDMOS transistor M1 via a Zener diode. Its drain is connected to a second power supply terminal. The gate of P-type LDMOS transistor M2 is connected between the cathode of the Zener diode and the source of P-type LDMOS transistor M2. In a first embodiment, the gate of P-type LDMOS transistor M1 is connected to the anode of the Zener diode, and the gate of P-type LDMOS transistor M2 is connected to the cathode of the Zener diode. In a second embodiment, the gate of P-type LDMOS transistor M1 is connected to the anode of the Zener diode, and the gate of P-type LDMOS transistor M2 is connected to the anode of the Zener diode. The structure of the second embodiment only lowers the potential at the gate terminal of M2, and its function is the same as the structure described above.
[0032] In the case where the first power supply terminal and the second power supply terminal are reversed, the P-type LDMOS transistor M1 is equivalent to a parasitic diode module. The parasitic diode module includes a parasitic diode D1. The anode of the parasitic diode D1 is connected to the third power supply terminal, and the cathode is connected in series with the first current-limiting resistor to form a surge discharge path before the ESD structure is turned on.
[0033] The parasitic diode module also includes parasitic diodes D2 and D3. The cathodes of parasitic diodes D1, D2 and D3 are connected to each other. The anode of parasitic diode D2 is connected to the second power supply terminal, and the anode of parasitic diode D3 is connected to the first power supply terminal.
[0034] P-type LDMOS transistor M1 is connected to the first power supply terminal through the second current-limiting resistor R2. When the first power supply terminal and the second power supply terminal are reverse-connected, the P-type LDMOS transistor M2 is reverse-cut off, which is equivalent to parasitic diode D4. The cathode of parasitic diode D4 is connected to the cathode of Zener diode, and the anode is connected to the second power supply terminal.
[0035] Specifically, during normal operation, the drain of M2 increases as VCC increases. The drain terminal of M2 is forward-biased to the N-well parasitic diode, and then through the Zener diode, the potential at point a is stably reduced by about 5V to obtain the potential at point b.
[0036] Because the potential at point b is 5V lower than that at point a, M1 can operate normally. Since M1 and M2 are LDMOS transistors, they have a high voltage withstand capability between the source and drain, but a lower withstand capability between the gate and source. Therefore, Zener protection is needed to prevent the gate voltage of M1 from becoming too high. After M1 operates normally, it obtains an internal voltage Invcc (the third power supply terminal). The voltage difference between Invcc and VCC depends on the on-state voltage drop of M1. The larger the aspect ratio of M1, the smaller the voltage drop, and the closer Invcc is to VCC.
[0037] When the power supply and ground are reversed, the parasitic diodes existing between the Psub and the N-well of the PMOS or between the Psub and the source / drain terminals of the NMOS in the internal circuit of the chip are forward-biased, so the source voltage of M1 is approximately VCC. To distinguish it from the power supply VCC, it is uniformly referred to as VCC1 in all schematic diagrams.
[0038] like Figure 3 As shown, when the power supply and ground are reversed, Psub is at a high potential. The gate (G), base (B), and source (S) terminals of M2 are at high potentials, and the drain (D) terminal is at a low potential. The drain of M2 is reverse-biased and cut off by the parasitic diode D4 of the N-well. Therefore, the branch consisting of VCC, resistor R2, Zener diode, and M2 is closed because D4 does not meet the conduction condition. The gate (G) and source (S) terminals of M1 are at high potentials, and the drain (D) and base (B) terminals are at low potentials. The Psub terminal of M1 is forward-biased and connected to the parasitic diode D3 of the N-well. The source terminal is forward-biased and connected to the parasitic diode D1 of the N-well. The drain terminal is reverse-biased and cut off by the parasitic diode D2 of the N-well. Therefore, the branch consisting of D1, D3, and R1 is conducting. However, due to the presence of R1, the magnitude of the current in the path is limited to prevent the metal connection from melting due to excessive current. R1 can also discharge some of the ESD impact or high-voltage surge through the branch of D1 and resistor R1 before the ESD protection tube is turned on. When the ESD impact completely exceeds the ESD discharge threshold, the ESD protection tube will take over, thereby further improving the reliability of the circuit.
[0039] Figure 4 This is an equivalent cross-sectional view of the P-type LDMOS transistor M1 in the reverse connection state of the first and second power supply terminals according to this application. This figure shows the equivalent cross-sectional view of M1 when the power supply and ground are reversed. Since only the circuitry related to the internal circuitry of the chip needs to be considered, the parasitic diode D3 is ignored, and M1 is equivalent to diodes D1 and D2 connected back-to-back (N-terminal connected). Because the parasitic diode D1 is forward-biased, a current-limiting resistor R1 is connected in series with the N-well of the PMOS transistor to pre-dissipate high-voltage surges and prevent the metal interconnect from melting due to excessive current.
[0040] The power supply VCC is connected to three P+ regions through resistor R2. One P+ region is connected to VCC1, and VCC1 is associated with another P+ region through a deep N-well (shaded area in the diagram). The three P+ regions are connected to diodes D1 and D2 and their associated paths, respectively. The cathode of D1 is connected to the cathode of D3, and the cathode of D2 is connected to the N+ region. The N+ region is grounded through resistor R1. The overall structure is located in the Nwell and Psub regions. During normal operation, VCC is current-limited by R2 and forms the main current path through the P+ region, D2, N+ region, and R1. In reverse connection, VCC1 is at a high potential, D1 and the parasitic diode D3 of the Psub-Nwell are forward-biased, and the current is discharged through the D1-R1 or D3-R1 path. R1 limits the current peak to prevent metal melting, while D2 is reverse-biased to block the reverse current. Under ESD impact, R1 discharges part of the surge in advance. When the voltage exceeds the threshold, the back-to-back ESD module (composed of D1 and the parasitic diode of another LDMOS transistor) is fully turned on to quickly discharge the remaining current. The Zener diode stabilizes the gate potential to prevent overvoltage, achieving dual protection against reverse connection and ESD.
[0041] Figure 5 This is a schematic diagram of the ESD module of this application.
[0042] The ESD module includes:
[0043] Deep N-well, connected to reference ground.
[0044] The first N-well is located in the deep N-well and connected to the first power supply terminal.
[0045] The second N-well is located within the deep N-well and connected to the second power supply terminal.
[0046] The N-well and deep N-well intersect to form a diode with two connected cathodes.
[0047] exist Figure 5 In this configuration, the P-wells (PW) and deep N-wells (DNW) of two P-type LDMOS transistors intersect to form a parasitic diode. Terminals A and B are connected to the power supply and ground, respectively. Specifically, it includes two P-type LDMOS transistors (it should be noted that these are not M1 / M2, but dedicated ESD devices), a P+ region, a P-well (PW), a deep N-well (DNW), and a P-type substrate (Psub). The N-wells and deep N-wells of the two LDMOS transistors intersect to form a back-to-back parasitic diode, with terminal A connected to the positive power supply and terminal B grounded.
[0048] Working principle:
[0049] During normal operation, only one of the two diodes conducts in the forward direction, allowing current to flow in one direction. Regardless of whether the A or B terminals are connected to a power source, the ESD current is quickly discharged through the forward-conducting parasitic diode, while the reverse direction blocks the reverse current, achieving symmetrical protection. The parasitic diode and current-limiting resistor are also involved.
[0050] The principle of parasitic diode formation is existing technology, and is briefly introduced below:
[0051] P-wells (PWs) are formed by P-type impurity implantation and diffusion, while deep N-wells (DNWs) are formed by high-energy ion implantation and deep diffusion processes. The two are in cross contact on a P-type substrate to form a PN junction.
[0052] N-type regions are formed by implanting N-type impurities (such as phosphorus or arsenic) into a P-type silicon substrate, followed by high-temperature annealing and diffusion. This process is completed early in chip manufacturing, providing a foundation for device fabrication. Deep N-type regions are formed using higher-energy ion implantation and deeper diffusion processes. Deep N-wells are typically used for isolation or to build devices with special electrical characteristics.
[0053] When N-wells and deep N-wells are physically intersected or adjacent, the contact surface between the P-type silicon substrate and the N-type region (N-well / deep N-well) forms a depletion region, constituting a PN junction. This structure exhibits unidirectional conductivity, acting as a parasitic diode. The intersecting arrangement gives the PN junction bidirectional conductivity, and the difference in doping concentration between the N-wells and deep N-wells optimizes the diode's breakdown voltage and on-resistance, ensuring rapid ESD current discharge.
Claims
1. A reverse-connection protection ESD structure with a resistive discharge path, characterized in that, include: The ESD module consists of two diodes with their cathodes connected together. The anodes of the two diodes are connected to the first power supply terminal and the second power supply terminal, respectively. The first power supply terminal is connected to GND, and the second power supply terminal is connected to the power supply VCC. The P-type LDMOS transistor M1 has its substrate connected to the second power supply terminal through a first current-limiting resistor, its drain connected to the second power supply terminal, its source connected to the third power supply terminal, and its gate connected between the anode of the Zener diode and the second current-limiting resistor. The P-type LDMOS transistor M2 has its substrate connected to its source, and its source connected to the gate of the P-type LDMOS transistor M1 via a Zener diode. Its drain is connected to the second power supply terminal. The gate of the P-type LDMOS transistor M2 is connected between the gate of the P-type LDMOS transistor M1 and the source of the P-type LDMOS transistor M2. In the case where the first power supply terminal and the second power supply terminal are reversed, the P-type LDMOS transistor M1 is equivalent to a parasitic diode module. The parasitic diode module includes a parasitic diode D1. The anode of the parasitic diode D1 is connected to the third power supply terminal, and the cathode is connected in series with the first current-limiting resistor to form a surge discharge path before the ESD structure is turned on.
2. The reverse connection protection ESD structure with resistive discharge path according to claim 1, characterized in that, The parasitic diode module includes parasitic diode D2 and parasitic diode D3. The cathodes of parasitic diodes D1, D2 and D3 are connected to each other. The anode of parasitic diode D2 is connected to the second power supply terminal, and the anode of parasitic diode D3 is connected to the first power supply terminal.
3. The reverse connection protection ESD structure with resistive discharge path according to claim 2, characterized in that, When the first and second power supply terminals are reverse-connected, the P-type LDMOS transistor M2 is reverse-cut off, which is equivalent to the parasitic diode D4. The cathode of the parasitic diode D4 is connected to the cathode of the Zener diode, and the anode is connected to the second power supply terminal.
4. The reverse connection protection ESD structure with resistive discharge path according to claim 1, characterized in that, P-type LDMOS transistor M2 is connected to the first power supply terminal through the second current-limiting resistor.
5. The reverse connection protection ESD structure with resistive discharge path according to claim 1, characterized in that, The gate of the P-type LDMOS transistor M1 is connected to the anode of the Zener diode, and the gate of the P-type LDMOS transistor M2 is connected to the cathode of the Zener diode.
6. The reverse connection protection ESD structure with resistive discharge path according to claim 1, characterized in that, The gate of the P-type LDMOS transistor M1 is connected to the anode of the Zener diode, and the gate of the P-type LDMOS transistor M2 is connected to the anode of the Zener diode.
7. The reverse connection protection ESD structure with resistive discharge path according to claim 1, characterized in that, The ESD module includes: Deep N-well, connected to reference ground. The first N-well is located in the deep N-well and connected to the first power supply terminal. The second N-well is located in the deep N-well and connected to the second power supply terminal. The N-well and deep N-well intersect to form a diode with two connected cathodes.