A SiC LDMOS device with L-shaped extension layer for drain

Abstract

This invention relates to a SiC LDMOS device with an L-shaped extended layer at the drain, belonging to the field of semiconductor power device technology. The invention primarily addresses the problem of premature breakdown caused by uneven electric field distribution on the surface and near the drain of traditional devices. The technical solution includes setting a ramp gate field plate on a P-type epitaxial layer and wrapping an L-shaped drift region extension layer around the heavily doped N-type drain region, while also incorporating a drain metal field plate structure. The ramp field plate of this invention can uniformly distribute the surface electric field, and the L-shaped drift region extension layer can effectively alleviate the density of transverse and longitudinal electric fields near the drain, shifting the electric field peak deeper into the substrate, resulting in a more uniform bulk electric field distribution. This structure significantly improves the device's breakdown voltage while effectively reducing specific on-resistance, improving transconductance characteristics and current drive capability, and greatly enhancing the device's breakdown voltage reliability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology and relates to a SiC LDMOS device with an L-shaped extension layer at the drain. Background Technology

[0002] In recent years, integrated circuits (ICs) based on silicon carbide (SiC) have developed rapidly. These ICs combine the advantages of silicon carbide power devices and integrated circuit technology, exhibiting excellent performance, reliability, and optimized size and cost. Silicon carbide power ICs are expected to play a core role in high-voltage, high-efficiency applications, particularly in photovoltaic new energy systems, electric vehicles, and industrial motor drives. The development of high-voltage power ICs in silicon carbide will solve the high-temperature, high-power challenges that current silicon (Si) devices cannot meet.

[0003] However, traditional silicon carbide lateral double-diffused metal oxide semiconductor (SiC LDMOS) structures still face problems such as high resistance and uneven electric field distribution when achieving high voltage levels of 1200V and above. These problems limit further improvement in device performance.

[0004] The breakdown voltage (BV) of a laterally diffused metal-oxide-semiconductor (LDMOS) depends on the smaller of the lateral and longitudinal breakdown voltages. Therefore, it is necessary to improve the breakdown voltages in both directions simultaneously to enhance the overall device performance. The lateral breakdown voltage is borne by the P-type base region and the N-type drift region. Two electric field peaks exist at the source and drain ends of the device surface. If the electric field strength exceeds the critical breakdown electric field strength, the device will break down. Under high voltage conditions, silicon carbide (SiC) LDMOS devices are prone to electric field concentration at the gate-drain ends and drift region edges, leading to an increased risk of localized breakdown. Therefore, optimizing the lateral and longitudinal electric field distributions is an important research direction for improving device reliability and withstand voltage. Summary of the Invention

[0005] In view of this, the object of the present invention is to provide a SiC LDMOS device with an L-shaped extension layer at the drain.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A SiC LDMOS device with an L-shaped extension layer at the drain, the SiC LDMOS device comprising: P+ substrate region 12; P-epitaxial layer 11 is located on the upper surface of the P+ substrate region 12; The P-base region 7 and the N-drift region 8 are both located on the upper surface of the P-epitaxial layer 11, and the right side of the P-base region 7 is in contact with the N-drift region 8. Source P+ region 5 and source N+ region 6 are both located inside and above the P-base region 7, and source P+ region 5 and source N+ region 6 are adjacent to each other. The L-shaped drift region extension layer 10 is located on the upper surface of the P-epitaxial layer 11, and its left side is in contact with the N-drift region 8. The doping concentration of the L-shaped drift region extension layer 10 is higher than that of the N-drift region 8. The drain N+ region 9 is located inside and above the L-shaped drift region extension layer 10, and is wrapped by the L-shaped drift region extension layer 10. Source metal 1 is located on top of the device and covers the source P+ region 5 and the source N+ region 6; Gate oxide and field oxide layer 4 covers part of the upper surface of the P-base region 7, the N-drift region 8 and the L-type drift region extension layer 10; A gate polysilicon ramp field plate 2 is located on the upper surface of the gate oxide and field oxide layer 4, with its left end positioned above the P-base region 7 and its right end extending above the N-drift region 8; and The drain metal field plate 3 is located on the upper surface of the drain N+ region 9, and the drain metal field plate 3 extends above the L-shaped drift region extension layer 10.

[0007] Furthermore, the gate oxide and field oxide layer 4 includes a gate oxide layer and a field oxide layer located below the gate, wherein the thickness of the field oxide layer is ten times the thickness of the gate oxide layer.

[0008] Furthermore, the L-shaped drift region extension layer 10 forms a horizontal connection with the N-drift region 8. Junctions are used to generate electric field peaks at the junction interface to uniformly shape the surface electric field.

[0009] Furthermore, the L-shaped drift region extension layer 10 forms a vertical connection with the P-epipolar layer 11. PN The junction is such that the peak value of the longitudinal electric field is located at the interface between the L-shaped drift region extension layer 10 and the P-epipolar layer 11.

[0010] Furthermore, the length of the gate polysilicon ramp field plate 2 is 2. The portion of the drain metal field plate 3 extending above the L-shaped drift region extension layer 10 has a length of 2. .

[0011] Furthermore, the doping concentration of the N-drift region 8 is... The doping concentration of the L-shaped drift region extension layer 10 is .

[0012] Furthermore, the doping concentration of the P-base region 7 is... Furthermore, the junction depth of both the P-base region 7 and the N-drift region 8 is 1.0. .

[0013] Furthermore, the thickness of the P-epipolar layer 11 is 10. The doping concentration is .

[0014] Furthermore, the gate polysilicon ramp field plate 2, through the variation in the thickness of the gate oxide and field oxide layer 4, makes the gate edge electric field borne by the gate oxide and field oxide layer 4.

[0015] The beneficial effects of this invention are as follows: (1) By introducing a polysilicon ramp field plate for the gate, the electric field at the gate end is shared by the field plate oxide layer and the drift region. Increasing the thickness of the field plate oxide layer effectively alleviates the electric field concentration effect at the gate edge, making the surface electric field distribution more uniform. The design of the drain L-shaped extension layer optimizes the lateral and longitudinal electric field distribution near the drain, alleviating the problem of electric field density, thereby significantly improving the breakdown voltage of the device.

[0016] (2) The doping concentration of the drain L-shaped extension layer is higher than that of the drift region, which increases the number of charge carriers participating in conduction, thereby effectively reducing the specific on-resistance of the device. The device has a higher saturation current in the on-state, which means that it can withstand a larger current density and is suitable for high-power applications. Due to the reduction in on-resistance, the conduction loss of the device is also reduced, improving the overall energy conversion efficiency.

[0017] (3) The L-shaped extension layer is used to transfer the vertical electric field peak, which was originally located at the interface between the drift region and the substrate, to the bottom of the extension layer, making the vertical electric field distribution more uniform and improving the reliability of the device. The ramp field plate introduces a new electric field peak on the surface of the drift region, and avoids local premature breakdown through the synergistic effect of multiple peaks. The device exhibits better transconductance characteristics, indicating that its voltage-to-current conversion efficiency is higher and it has better small-signal amplification performance. Under a specific gate voltage, the device has good short-circuit withstand capability, which improves its durability in complex circuit environments.

[0018] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the SiC LDMOS device structure with a ramp field plate and an L-shaped drain extension layer proposed in this invention. Figure 2 This is a diagram illustrating the key parameters of the device of the present invention; Figure 3 A comparison of the transfer characteristic curves of the device of this invention and the conventional SiC LDMOS device; Figure 4 A comparison of the transconductance curves of the device of this invention and a conventional SiC LDMOS device; Figure 5 With gate voltages of 10V and 20V respectively, and VDS scanned from 0 to 200V, the output characteristic curves of the device of the present invention and the conventional SiCLDMOS device during forward conduction are compared. Figure 6 With gate voltages of 10V and 20V respectively, and VDS scanned from 0 to 6V, the output characteristic curves of the device of the present invention and the conventional SiC LDMOS device when the linear region is turned on are compared. Figure 7 A comparison of the on-resistance of the device of the present invention and the conventional SiC LDMOS device under different gate voltages; Figure 8 This is a diagram showing the distribution of the internal electric field of the device under reverse blocking state as a function of the applied voltage. Figure 9 A comparison of the breakdown characteristic curves of the device of this invention and the conventional SiC LDMOS device; Figure 10 The impact ionization rate distribution of the device of this invention and the conventional SiC LDMOS device during breakdown is shown. Figure 11 This is a graph showing the lateral electric field distribution within the device during breakdown. Figure 12 This is a graph showing the lateral electric field distribution within the device when the device breaks down.

[0020] Figure reference numerals: 1. Source metal, 2. Gate polysilicon ramp field plate, 3. Drain metal field plate, 4. Gate oxide and field oxide layer, 5. Source P+ region, 6. Source N+ region, 7. P-base region, 8. N-drift region, 9. Drain N+ region, 10. L-type drift region extension layer, 11. P-epitaxial layer, 12. P+ substrate region. Detailed Implementation

[0021] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0022] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0023] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0024] Example 1: Device Structure and Static Distribution This embodiment combines Figure 1 , Figure 2 Table 1 describes in detail the specific physical structure of a silicon carbide laterally diffused metal oxide semiconductor (SiC) LDMOS device with an L-shaped extension layer at the drain, provided by the present invention.

[0025] The device is constructed from bottom to top on a P+ substrate region 12. A P- epitaxial layer 11 is grown on the upper surface of the P+ substrate region 12, which serves as the main breakdown voltage layer of the device. On top of the P- epitaxial layer 11, a P-base region 7, an N-drift region 8, and an L-type drift region extension layer 10 are formed through processes such as ion implantation.

[0026] P-base region 7 is located on the left side of the device, and its upper part contains source P+ region 5 and source N+ region 6. Among them, source P+ region 5 serves as the diffusion window of P-base region 7, and source N+ region 6 is adjacent to source P+ region 5. The upper surfaces of both are connected to source metal 1, and together they serve as source input terminals.

[0027] The N-drift region 8 is located to the right of the P-base region 7. An L-shaped drift region extension layer 10 is disposed at the right end of the N-drift region 8. This layer contacts the less doped N-drift region 8 on its left side and completely encloses the heavily doped drain N+ region 9. The drain N+ region 9 is located in the upper right corner inside the L-shaped drift region extension layer 10.

[0028] On the device surface, the gate oxide and field oxide layer 4 are located between the active region and the field plate. The gate polysilicon ramp field plate 2 is located on the upper surface of the gate oxide and field oxide layer 4, with its leftmost end above the P-base region 7 and its rightmost end extending above the N-drift region 8. The drain metal field plate 3 is located on the upper surface of the drain, and its extended portion covers the L-type drift region extension layer 10.

[0029] Based on the structural parameters shown in Table 1, the gate oxide thickness Tgox of this device is 0.03. μm The field oxide layer thickness, Tfox, is 0.2. μm The horizontal length of the L-shaped drift zone extension layer 10, Extension 1, is 3.0 mm. μm The vertical depth Textension is 3.0. μm Its doping concentration Nextension is The concentration was significantly higher than that in the N-drift region 8.

[0030] Table 1

[0031] The gate field plate length is 2 μm The drain metal field plate 3, located above the gate oxide and field oxide layer 4, has a length of 2. μm The length (X-axis direction) of the source P+ region 5 below source metal 1 is 0.5. μm The knot depth is 0.2. μm P-type impurity nitrogen (B) was incorporated at a concentration of 1.0 × 10⁻⁶. 19 cm -3The source N+ region is located to the right of the source P+ region, and its length (in the X-axis direction) is 1.0. μm The knot depth is 0.2. μm It incorporates N-type impurity nitrogen (N) at a concentration of 1.0 × 10⁻⁶. 19 cm -3 The junction depths of both P-base region 7 and N-drift region 8 are 1.0. μm P-base region 7 is doped with p-type impurity nitrogen (B) at a concentration of 1.0 × 10⁻⁶. 17 cm -3 The length (X-axis direction) of the N-drift region 8 is 8.5. μm From X=2.5 μm up to X=11 μm The width (Y-axis direction) of the P-epilayer 11 below the N-drift region 8 is 10. μm From Y=1 μm up to Y=11 μm P-type impurity nitrogen (B) was incorporated at a concentration of 3.0 × 10⁻⁶. 15 cm -3 The width (Y-axis direction) of the P+ substrate region 12 below the P- epitaxial layer 11 is 1. μm From Y=11 μm up to Y=12 μm P-type impurity nitrogen (B) was incorporated at a concentration of 1.0 × 10⁻⁶. 19 cm -3 The overall length of the device is 14. μm The overall width (Y-axis direction) is 12. μm .

[0032] The following simulation analysis is performed on the SiC LDMOS device with a ramp field plate and an L-shaped drain extension layer proposed in this embodiment, and compared with the traditional SiC LDMOS device.

[0033] Figure 3 A comparison of the transfer characteristic curves of the device of this invention and the conventional SiC LDMOS device (V) DS =0.1V), the two devices have the same gate oxide and field oxide layer 4 thickness and the same doping concentration in the P-base region 7, resulting in very close threshold voltages. The threshold voltage of a conventional SiC LDMOS device is 7.69V, while the threshold voltage of the device of this invention is 7.81V. From Figure 3 It can be seen that the saturation current of the present invention is significantly greater than that of the traditional SiC LDMOS device when it is turned on. The high saturation current means that the device can withstand a greater current density and power output, and is suitable for high power application scenarios.

[0034] Figure 4To compare the transconductance curves of the device of this invention with those of a conventional SiC LDMOS device, the gate voltage corresponding to the peak transconductance of the device at turn-on is defined as the threshold voltage. This invention increases the peak transconductance from 19.6 μS in the conventional SiC LDMOS device to 22.9 μS, indicating higher voltage-to-current conversion efficiency and better small-signal amplification performance.

[0035] Figure 5 With gate voltages of 10V and 20V respectively, V DS A comparison of the output characteristic curves of the device of this invention and a conventional SiCMOSFET device during forward conduction, from 0 to 200V, shows that the drain current Id of the device increases with increasing voltage after the device is turned on. When V... GS At 10V, this invention exhibits a smaller saturation current, better short-circuit capability, lower short-circuit loss, and improved short-circuit durability. When V GS At 20V, due to the introduction of an L-type drift region extension layer 10 in the N-drift region 8 of this invention, the drift region resistance is significantly reduced, and therefore the saturation current is greater than that of a traditional SiC LDMOS device.

[0036] Figure 6 With gate voltages of 10V and 20V respectively, V DS A comparison of the output characteristic curves of the device of this invention and a conventional SiC LDMOS device is shown from 0 to 6V. The slope of the output characteristic curve in the linear region reflects the on-resistance of the device. When the gate voltage is approximately 1V, the device is in the linear region. The device of this invention has a larger slope in the linear region and a smaller on-resistance than the conventional SiC LDMOS. This is because the presence of the L-shaped drift region extension layer 10 is equivalent to increasing the doping concentration in the drift region, allowing more charge carriers to participate in transport during conduction, resulting in a smaller on-resistance.

[0037] Figure 7 A comparison of the on-resistance of the device of the present invention and that of a conventional SiC LDMOS device at different gate voltages is presented. It can be seen that the on-resistance of the device of the present invention is significantly lower than that of the conventional SiC LDMOS device at all different gate voltages, and the conduction loss is also lower.

[0038] Example 2: Simulation of the forward conduction process and characteristics of the device When the device is in forward conduction mode, the specific process is as follows: Channel turn-on: A forward bias voltage is applied to the gate polysilicon ramp field plate 2. When the voltage exceeds the threshold voltage, inversion occurs on the surface of the P-base region 7, generating an electron conduction channel.

[0039] Current transport: A positive voltage is applied to the drain. Electrons flow out from the source metal 1, pass through the source N+ region 6, cross the inversion channel of the P-base region 7, and successively enter the N-drift region 8 and the L-drift region extension layer 10, and are finally collected by the drain N+ region 9.

[0040] Electric field modulation: During conduction, the field oxide layer below the gate polysilicon ramp field plate 2, which is about ten times thicker than the gate oxide layer, can effectively share part of the electric field and protect the gate oxide layer from high voltage damage.

[0041] Combination Figures 3-7 Simulation results: Figure 3 and Figure 4 The device of this invention exhibits a significantly greater saturation current when turned on than that of the conventional structure, and the transconductance is increased from 19.6 microSiemens to 22.9 microSiemens. Figure 5 and Figure 6 This indicates that when VGS is 20V, the presence of the L-shaped drift region extension layer 10 reduces the drift region resistance, resulting in a higher saturation current and a larger slope in the linear region. Figure 7 The invention visually demonstrates that the specific on-resistance of the device under different gate voltages is significantly lower than that of the traditional structure, effectively reducing conduction losses.

[0042] Figure 8 This diagram illustrates the distribution of the bulk electric field in the reverse blocking state of the device of this invention as a function of the applied voltage. The white solid line represents the depletion region. As the drain voltage increases, the P-base region and the N-drift region deplete each other horizontally, and the N-drift region and the P-type epitaxial layer deplete each other vertically, until the epitaxial layer below the drain region is completely depleted. The depletion layer diffuses to the left of the epitaxial layer towards the source, then the bottom of the epitaxial layer is almost depleted, and finally the depletion layer shrinks towards the P-base. In the N-drift region, the depletion layer depletes from the bottom up and from the left to the right, finally shrinking towards the heavily doped drain until the device breaks down. As can be seen from the figure, before the device breaks down, the P-type epitaxial layer and the N-drift region have already depleted each other, indicating that the total N-type impurity charge Qn in the N-drift region and the total P-type impurity charge Qp in the epitaxial layer are approximately balanced. At the time of breakdown, the N-drift region is completely depleted, the depletion line is close to the drain, and the substrate is almost depleted.

[0043] Figure 9 A comparison of the breakdown characteristic curves of the device of this invention and a conventional SiC LDMOS device (T=300K) shows that the breakdown voltage of the device of this invention is significantly higher than that of the conventional SiC LDMOS device. The breakdown voltage of the conventional structure is 667V, while the breakdown voltage of the improved structure of this invention is 1317V. The breakdown voltage is limited by relatively small values ​​of lateral and longitudinal voltages. The L-shaped drift region extension layer 10 can optimize the lateral and longitudinal electric fields near the drain, greatly improving the lateral and longitudinal breakdown voltages. Therefore, the breakdown voltage is significantly improved compared to the conventional SiC LDMOS device.

[0044] Figure 10The diagram shows the impact ionization rate distribution during breakdown of the device of this invention and a conventional SiC LDMOS device. It can be seen that the conventional SiC LDMOS device is prone to avalanche breakdown at the corner of the N+ region 9 of the drain due to curvature effects, while the device of this invention is prone to avalanche breakdown below and on the sides of the L-shaped drift region extension layer 10. The breakdown location changes from a single point to a surface; during breakdown, multiple regions within the device of this invention simultaneously reach the critical breakdown electric field, resulting in a higher breakdown voltage.

[0045] Example 3: Optimization of Reverse Blocking and Breakdown Mechanisms of Devices When the device is in reverse blocking mode, its operation is as follows: Depletion propagation: As the drain voltage VDS increases, the P-base region 7 and the N-drift region 8 deplete each other laterally, while the N-drift region 8 and the P-epitaxy layer 11 deplete each other longitudinally.

[0046] Electric field peak introduction: The L-shaped drift region extension layer 10 forms an N+N junction with the N-drift region 8 in the horizontal direction, generating a new electric field peak at the junction interface. For example... Figure 11 As shown, this peak value increases the electric field intensity in the middle of the device surface, causing the electric field distribution to change from a single peak to multiple peaks, thereby homogenizing the surface electric field.

[0047] Vertical peak transfer: In the vertical direction, the L-shaped drift region extension layer 10 and the P-epitaxial layer 11 form a PN junction. For example... Figure 12 As shown, the electric field peak originally located at the bottom of the drift region was successfully transferred to the interface between the extended layer and the epitaxial layer, increasing the total charge of the longitudinal withstand layer and improving the longitudinal breakdown voltage.

[0048] Ramp field plate optimization: The gate polysilicon ramp field plate 2 introduces an additional electric field peak on the surface of the drift region. The thickened field oxide layer makes most of the electric field at the gate edge bear the oxide layer, avoiding preferential breakdown at the gate edge.

[0049] Figure 8 The changes in the body electric field as VDS increases from 400V to the breakdown voltage of 1317V are shown in detail. It can be seen that the depletion layer is closely attached to the drain and achieves good charge balance. Figure 9 This shows that the breakdown voltage of the device of the present invention is increased from 667V in the conventional structure to 1317V. Figure 10 Compared with impact ionization rate, traditional devices are prone to avalanche breakdown at the 9-corner point of the drain N+ region due to curvature effect, while the present invention transforms the breakdown location into a surface, which greatly improves the upper limit of withstand voltage.

[0050] Figure 11The diagram shows the lateral electric field distribution within the device during breakdown. In the X-axis direction, the N-drift region 8 and the L-shaped drift region extension layer 10 form a structure similar to a double drift region. The N+N- junction formed by the double regions has an electric field peak in the middle of the device, which reduces the concentration difference between the drain and the drift region, reduces the probability of drain avalanche breakdown, increases the electric field intensity in the middle of the device surface, homogenizes the lateral surface electric field, and improves the lateral breakdown voltage.

[0051] Figure 12 This is a graph showing the lateral electric field distribution within the device during breakdown. Compared to a conventional LDMOS, the depletion region of the L-shaped drift region extension layer 10 below the drain N+ region 9 extends further into the substrate. The L-shaped drift region extension layer 10 can assist in the depletion of the P-type epitaxial layer. The L-shaped drift region extension layer 10 increases the total charge in the drift region. The vertical bulk electric field is affected by the vertical extension layer. After depletion, the total charge in the breakdown layer increases, and the original peak electric field below the drain shifts to the bottom of the buried layer. The vertical electric field becomes more uniform, and the vertical breakdown voltage increases.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A SiC LDMOS device with an L-shaped extension layer at the drain, characterized in that: The SiC LDMOS device includes: P+ substrate region (12); The P-epitaxial layer (11) is located on the upper surface of the P+ substrate region (12); The P-base region (7) and the N-drift region (8) are both located on the upper surface of the P-epitaxial layer (11), and the right side of the P-base region (7) is in contact with the N-drift region (8). The source P+ region (5) and the source N+ region (6) are both located above the interior of the P-base region (7), and the source P+ region (5) and the source N+ region (6) are adjacent to each other. The L-type drift region extension layer (10) is located on the upper surface of the P-epitaxial layer (11), and its left side is in contact with the N-drift region (8). The doping concentration of the L-type drift region extension layer (10) is higher than that of the N-drift region (8). The drain N+ region (9) is located above the interior of the L-shaped drift region extension layer (10) and is wrapped by the L-shaped drift region extension layer (10). Source metal (1) is located on top of the device and covers the source P+ region (5) and the source N+ region (6). A gate oxide and field oxide layer (4) covers part of the upper surface of the P-base region (7), the N-drift region (8) and the L-type drift region extension layer (10); A gate polysilicon ramp field plate (2) is located on the upper surface of the gate oxide and field oxide layer (4), with its left end above the P-base region (7) and its right end extending above the N-drift region (8); and The drain metal field plate (3) is located on the upper surface of the drain N+ region (9) and extends above the L-shaped drift region extension layer (10).

2. The SiC LDMOS device according to claim 1, characterized in that: The gate oxide and field oxide layer (4) includes a gate oxide layer and a field oxide layer located below the gate, wherein the thickness of the field oxide layer is ten times the thickness of the gate oxide layer.

3. The SiC LDMOS device according to claim 1, characterized in that: The L-shaped drift region extension layer (10) forms with the N-drift region (8) in the horizontal direction. Junctions are used to generate electric field peaks at the junction interface to uniformly shape the surface electric field.

4. The SiC LDMOS device according to claim 1, characterized in that: The L-shaped drift region extension layer (10) forms with the P-epipolar layer (11) in the vertical direction. PN The junction is such that the peak value of the longitudinal electric field is located at the interface between the L-shaped drift region extension layer (10) and the P-epipolar layer (11).

5. The SiC LDMOS device according to claim 1, characterized in that: The length of the gate polysilicon ramp field plate (2) is 2. The portion of the drain metal field plate (3) extending above the L-shaped drift region extension layer (10) has a length of 2. .

6. The SiC LDMOS device according to claim 1, characterized in that: The doping concentration of the N-drift region (8) is The doping concentration of the L-shaped drift region extension layer (10) is .

7. The SiC LDMOS device according to claim 1, characterized in that: The doping concentration of the P-base region (7) is Furthermore, the junction depth of both the P-base region (7) and the N-drift region (8) is 1.

0. .

8. The SiC LDMOS device according to claim 1, characterized in that: The thickness of the P-epipolar layer (11) is 10. The doping concentration is .

9. The SiC LDMOS device according to claim 1, characterized in that: The gate polysilicon ramp field plate (2) makes the gate edge electric field borne by the gate oxide and field oxide layer (4) through the change in the thickness of the gate oxide and field oxide layer (4).

Images