A to package semiconductor chip burn-in test fixture

By designing an aging test fixture for TO packaged semiconductor chips, a tight contact between the probe and the chip is achieved using an upper pressure plate and elastic components. This solves the problem of poor contact caused by probe wear and unevenness, ensuring the accuracy of test results and protecting the probe.

CN224480499UActive Publication Date: 2026-07-10DONGGUAN JRS ELECTRONIC TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
DONGGUAN JRS ELECTRONIC TECH CO LTD
Filing Date
2025-06-04
Publication Date
2026-07-10

AI Technical Summary

Technical Problem

During the aging test of TO-packaged semiconductor chips, uneven chip surface and wear of test probes can lead to poor contact between the probes and the chip, affecting the test results.

Method used

A TO-packaged semiconductor chip aging test fixture was designed, including a sealing structure, a support structure, and test components. The chip and the support stage are pressed by an upper pressure plate, so that the test probe is in close contact with the conductive plate. The potential energy is stored and released by the elastic element to ensure good contact between the probe and the chip. The fixing structure and the buffer structure prevent the probe from wearing and deviating.

Benefits of technology

This effectively avoids contact problems caused by uneven chip surfaces and probe wear, ensuring the accuracy of test results and protecting the probes.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model provides a kind of TO encapsulation semiconductor chip ageing test fixture, comprising: placing base, still include: sealing structure, the sealing structure includes cover plate and two upper pressing plates, two the upper pressing plates are fixedly installed on the cover plate;Bearing structure, the bearing structure includes bearing station, placement slot and hole slot, the top of bearing station is equipped with the placement slot, the bottom of bearing station is equipped with multiple hole slots at equal intervals;Multiple test components, multiple test components are installed in the placing base at equal intervals.The utility model provides a kind of TO encapsulation semiconductor chip ageing test fixture, by upper pressing plate pressure movement chip body and bearing station downward, while first elastic piece is pushed up to test probe, so that test probe and conductive plate are closely attached, avoid unevenness on the surface of chip body and the abrasion of test probe cause with conductive plate contact bad, cause influence to test.
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Description

Technical Field

[0001] This utility model relates to the field of TO packaged semiconductor chips, and in particular to an aging test fixture for TO packaged semiconductor chips. Background Technology

[0002] TO-packaged semiconductor chips are semiconductor devices obtained by packaging semiconductor chips in a TO packaging format. Metal, plastic, or ceramic casings provide a physical barrier to protect the semiconductor chip from external factors. After packaging, the chip aging process is accelerated by simulating various stress conditions that might be encountered in actual use, such as high temperature, high humidity, and high pressure, to test its performance and reliability.

[0003] In actual testing, due to manufacturing processes, the chip surface may not be flat, resulting in unevenness. Furthermore, long-term use can cause wear on the top of the test probes, making it difficult for the test probes to make good contact with the chip and affecting the test results.

[0004] Therefore, it is necessary to provide a TO-packaged semiconductor chip aging test fixture to solve the above-mentioned technical problems. Utility Model Content

[0005] This invention provides an aging test fixture for TO packaged semiconductor chips, which solves the problem that long-term use can cause wear on the top of the test probes, making it difficult for the test probes to make good contact with the chip.

[0006] To solve the above-mentioned technical problems, this utility model provides an aging test fixture for TO packaged semiconductor chips, including: a placement base, and a sealing structure, wherein the sealing structure includes a cover plate and two upper pressure plates, the cover plate is rotatably connected to the placement base, and the two upper pressure plates are fixedly installed on the cover plate;

[0007] The support structure includes a support platform, a placement groove, and slots. The support platform is slidably installed in the placement base through a buffer structure. The placement groove is opened on the top of the support platform, and the chip body is placed in the placement groove. Multiple slots are opened at equal intervals on the bottom of the support platform, and the multiple slots are connected to the placement groove.

[0008] Multiple test components are installed at equal intervals within the placement base, and the output ends of the multiple test components are slidably connected within the slots.

[0009] Preferably, the test assembly includes a test base, a test probe, and a first elastic element. The test base is fixedly installed in the placement base, one end of the test probe is slidably installed in the test base, the other end of the test probe is slidably installed in the slot, and the first elastic element is fixedly installed in the test base.

[0010] Preferably, the buffer structure includes a limiting sleeve, a limiting rod, and a second elastic element. The limiting sleeve is fixedly installed at the bottom of the support platform, the limiting rod is fixedly installed inside the placement base, and the second elastic element is fixedly installed at the bottom of the limiting sleeve. Both the limiting sleeve and the second elastic element are sleeved on the limiting rod.

[0011] Preferably, the TO packaged semiconductor chip aging test fixture further includes a fixing structure, which is fixedly installed on one side of the placement base. Two hooks are also fixedly installed on the cover plate, and the two hooks are slidably connected to the fixing structure.

[0012] Preferably, the fixing structure includes a first fixing block, a second fixing block, a threaded rod, a drive knob, and two locking blocks. The first fixing block and the second fixing block are symmetrically installed on one side of the placement base. One end of the threaded rod passes through the first fixing block and is rotatably connected to the second fixing block. The other end of the threaded rod is fixedly installed with the drive knob. The surface of the threaded rod has symmetrically arranged threads. Two locking blocks are threadedly connected to the threaded rod, and the locking blocks are adapted to the locking hooks.

[0013] Preferably, the fixing structure further includes two stops, which are fixedly installed on the threaded rod and located between the two locking blocks.

[0014] Preferably, the sealing structure further includes a protective gasket, which is fixedly mounted on the upper pressure plate.

[0015] Compared with related technologies, the TO packaged semiconductor chip aging test fixture provided by this utility model has the following advantages:

[0016] This invention provides an aging test fixture for TO packaged semiconductor chips. The upper pressure plate continuously presses the chip body and the support platform downward, while the first elastic element pushes the test probe upward, so that the test probe is in close contact with the conductive plate. This avoids unevenness of the chip body surface and wear of the test probe, which could lead to poor contact with the conductive plate and affect the test results. Attached Figure Description

[0017] Figure 1A schematic diagram of a preferred embodiment of the TO-packaged semiconductor chip aging test fixture provided by this utility model;

[0018] Figure 2 This is a schematic diagram of the side sectional structure of this utility model;

[0019] Figure 3 for Figure 2 The enlarged schematic diagram of part A shown below;

[0020] Figure 4 for Figure 2 The enlarged schematic diagram of section B is shown below;

[0021] Figure 5 This is a front view schematic diagram of the fixed structure of this utility model.

[0022] Numbering on the map:

[0023] 1. Place the base;

[0024] 2. Sealing structure; 21. Cover plate; 22. Upper pressure plate; 23. Protective gasket; 24. Clip;

[0025] 3. Supporting structure; 31. Supporting platform; 32. Placement groove; 33. Hole groove;

[0026] 4. Test components; 41. Test base; 42. Test probe; 43. First elastic element;

[0027] 5. Buffer structure; 51. Limiting sleeve; 52. Limiting rod; 53. Second elastic element;

[0028] 6. Fixing structure; 61. First fixing block; 62. Second fixing block; 63. Threaded rod; 64. Drive knob; 65. Locking block; 66. Stop block;

[0029] 7. Chip body. Detailed Implementation

[0030] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0031] First Embodiment

[0032] Please refer to the following: Figure 1 , Figure 2 and Figure 3 A TO packaged semiconductor chip aging test fixture includes a placement base 1 and a sealing structure 2. The sealing structure 2 includes a cover plate 21 and two upper pressure plates 22. The cover plate 21 is rotatably connected to the placement base 1, and the two upper pressure plates 22 are fixedly installed on the cover plate 21.

[0033] The support structure 3 includes a support platform 31, a placement groove 32, and a hole groove 33. The support platform 31 is slidably installed in the placement base 1 through a buffer structure 5. The top of the support platform 31 is provided with the placement groove 32, in which the chip body 7 is placed. The bottom of the support platform 31 is provided with a plurality of hole grooves 33 at equal intervals, and the plurality of hole grooves 33 are connected to the placement groove 32.

[0034] Multiple test components 4 are installed at equal intervals in the placement base 1, and the output ends of the multiple test components 4 are slidably connected in the slot 33;

[0035] During testing, the chip body 7 is placed in the placement slot 32 on the support platform 31, and the cover plate 21 is closed and placed on the placement base 1. At this time, the upper pressure plate 22 contacts the chip body 7 and the support platform 31, pressing the chip body 7 and the support platform 31 downward. The buffer structure 5 limits the support platform 31 to prevent it from shifting. After the chip body 7 moves downward and contacts the output end of the test component 4, it continues to move, causing the output end of the test component 4 to slide downward in the slot 33. This makes the conductive plate of the chip body 7 contact all the output ends of the test components 4, achieving good contact between the test components 4 and the conductive plate, and avoiding any impact on the test results.

[0036] Please refer to the following: Figure 2 and Figure 3 The test component 4 includes a test base 41, a test probe 42, and a first elastic element 43. The test base 41 is fixedly installed in the placement base 1. One end of the test probe 42 is slidably installed in the test base 41, and the other end of the test probe 42 is slidably installed in the slot 33. The first elastic element 43 is fixedly installed in the test base 41.

[0037] When the cover plate 21 is closed, the upper pressure plate 22 presses the chip body 7 and the support stage 31 downwards. The conductive plate of the chip body 7 comes into contact with the test probe 42. The upper pressure plate 22 continues to press the chip body 7 and the support stage 31 downwards, causing the test probe 42 to slide downwards in the slot 33 into the test base 41. The test probe 42 compresses the first elastic element 43. The first elastic element 43 stores elastic potential energy and pushes the test probe 42 upwards, so that the test probe 42 fits tightly with the conductive plate. This avoids poor contact with the conductive plate due to unevenness of the surface of the chip body 7 and wear of the test probe 42, which would affect the test results.

[0038] Please refer to the following: Figure 2 and Figure 4The buffer structure 5 includes a limiting sleeve 51, a limiting rod 52, and a second elastic element 53. The limiting sleeve 51 is fixedly installed at the bottom of the support platform 31, the limiting rod 52 is fixedly installed inside the placement base 1, and the second elastic element 53 is fixedly installed at the bottom of the limiting sleeve 51. Both the limiting sleeve 51 and the second elastic element 53 are sleeved on the limiting rod 52.

[0039] During testing, when the upper pressure plate 22 presses the support platform 31 downward, the support platform 31 drives the limiting sleeve 51 to slide on the limiting rod 52, limiting the support platform 31 and preventing it from shifting. At the same time, the limiting sleeve 51 compresses the second elastic element 53. When the cover plate 21 is opened after the test, the second elastic element 53 releases its elastic potential energy, pushing the support platform 31 upward to its initial position and storing the test probe 42 in the slot 33, thus protecting the test probe 42.

[0040] Second Embodiment

[0041] Please refer to the following: Figure 1 , Figure 2 and Figure 5 The TO packaged semiconductor chip aging test fixture also includes a fixing structure 6, which is fixedly installed on one side of the placement base 1. Two hooks 24 are also fixedly installed on the cover plate 21, and the two hooks 24 are slidably connected to the fixing structure 6.

[0042] When the cover plate 21 is closed, the support platform 31 and the chip body 7 are pressed downwards, and the hook 24 is fixed by the fixing structure 6 to limit the cover plate 21 and prevent the cover plate 21 from opening during the test and affecting the test process.

[0043] Please refer to the following: Figure 1 and Figure 5 The fixing structure 6 includes a first fixing block 61, a second fixing block 62, a threaded rod 63, a drive knob 64, and two locking blocks 65. The first fixing block 61 and the second fixing block 62 are symmetrically installed on one side of the placement base 1. One end of the threaded rod 63 passes through the first fixing block 61 and is rotatably connected to the second fixing block 62. The other end of the threaded rod 63 is fixedly installed with the drive knob 64. The surface of the threaded rod 63 is provided with symmetrically arranged threads. Two locking blocks 65 are threadedly connected to the threaded rod 63, and the locking blocks 65 are adapted to the hook 24.

[0044] After the cover plate 21 is closed, rotating the drive knob 64 drives the threaded rod 63 to rotate, driving the two locking blocks 65 to move into the hooks 24 and engage with them, thus limiting and fixing the cover plate 21. After the test is completed, rotating the drive knob 64 and the threaded rod 63 in the opposite direction separates the two locking blocks 65 from the two hooks 24, thus disengaging the hooks 24 and the cover plate 21 from their limiting position and preventing the cover plate 21 from opening and affecting the test process.

[0045] Please refer to the reference again. Figure 1 and Figure 5 The fixing structure 6 also includes two stops 66, which are fixedly installed on the threaded rod 63 and located between the two locking blocks 65;

[0046] After the test is completed, the drive knob 64 and the threaded rod 63 are rotated in the opposite direction to drive the two locking blocks 65 and the two locking hooks 24 to separate, thereby releasing the limit on the locking hooks 24 and the cover plate 21. After the two locking blocks 65 are separated, the two stops 66 block the locking blocks 65 to prevent the locking blocks 65 from disengaging from the threads on the threaded rod 63.

[0047] Please refer to the following: Figure 1 and Figure 2 The sealing structure 2 further includes a protective gasket 23, which is fixedly installed on the upper pressure plate 22;

[0048] When the cover plate 21 drives the upper pressure plate 22 to close downwards, the upper pressure plate 22 drives the protective pad 23 to make contact with the chip body 7 first, protecting the chip body 7 and preventing damage to the chip body 7 during the test.

[0049] The working principle of the TO-packaged semiconductor chip aging test fixture provided by this utility model is as follows:

[0050] During testing, the chip body 7 is placed in the placement slot 32 on the support platform 31, and the cover plate 21 is closed and placed on the placement base 1. The upper pressure plate 22 presses the chip body 7 and the support platform 31 downwards, and the conductive plate of the chip body 7 contacts the test probe 42. The upper pressure plate 22 continues to press the chip body 7 and the support platform 31 downwards, causing the test probe 42 to slide downwards in the slot 33 into the test base 41. The test probe 42 compresses the first elastic element 43, which stores elastic potential energy and pushes the test probe 42 upwards, so that the test probe 42 is in close contact with the conductive plate. This avoids unevenness on the surface of the chip body 7 and wear of the test probe 42, which could lead to poor contact with the conductive plate and affect the test results. When the test is finished and the cover plate 21 is opened, the second elastic element 53 releases elastic potential energy, pushes the support platform 31 upwards to the initial position, and stores the test probe 42 in the slot 33, protecting the test probe 42. The threaded rod 63 and the locking block 65 are configured so that when the cover plate 21 is closed, the drive knob 64 and the threaded rod 63 are rotated to drive the two locking blocks 65 to move into the hooks 24 and engage with them, thus limiting and fixing the cover plate 21. After the test is completed, the drive knob 64 and the threaded rod 63 are rotated in the opposite direction to separate the two locking blocks 65 from the two hooks 24, thereby releasing the limitation on the hooks 24 and the cover plate 21 and preventing the cover plate 21 from opening during the test.

[0051] The above description is merely an embodiment of this utility model and does not limit the patent scope of this utility model. Any equivalent structural or procedural transformations made based on the content of this utility model specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this utility model.

Claims

1. A TO-packaged semiconductor chip aging test fixture, comprising: The placement base is characterized in that it further includes a sealing structure, the sealing structure comprising a cover plate and two upper pressure plates, the cover plate being rotatably connected to the placement base, and the two upper pressure plates being fixedly installed on the cover plate; The support structure includes a support platform, a placement groove, and slots. The support platform is slidably installed in the placement base through a buffer structure. The placement groove is opened on the top of the support platform, and the chip body is placed in the placement groove. Multiple slots are opened at equal intervals on the bottom of the support platform, and the multiple slots are connected to the placement groove. Multiple test components are installed at equal intervals within the placement base, and the output ends of the multiple test components are slidably connected within the slots.

2. The TO-packaged semiconductor chip aging test fixture according to claim 1, characterized in that, The test assembly includes a test base, a test probe, and a first elastic element. The test base is fixedly installed inside the placement base. One end of the test probe is slidably installed inside the test base, and the other end of the test probe is slidably installed inside the slot. The first elastic element is fixedly installed inside the test base.

3. The TO-packaged semiconductor chip aging test fixture according to claim 1, characterized in that, The buffer structure includes a limiting sleeve, a limiting rod, and a second elastic element. The limiting sleeve is fixedly installed at the bottom of the support platform, the limiting rod is fixedly installed inside the placement base, and the second elastic element is fixedly installed at the bottom of the limiting sleeve. Both the limiting sleeve and the second elastic element are sleeved on the limiting rod.

4. The TO-packaged semiconductor chip aging test fixture according to claim 1, characterized in that, The TO packaged semiconductor chip aging test fixture also includes a fixing structure, which is fixedly installed on one side of the placement base. Two hooks are also fixedly installed on the cover plate, and the two hooks are slidably connected to the fixing structure.

5. The TO-packaged semiconductor chip aging test fixture according to claim 4, characterized in that, The fixing structure includes a first fixing block, a second fixing block, a threaded rod, a drive knob, and two locking blocks. The first fixing block and the second fixing block are symmetrically installed on one side of the placement base. One end of the threaded rod passes through the first fixing block and is rotatably connected to the second fixing block. The other end of the threaded rod is fixedly installed with the drive knob. The surface of the threaded rod has symmetrically arranged threads. Two locking blocks are threadedly connected to the threaded rod, and the locking blocks are adapted to the locking hooks.

6. The TO-packaged semiconductor chip aging test fixture according to claim 5, characterized in that, The fixing structure also includes two stops, which are fixedly installed on the threaded rod and located between the two locking blocks.

7. The TO-packaged semiconductor chip aging test fixture according to claim 1, characterized in that, The sealing structure also includes a protective gasket, which is fixedly installed on the upper pressure plate.