A vertical conductive via structure
By employing a vertical conductive via structure on the printed circuit board, vertical wiring is achieved, solving the problem of insufficient wiring channel resources, reducing the number of circuit board layers and costs, and ensuring the consistency and reliability of transmission lines.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- EMDOOR ELECTRONICS TECH
- Filing Date
- 2025-04-24
- Publication Date
- 2026-07-10
AI Technical Summary
In high-density printed circuit board design, there is a balance between insufficient wiring channel resources and manufacturing cost control. Especially in BGA packaging, the increase in the number of layers in multilayer boards leads to increased costs and processing risks, and the inconsistency of transmission line impedance affects circuit reliability.
The vertical conductive via structure is adopted. By setting multiple trace channels on the substrate, each channel has metallized pads and vertical conductors on both sides, vertical wiring is realized, which reduces the number of board layers and the horizontal space occupied, widens the wiring channels, and ensures the consistency of transmission line impedance.
It effectively reduces the size and number of layers of circuit boards, lowers production costs, reduces the risk of warping, ensures consistent transmission line impedance, and reduces signal reflection.
Smart Images
Figure CN224481841U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of circuit board technology, and more specifically, to a vertical conductive via structure. Background Technology
[0002] As electronic devices continue to evolve towards miniaturization and high performance, the design and manufacturing technology of printed circuit boards (PCBs) has undergone significant technological iterations. Early through-hole technology (THT) components were gradually replaced by surface mount technology (SMT), the number of PCB layers expanded from two to multiple layers, and wiring density moved from conventional conductors to high-density interconnects (HDI). However, with breakthroughs in integrated circuit packaging technology, especially the widespread application of high pin count, fine-pitch ball grid arrays (BGAs) and chip-scale packages (CSPs), the core challenge in PCB design has gradually shifted to balancing insufficient wiring channel resources with manufacturing cost control.
[0003] In ultra-high density PCB design, the physical limitations of routing channels become the primary bottleneck. Taking BGA packages as an example, the number of pins can reach hundreds to thousands, and the pin pitch has been narrowed to 0.4mm or even smaller. Although microvia and via-in-pad technologies can achieve direct escape routing from the pads, these technologies have extremely high requirements for drilling accuracy, material properties, and process stability. At the same time, as pin density increases, the number of layers required for escape routing grows exponentially. For example, a BGA with a pin pitch of 0.5mm typically requires at least 4 to 6 layers to complete the escape of all signal lines; and when the pin pitch is further reduced to 0.3mm, the number of layers required may exceed 8.
[0004] As the number of BGA pins increases, the number of layers required for trace routing also increases, directly leading to higher manufacturing costs. Each additional layer means extra substrate, copper foil, lamination, and drilling processes, significantly increasing costs, and yield decreases with increasing layer count. Furthermore, the difficulty of matching the coefficient of thermal expansion (CTE), controlling interlayer alignment accuracy, and dielectric uniformity in multilayer boards becomes more pronounced, significantly increasing processing risks. In extreme cases, interlayer misalignment can lead to microvia breakage or impedance mismatch, thus affecting the long-term reliability of the circuit. Utility Model Content
[0005] To overcome the shortcomings of existing technologies, this invention provides a vertical conductive via structure, which not only reduces the number of layers on the printed circuit board and lowers production costs, but also effectively reduces the risk of PCB warping during lamination. Furthermore, it widens the wiring channel, eliminating the need for impedance transitions in BGA packages, thereby ensuring impedance consistency of transmission lines and reducing reflections.
[0006] The technical solution of this utility model is as follows: A vertical conductive via structure, comprising:
[0007] substrate body;
[0008] Multiple trace channels are formed on the substrate body. Each trace channel has multiple first metallized pads and multiple vertical conductors on both sides. Each vertical conductor and each first metallized pad are configured in a one-to-one correspondence. The first metallized pads are connected to the horizontal traces of the inner layer of the substrate body through the vertical conductors.
[0009] Furthermore, the trace channel includes a metallized strip hole, a second metallized pad surrounding the metallized strip hole, and a plurality of non-metallized circular holes located within the metallized strip hole. Each non-metallized circular hole has a trace ban area corresponding to its outer periphery, and the first metallized pad is located between two adjacent trace ban areas.
[0010] Furthermore, the multiple wiring channels are arranged at equal intervals, and the center-to-center distance between two adjacent wiring channels is 2mm.
[0011] Furthermore, the plurality of non-metallic circular holes are arranged at equal intervals, and the center-to-center distance between two adjacent non-metallic circular holes is 1 mm.
[0012] Furthermore, the length of the metallized strip hole is 5.254 mm, and the width of the metallized strip hole is 0.254 mm.
[0013] Furthermore, the outer contour of the second metallized pad is elongated, the length of the second metallized pad is 5.508 mm, and the width of the second metallized pad is 0.508 mm.
[0014] Furthermore, the diameter of the non-metallized circular hole is 0.559 mm.
[0015] Furthermore, the diameter of the wiring ban zone is 0.813 mm.
[0016] The advantages of this utility model according to the above solution are as follows: This utility model provides a vertical conductive via structure, including a substrate body and multiple trace channels formed on the substrate body. Each trace channel has multiple first metallized pads and multiple vertical conductors on both sides. Each vertical conductor and each first metallized pad are arranged in a one-to-one correspondence. The first metallized pads are connected to the horizontal traces of the inner layer of the substrate body through the vertical conductors. This design allows for vertical wiring in the board layer stack. The space between two adjacent trace channels can accommodate multiple horizontal traces, thereby increasing the wiring density and effectively reducing the size and number of layers of the circuit board, thus reducing manufacturing costs. In addition, it can widen the wiring channels, so that traces in BGA packages do not need impedance switching, thereby ensuring the consistency of transmission line impedance and reducing reflections. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A schematic diagram of the fabricated metallized strip hole;
[0019] Figure 2 A schematic diagram showing how to place the fabricated metallized vias between two rows of BGA pads;
[0020] Figure 3 This is a schematic diagram showing the metal block segmentation achieved on a metallized strip hole;
[0021] Figure 4 A schematic diagram showing the placement of vertical conductors on segmented metal blocks;
[0022] Figure 5 A schematic diagram of the completed vertical conductive structure;
[0023] Figure 6 This is a schematic diagram of a BGA device layer;
[0024] Figure 7 A planar schematic diagram showing the effect of the inner layer wiring flare-out;
[0025] Figure 8 This is a 3D schematic diagram showing the effect of the inner layer wiring.
[0026] In the figure, 1 is the substrate body; 2 is the trace channel; 21 is the metallized strip hole; 22 is the second metallized pad; 23 is the non-metallized circular hole; 24 is the trace keepout area; 3 is the first metallized pad; 4 is the vertical conductor; 5 is the horizontal trace; D is the center-to-center distance between two adjacent trace channels; L1 is the length of the metallized strip hole; W1 is the width of the metallized strip hole; L2 is the length of the second metallized pad; W2 is the width of the second metallized pad; d1 is the diameter of the non-metallized circular hole; d2 is the diameter of the trace keepout area. Detailed Implementation
[0027] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following detailed description of the embodiments and the accompanying drawings are used to illustrate the principles of the present invention by way of example, but should not be used to limit the scope of the present invention, that is, the present invention is not limited to the described embodiments.
[0028] To better understand this utility model, the following description, in conjunction with the accompanying drawings and embodiments, will further illustrate the present utility model:
[0029] See Figures 1-8 As shown, the present invention provides a vertical conductive via structure, including a substrate body 1 and a plurality of trace channels 2 formed on the substrate body 1. Each trace channel 2 is provided with a plurality of first metallized pads 3 and a plurality of vertical conductors 4 on both sides. Each vertical conductor 4 and each first metallized pad 3 are provided in a one-to-one correspondence. The first metallized pads 3 are connected to the horizontal traces 5 of the inner layer of the substrate body 1 through the vertical conductors 4.
[0030] The vertical conductive via structure provided in this embodiment of the invention achieves direct interconnection between the vertical conductor 4 and the horizontal trace 5 by setting corresponding first metallized pads 3 and vertical conductors 4 on both sides of the trace channel 2. The vertical conductor 4 adopts a vertical through-hole design, which can form an independent conductive channel in the board stacking direction. Compared with the traditional through-hole that requires lateral space, it effectively releases the horizontal wiring area between adjacent trace channels 2, thereby improving the vertical dimension utilization of the signal transmission path in the multilayer board, reducing the need to increase the number of PCB layers to meet wiring density, and effectively reducing the number of PCB layers under the same wiring complexity, significantly reducing material costs and the warpage risk of the lamination process.
[0031] It is worth mentioning that the vertical conductive via structure provided in this embodiment of the invention frees up horizontal wiring space, widening the wiring channel to 1.5 to 2 times that of traditional designs. This allows for thicker traces, which helps reduce signal loss. Furthermore, the widened wiring channel eliminates the need for impedance switching in BGA packages, ensuring consistent transmission line impedance and reducing reflections.
[0032] Specifically, the present invention provides a vertical conductive via structure that allows vertical wiring in board stacking. Multiple horizontal traces 5 can be laid in the space between two adjacent trace channels 2, thereby increasing the wiring density and effectively reducing the size and number of layers of the circuit board, thus reducing manufacturing costs.
[0033] Preferably, the trace channel 2 includes a metallized strip hole 21, a second metallized pad 22 surrounding the metallized strip hole 21, and a plurality of non-metallized circular holes 23 located within the metallized strip hole 21. Each non-metallized circular hole 23 has a trace blocking area 24 corresponding to its outer periphery, and the first metallized pad 3 is located between two adjacent trace blocking areas 24.
[0034] In this embodiment, multiple routing channels 2 are arranged at equal intervals, and the center-to-center distance between two adjacent routing channels 2 is 2mm.
[0035] Specifically, multiple non-metallic circular holes 23 are arranged at equal intervals, and the center-to-center distance D between two adjacent non-metallic circular holes 23 is 1 mm.
[0036] Specifically, the length L1 of the metallized strip hole 21 is 5.254 mm, and the width W1 of the metallized strip hole 21 is 0.254 mm.
[0037] Specifically, the outer contour of the second metallized pad 22 is elongated, the length L2 of the second metallized pad 22 is 5.508mm, and the width W2 of the second metallized pad 22 is 0.508mm.
[0038] Specifically, the diameter d1 of the non-metallized circular hole 23 is 0.559 mm.
[0039] Specifically, the diameter d2 of the no-cable zone 24 is 0.813mm.
[0040] To further illustrate this point, this embodiment also provides the fabrication process of the vertical conductive via structure, as detailed below:
[0041] Taking a 1.0mm BGA as an example, firstly, a metallized slot 21 is fabricated on the PCB board. The length L1 of the metallized slot 21 is 5.254mm, and the width W1 of the metallized slot 21 is 0.254mm. A second metallized pad 22 is then provided around the metallized slot 21, with a length L2 of 5.508mm and a width W2 of 0.508mm. (The text repeats itself here.) Figure 1 As shown.
[0042] Next, the fabricated metallized via 21 is placed between two rows of BGA pads (the first metallized pad 3 in a ball grid array (BGA) chip design), as shown. Figure 2 As shown.
[0043] Then, a non-metallized circular hole 23 is drilled every 1 mm on the metallized strip hole 21 to achieve the division of the metal block, such as... Figure 3 As shown.
[0044] Vertical conductors 4 are placed on the segmented metal blocks to facilitate the routing of wires and the establishment of connections, such as... Figure 4 As shown.
[0045] The completed vertical conductive structure is as follows: Figure 5 As shown.
[0046] It should be noted that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product is usually placed in during use, or the orientation or positional relationship that is commonly understood by those skilled in the art, or the orientation or positional relationship that the product is usually placed in during use. It is only for the purpose of facilitating the description of this application and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application.
[0047] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
[0048] The present utility model patent has been described above with reference to the accompanying drawings. Obviously, the implementation of the present utility model patent is not limited to the above-described manner. Any improvements made by adopting the inventive concept and technical solution of the present utility model patent, or the direct application of the inventive concept and technical solution of the present utility model patent to other occasions without modification, are all within the protection scope of the present utility model.
Claims
1. A vertical conductive via structure, characterized in that, include: Substrate body(1); Multiple trace channels (2) are formed on the substrate body (1). Each trace channel (2) has multiple first metallized pads (3) and multiple vertical conductors (4) on both sides. Each vertical conductor (4) and each first metallized pad (3) are arranged in a one-to-one correspondence. The first metallized pad (3) is connected to the horizontal traces (5) of the inner layer of the substrate body (1) through the vertical conductor (4).
2. The vertical conductive via structure as described in claim 1, characterized in that: The trace channel (2) includes a metallized strip hole (21), a second metallized pad (22) surrounding the metallized strip hole (21), and a plurality of non-metallized circular holes (23) located within the metallized strip hole (21). Each non-metallized circular hole (23) has a corresponding trace blocking area (24) on its outer periphery. The first metallized pad (3) is located between two adjacent trace blocking areas (24).
3. The vertical conductive via structure as described in claim 1, characterized in that: Multiple wiring channels (2) are arranged at equal intervals, and the center-to-center distance between two adjacent wiring channels (2) is 2 mm.
4. The vertical conductive via structure as described in claim 2, characterized in that: The multiple non-metallized circular holes (23) are arranged at equal intervals, and the center distance between two adjacent non-metallized circular holes (23) is 1 mm.
5. A vertical conductive via structure as described in claim 2, characterized in that: The length of the metallized strip hole (21) is 5.254 mm, and the width of the metallized strip hole (21) is 0.254 mm.
6. The vertical conductive via structure as described in claim 2, characterized in that: The outer contour of the second metallized pad (22) is elongated, the length of the second metallized pad (22) is 5.508mm, and the width of the second metallized pad (22) is 0.508mm.
7. A vertical conductive via structure as described in claim 2, characterized in that: The diameter of the non-metallized circular hole (23) is 0.559 mm.
8. A vertical conductive via structure as described in claim 2, characterized in that: The diameter of the wiring ban zone (24) is 0.813 mm.