Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device includes a substrate, a first pad electrode on the substrate, a second pad electrode on the substrate spaced apart from the first pad electrode, a light emitting element including a first electrode connected to the first pad electrode and a second electrode connected to the second pad electrode, a first power line on the substrate spaced apart from the first pad electrode, connected to a first side of the second pad electrode, and configured to receive a first source voltage, and a pad light blocking pattern superposed with a first gap between the first pad electrode and the first power line and a second gap between the second pad electrode and the first power line. Accordingly, it is possible to improve a phenomenon in which a line and a device identifier on a rear surface of the substrate are visually recognized.

Description

Technical Field

[0001] One or more embodiments of this disclosure relate to a display device, a splicing display device including the display device, and an electronic device including the display device. Background Technology

[0002] With the development of the information society, the demand for display devices used to display images has increased and diversified. Display devices can be flat panel display devices such as liquid crystal displays (LCDs), field emission displays (FEDs), or light-emitting displays (LEDs). Light-emitting display devices can include organic light-emitting display devices or light-emitting diode display devices. Organic light-emitting display devices include organic light-emitting diode (OLED) elements as light-emitting elements, while light-emitting diode display devices include inorganic light-emitting diode elements (such as light-emitting diodes (LEDs)) as light-emitting elements.

[0003] A display device includes a display area with pixels for displaying images and a non-display area (or bezel area) surrounding the display area and having lines for driving the pixels. Recently, bezel-less display devices have been released to maximize the area of ​​the display area. Therefore, there is an increasing demand for display devices that can reduce or completely eliminate the non-display area by connecting lines on the side and rear surfaces of a substrate to a circuit board on the rear surface of the substrate. However, light from the display area directed to the rear surface of the substrate is reflected from the lines and device identifiers on the rear surface of the substrate. Therefore, the lines and device identifiers on the rear surface of the substrate are visually identifiable. Utility Model Content

[0004] The aspects and features of embodiments of this disclosure provide a display device capable of preventing lines and device identifiers disposed on the rear surface of a substrate from being seen.

[0005] However, this disclosure is not limited thereto. The above and other embodiments of this disclosure will become more apparent to those skilled in the art from the detailed description of this disclosure given below.

[0006] According to one or more embodiments of the present disclosure, a display device is provided, the display device comprising: a substrate; a first pad electrode on the substrate; a second pad electrode on the substrate spaced apart from the first pad electrode; a light-emitting element including a first electrode connected to the first pad electrode and a second electrode connected to the second pad electrode; a first electric field line on the substrate spaced apart from the first pad electrode, connected to a first side of the second pad electrode, and configured to receive a first source voltage; and a light-blocking pattern superimposed on a first gap between the first pad electrode and the first electric field line and a second gap between the second pad electrode and the first electric field line.

[0007] The display device may also include a second power line, which is superimposed on a third gap between the first pad electrode and the second pad electrode, and is configured to receive a second source voltage.

[0008] The display device may also include a light-blocking pattern, which is superimposed on the light-shielding pattern in the thickness direction of the substrate.

[0009] The area of ​​the lower light blocking pattern can be larger than the area of ​​the pad light blocking pattern.

[0010] The thickness of the lower light blocking pattern can be less than the thickness of the pad light blocking pattern.

[0011] The light-blocking pattern may include a first light-blocking pattern superimposed on the first gap and a second light-blocking pattern superimposed on the second gap and spaced apart from the first light-blocking pattern.

[0012] The display device may also include a second power line configured to receive a second source voltage.

[0013] The second electric field line is superimposed on the third gap between the first pad electrode and the second pad electrode.

[0014] The minimum distance between the first light-blocking pattern and the second light-blocking pattern in one direction can be greater than the length of the third gap in that direction.

[0015] The first pad electrode, the second pad electrode, and the first electric field line may comprise the same material.

[0016] The second pad electrode and the first electric field line can be formed integrally with each other.

[0017] According to one or more embodiments of the present disclosure, a display device is provided, the display device comprising: a substrate; a first pad electrode on the substrate; a second pad electrode on the substrate spaced apart from the first pad electrode; a light-emitting element including a first electrode connected to the first pad electrode and a second electrode connected to the second pad electrode; a first electric field line on the substrate spaced apart from the first pad electrode, connected to a first side of the second pad electrode, and configured to receive a first source voltage; and a lower light-blocking pattern superimposed on a first gap between the first pad electrode and the first electric field line and a second gap between the second pad electrode and the first electric field line.

[0018] The thickness of the light-blocking pattern can be 3,000 Å or greater.

[0019] The display device may further include an active layer of a thin-film transistor on a substrate, a first insulating film on the active layer of the thin-film transistor, a gate electrode of the thin-film transistor on the first insulating film and stacked with the active layer of the thin-film transistor in the thickness direction of the substrate, and a second insulating film on the gate electrode of the thin-film transistor.

[0020] The light-blocking pattern can be on the substrate and the active layer of the thin-film transistor. The display device may also include a third insulating film between the light-blocking pattern and the active layer of the thin-film transistor.

[0021] The first pad electrode and the second pad electrode can be on the second insulating film.

[0022] According to one or more embodiments of this disclosure, a splicing display device is provided, the splicing display device including a plurality of display devices and seams between the plurality of display devices. One of the plurality of display devices includes: a substrate; a first pad electrode on a first surface of the substrate; a second pad electrode on the substrate spaced apart from the first pad electrode; a light-emitting element including a first electrode connected to the first pad electrode and a second electrode connected to the second pad electrode; a first electric field line on the substrate spaced apart from the first pad electrode, connected to a first side of the second pad electrode, and configured to receive a first source voltage; and a light-blocking pattern superimposed on a first gap between the first pad electrode and the first electric field line and a second gap between the second pad electrode and the first electric field line.

[0023] The substrate may include glass.

[0024] The display device may further include: a side surface line on a side surface between a first surface of the substrate and a second surface opposite to the first surface; a rear surface line and a device identifier on the second surface of the substrate; and a flexible film connected to the rear surface line by a conductive adhesive member.

[0025] Multiple display devices can be arranged in a matrix along M rows and N columns.

[0026] An electronic device includes a display device, the display device comprising: a substrate; a first pad electrode on the substrate; a second pad electrode on the substrate spaced apart from the first pad electrode; a light-emitting element including a first electrode connected to the first pad electrode and a second electrode connected to the second pad electrode; a first electric field line on the substrate spaced apart from the first pad electrode, connected to a first side of the second pad electrode, and configured to receive a first source voltage; a light-blocking pattern superimposed on a first gap between the first pad electrode and the first electric field line and a second gap between the second pad electrode and the first electric field line; and a lower light-blocking pattern superimposed on the light-blocking pattern in the thickness direction of the substrate.

[0027] Electronic devices include televisions, laptops, monitors, billboards, Internet of Things (IoT) devices, mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, or ultra-mobile PCs (UMPCs).

[0028] According to the foregoing and other embodiments of this disclosure, by arranging the light-blocking pattern and the first electric field lines to overlap with the gap formed around the pad electrode, light emitted from the light-emitting element is not reflected from the lines and device identifiers on the rear surface of the display panel through the gap. Therefore, the visual recognition of lines and device identifiers on the rear surface of the substrate can be improved. Attached Figure Description

[0029] The above and other embodiments and features of this disclosure will become more apparent from the description of embodiments with reference to the accompanying drawings, in which:

[0030] Figure 1 and Figure 2 This is a perspective view showing a display device according to one or more embodiments;

[0031] Figure 3 It is a layout diagram showing the first to third sub-pixels of the pixels of a display device according to one or more embodiments;

[0032] Figure 4 This is a block diagram illustrating a display device according to one or more embodiments;

[0033] Figure 5 This is an equivalent circuit diagram showing the first sub-pixel according to one or more embodiments;

[0034] Figure 6 It is a layout diagram showing a first pad (or "pad") electrode, a second pad electrode, a third electric field line and a lower light blocking pattern of a first sub-pixel according to one or more embodiments;

[0035] Figure 7 It shows along Figure 6 A cross-sectional view of an example display panel, taken by line I1-I1';

[0036] Figure 8 It is a layout diagram showing a first pad electrode, a second pad electrode, a first electric field line, a third electric field line, and a pad light blocking pattern of a first sub-pixel according to one or more embodiments;

[0037] Figure 9 It shows along Figure 8 A cross-sectional view of an example display panel, taken by line I2-I2';

[0038] Figure 10 It shows along Figure 8 A cross-sectional view of an example display panel, taken by line I3-I3';

[0039] Figure 11 It shows along Figure 8 A cross-sectional view of an example display panel, taken by line I4-I4';

[0040] Figure 12 It is a layout diagram showing a first pad electrode, a second pad electrode, a first electric field line, a third electric field line, a first pad light blocking pattern, and a second pad light blocking pattern of a first sub-pixel according to one or more embodiments;

[0041] Figure 13 It shows along Figure 12 A cross-sectional view of an example display panel taken by line I6-I6';

[0042] Figure 14 It shows along Figure 12 A cross-sectional view of an example display panel, taken by line I7-I7';

[0043] Figure 15 This is a perspective view showing a splicing display device including multiple display devices according to one or more embodiments;

[0044] Figure 16 It is shown in detail Figure 15 A magnified layout diagram of region Y; and

[0045] Figure 17 It shows along Figure 16 A cross-sectional view of an example of a splicing display device, taken from line N-N'. Detailed Implementation

[0046] The aspects and features of the embodiments of this disclosure, as well as methods of implementing them, can be more readily understood by referring to the detailed description of the embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments may be embodied in various different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of this disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are not essential for a full understanding of the aspects and features of this disclosure by those skilled in the art may not be described.

[0047] Unless otherwise indicated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description, and therefore their description will not be repeated. Furthermore, portions unrelated to the description of one or more embodiments may be omitted to make the description clear.

[0048] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity. Additionally, crosshairs and / or shading are typically used in the drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, scale, commonalities between the elements shown, and / or any other characteristics, properties, or characteristics of the elements.

[0049] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of examples and / or intermediate structures. Therefore, variations in the illustrated shapes will be expected due to, for example, manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes shown in the region, but rather include shape deviations caused, for example, by manufacturing processes.

[0050] For example, an injection region shown as rectangular may have circular or curved features at its edges and / or an injection concentration gradient, rather than a binary change from an injection region to a non-injection region. Similarly, a buried region formed by injection may result in some injection in the area between the buried region and the surface through which the injection occurs. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device, nor are they intended to be limiting. Furthermore, as those skilled in the art will recognize, the described embodiments can be modified in various different ways, all without departing from the scope of this disclosure.

[0051] In the detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the various embodiments. However, it will be apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0052] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” and / or “upper” may be used herein to describe the relationship of one element or feature to another element(s) as shown in the figures. It will be understood that, in addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as “below” or “under” or “below” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can cover both upper and lower orientations. The device may be oriented additionally (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when a first part is described as being arranged “above” a second part, this means that the first part is arranged on the upper or lower side (but not limited to the upper side) of the second part based on the direction of gravity.

[0053] Furthermore, in this specification, the phrase "in a plane" or "in a plan view" refers to the target portion viewed from above, and the phrase "in a cross-section" refers to the cross-section formed by vertically cutting the target portion viewed from the side.

[0054] It will be understood that when an element, layer, region, and / or component is referred to as "formed on," "on," "connected to," or "bonded to" another element, layer, region, or component, it can be directly formed on, directly on, directly connected to, or directly bonded to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly bonded to the other element, layer, region, or component, such that one or more intermediary elements, layers, regions, or components may be present. For example, when a layer, region, or component is referred to as "electrically connected" or "electrically bonded" to another layer, region, or component, it can be directly electrically connected to or directly electrically bonded to the other layer, region, or component, or an intermediary layer, region, or component may be present. However, "directly connected / directly bonded" means that one component is directly connected to or bonded to another component without an intermediary component. Similarly, other expressions describing relationships between components, such as "between," "immediately between," "adjacent to," and "directly adjacent to," can be interpreted in a similar way. Additionally, it will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0055] For the purposes of this disclosure, expressions such as “at least one of…”, “one of…”, and “selected from…” modify the entire column of elements when they follow or precede a column of elements, without modifying any individual element in that column. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as XYZ, XY, YZ, and XZ) or any variation thereof. Similarly, expressions such as “at least one of A and B” can include A, B, or A and B. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, expressions such as “A and / or B” can include A, B, or A and B. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure”.

[0056] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the scope of this disclosure, the first element, first component, first region, first layer, or first portion described below may be referred to as a second element, second component, second region, second layer, or second portion.

[0057] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0058] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are also intended to include the plural forms. It will also be understood that when the terms “comprising,” “having,” “including,” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0059] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to explain the inherent biases of measured or calculated values ​​that will be recognized by one of ordinary skill in the art. As used herein, “about” or “approximately” includes the stated value and refers to an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.”

[0060] When one or more embodiments can be implemented differently, a particular process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described sequence.

[0061] Furthermore, any numerical range disclosed and / or described herein is intended to include all subranges containing the same numerical precision within the described range. For example, the range "1.0 to 10.0" is intended to include all subranges between the described minimum value of 1.0 and the described maximum value of 10.0 (and including both the described minimum value of 1.0 and the described maximum value of 10.0), such as having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, as exemplified by 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to modify this specification and the claims to expressly describe any subranges contained within the ranges expressly described herein. All such ranges are intended to be inherently described in this specification such that any modification to expressly describe any such subrange will be deemed acceptable.

[0062] Electronic or electrical devices and / or any other related devices or components according to one or more embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed on an integrated circuit (IC) chip or on a separate IC chip. Furthermore, various components of these devices can be implemented on a flexible printed circuit film, tape-on-a-carrier package (TCP), printed circuit board (PCB), or formed on a substrate.

[0063] Furthermore, the various components of these devices can be processes or threads that execute computer program instructions and interact with other system components to perform the various functions described herein, running on one or more processors in one or more computing devices. The computer program instructions are stored in memory, which can be implemented in a computing device using standard memory devices, such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Moreover, those skilled in the art will recognize that, without departing from the scope of this disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0064] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent, for example, with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0065] It will be understood by those skilled in the art that, in view of the whole of this disclosure, various suitable features of the various embodiments of this disclosure may be combined in part or in whole or in combination with each other, and may be technically interlocked and operated in various suitable ways, and unless otherwise indicated or implied, the various embodiments may be implemented independently or in combination with each other in any suitable manner.

[0066] Figure 1 and Figure 2 This is a perspective view showing a display device according to one or more embodiments.

[0067] Reference Figure 1 and Figure 2 The display device 10 according to one or more embodiments is a device for displaying moving images and / or still images, and can be used as a display screen for various products (such as televisions, laptops, monitors, billboards and / or Internet of Things (IoT) devices) and portable electronic devices (such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-books, portable multimedia players (PMPs), navigation devices and / or ultra-mobile PCs (UMPCs)).

[0068] The display device 10 according to one or more embodiments may include a display panel 100, a first circuit board 200, and a source driver 300.

[0069] The display panel 100 may include a substrate SUB, a first rear surface fan-out line BFL1, a second rear surface fan-out line BFL2, a plurality of pixels PX, a plurality of first side surface lines SIL1, a plurality of second side surface lines SIL2, and a plurality of device identifiers DID.

[0070] The substrate SUB may include a first surface FS, a second surface BS, multiple chamfered surfaces CS1 to CS8, and multiple side surfaces SS1 to SS4.

[0071] The first surface FS can be the front surface of the substrate SUB. The first surface FS can have a rectangular shape with a long side in the first direction DR1 and a short side in the second direction DR2.

[0072] The second surface BS can be a surface facing the first surface FS. The second surface BS can be the rear surface of the base SUB. The second surface BS can have a rectangular shape having a long side in the first direction DR1 and a short side in the second direction DR2.

[0073] Multiple chamfered surfaces CS1 to CS8 refer to surfaces that are located between the first surface FS and the multiple side surfaces SS1 to SS4, and between the second surface BS and the multiple side surfaces SS1 to SS4, and are chamfered at an angle to prevent notch defects from occurring in the multiple first side surface lines SIL1 and the multiple second side surface lines SIL2. Due to the multiple chamfered surfaces CS1 to CS8, the curvature angle of each of the multiple first side surface lines SIL1 and the multiple second side surface lines SIL2 can be made gentler, thus preventing notches or cracks from occurring in the multiple first side surface lines SIL1 and the multiple second side surface lines SIL2.

[0074] The first chamfered surface CS1 can extend from a first side (e.g., the lower side) of the first surface FS. The second chamfered surface CS2 can extend from a second side (e.g., the left side) of the first surface FS. The third chamfered surface CS3 can extend from a third side (e.g., the upper side) of the first surface FS. The fourth chamfered surface CS4 can extend from a fourth side (e.g., the right side) of the first surface FS. The interior angles formed by the first surface FS and the first chamfered surface CS1, the first surface FS and the second chamfered surface CS2, the first surface FS and the third chamfered surface CS3, and the first surface FS and the fourth chamfered surface CS4 can be greater than 90°.

[0075] The fifth chamfered surface CS5 may extend from the first side (e.g., the lower side) of the second surface BS. The sixth chamfered surface CS6 may extend from the second side (e.g., the left side) of the second surface BS. The seventh chamfered surface CS7 may extend from the third side (e.g., the upper side) of the second surface BS. The eighth chamfered surface CS8 may extend from the fourth side (e.g., the right side) of the second surface BS. The interior angles formed by the second surface BS and the fifth chamfered surface CS5, the second surface BS and the sixth chamfered surface CS6, the second surface BS and the seventh chamfered surface CS7, and the second surface BS and the eighth chamfered surface CS8 may be greater than 90°.

[0076] The first side surface SS1 may extend from the first chamfered surface CS1. The first chamfered surface CS1 may be disposed between the first surface FS and the first side surface SS1. The first side surface SS1 may be the lower side surface of the substrate SUB.

[0077] The second side surface SS2 may extend from the second chamfered surface CS2. The second chamfered surface CS2 may be located between the first surface FS and the second side surface SS2. The second side surface SS2 may be the left side surface of the substrate SUB.

[0078] The third side surface SS3 may extend from the third chamfered surface CS3. The third chamfered surface CS3 may be located between the first surface FS and the third side surface SS3. The third side surface SS3 may be the upper side surface of the substrate SUB.

[0079] The fourth side surface SS4 can extend from the fourth chamfered surface CS4. The fourth chamfered surface CS4 can be located between the first surface FS and the fourth side surface SS4. The fourth side surface SS4 can be the right side surface of the substrate SUB.

[0080] Multiple pixels PX can be disposed on the first surface FS of the substrate SUB to display an image. The multiple pixels PX can be arranged in a matrix along the first direction DR1 and the second direction DR2. See below for further details. Figure 3 Describes multiple pixels (PX).

[0081] Multiple first side surface lines SIL1 can be provided on at least two of the first surface FS, the second surface BS, the multiple chamfered surfaces CS1 to CS8, and at least one of the multiple side surfaces SS1 to SS4. For example, multiple first side surface lines SIL1 can be provided on the first surface FS, the second surface BS, the first chamfered surface CS1, the fifth chamfered surface CS5, and the first side surface SS1 to connect the first pad provided on the first side of the first surface FS with the first rear surface fan-out line BFL1 on the second surface BS.

[0082] Multiple second side surface lines SIL2 can be provided on at least two of the first surface FS, the second surface BS, the multiple chamfered surfaces CS1 to CS8, and at least one of the multiple side surfaces SS1 to SS4. For example, multiple second side surface lines SIL2 can be provided on the first surface FS, the second surface BS, the third chamfered surface CS3, the seventh chamfered surface CS7, and the third side surface SS3 to connect the second pad provided on the third side of the first surface FS (which is the side opposite to the first side of the first surface FS) to the second rear surface fan-out line BFL2 on the second surface BS.

[0083] Multiple first side surface lines SIL1 are used to connect the first pad disposed on the first surface FS and the first rear surface fan-out line BFL1 disposed on the second surface BS to each other. Multiple second side surface lines SIL2 are used to connect the second pad disposed on the first surface FS and the second rear surface fan-out line BFL2 disposed on the second surface BS to each other. The first pad and the second pad may correspond to the front surface pad. The first pad may be connected to the data line connected to the pixel PX of the substrate SUB. Some of the second pads may be connected to the first power line disposed on the first surface FS of the substrate SUB, and other second pads may be connected to the global power line disposed on the first surface FS of the substrate SUB.

[0084] Each of the plurality of device identifiers (DIDs) can be an identifier such as an identification number assigned to each of the display devices 10, in order to distinguish the display devices 10 from each other. The plurality of device identifiers (DIDs) can be disposed on the second surface BS of the substrate SUB. The plurality of device identifiers (DIDs) can be configured to be spaced apart (e.g., separated) from the first rear surface fan-out line BFL1, the second rear surface fan-out line BFL2, the plurality of first side surface lines SIL1, and the plurality of second side surface lines SIL2 in a plan view. Additionally, the device identifiers (DIDs) can be configured to be spaced apart (e.g., separated) from the plurality of first circuit boards 200 and second circuit boards 400 in a plan view. That is, the plurality of device identifiers (DIDs) can be in a electrically floating state.

[0085] Some of the multiple device identifiers (DIDs) can be configured to be adjacent to the second chamfered surface CS2, and other device identifiers (DIDs) can be configured to be adjacent to the fourth chamfered surface CS4. Some of the multiple device identifiers (DIDs) can be configured to be closer to the first chamfered surface CS1 than other device identifiers (DIDs). Additionally, other device identifiers (DIDs) can be configured to be closer to the third chamfered surface CS3 than some of the multiple device identifiers (DIDs).

[0086] Multiple device identifiers (DIDs) can be back surface metal layers formed using the same material and process as the first back surface fan-out line BFL1 and the second back surface fan-out line BFL2. For example, the back surface metal layers can be formed as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or alloys thereof.

[0087] Multiple first circuit boards 200 can be disposed on the second surface BS of the substrate SUB. The multiple first circuit boards 200 can be respectively connected to a first rear surface fan-out line BFL1 disposed on the second surface BS of the substrate SUB using a conductive adhesive member such as an anisotropic conductive film. The multiple first circuit boards 200 can be electrically connected to multiple first side surface lines SIL1 via the first rear surface fan-out line BFL1. Each of the multiple first circuit boards 200 can be a printed circuit board (PCB) or a flexible film, such as a flexible printed circuit board (FPCB) or a rigid printed circuit board.

[0088] The second circuit board 400 can be disposed on the second surface BS of the substrate SUB. The second circuit board 400 can be connected to the second rear surface fan-out line BFL2 disposed on the second surface BS of the substrate SUB using conductive adhesive members. The second circuit board 400 can be electrically connected to multiple second side surface lines SIL2 via the second rear surface fan-out line BFL2. The second circuit board 400 can be a printed circuit board (PCB) such as a flexible printed circuit board (FPCB) or a rigid printed circuit board, or a flexible film.

[0089] Each of the source drivers 300 can generate a data voltage and supply the data voltage to a data line via a first circuit board 200, a first rear surface fan-out line BFL1, and multiple first side surface lines SIL1. Each of the source drivers 300 can be formed as an integrated circuit (IC) and attached to its corresponding first circuit board 200. Alternatively, each of the source drivers 300 can be directly attached to the second surface BS of the substrate SUB in a chip-on-glass (COG) manner.

[0090] The power supply unit 500 can generate a voltage (e.g., a predetermined voltage) and supply the voltage (e.g., the predetermined voltage) to a voltage line (e.g., a predetermined voltage line) via the second circuit board 400, the second rear surface fan-out line BFL2, and multiple second side surface lines SIL2. For example, the power supply unit 500 can generate a first source voltage and supply the first source voltage to a first power line via the second circuit board 400, the second rear surface fan-out line BFL2, and multiple second side surface lines SIL2. Additionally, the power supply unit 500 can generate a global source voltage and supply the global source voltage to a global power line via the second circuit board 400, the second rear surface fan-out line BFL2, and multiple second side surface lines SIL2. The power supply unit 500 can be formed as an integrated circuit (IC) and attached to the second circuit board 400. Optionally, the power supply unit 500 can be directly attached to the second surface BS of the substrate SUB in a chip-on-glass (COG) manner.

[0091] like Figure 1 and Figure 2 As shown, by using multiple first side surface lines SIL1 and multiple second side surface lines SIL2, the bending of the flexible film along the side surface of the substrate SUB can be eliminated. Therefore, a borderless display device can be realized.

[0092] Figure 3 It is a layout diagram showing the first to third sub-pixels of pixels according to one or more embodiments.

[0093] Reference Figure 3 Each pixel PX can include multiple sub-pixels SP1, SP2, and SP3. Figure 3 The diagram already shows that each of the pixels PX comprises three sub-pixels SP1, SP2, and SP3 (i.e., first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3), but this disclosure is not limited thereto. Each of the first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3 can be connected to a pulse width modulation (PWM) data line DL (see...). Figure 4 One of the data lines, the first to the third data lines RDL, GDL and BDL (see) Figure 4 One of the scan lines GWL, GIL, GCL, SWPL, PAEL, and PWEL (see...) Figure 4 At least one of the following.

[0094] In a planar diagram, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have a rectangular shape, a square shape, and / or a rhombus shape. For example, as shown... Figure 3As shown, in the planar view, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2. Alternatively, in the planar view, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have a square or rhomboid shape including sides of the same length in the first direction DR1 and the second direction DR2.

[0095] like Figure 3 As shown, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be arranged along a first direction DR1. Optionally, any one of the second sub-pixel SP2 and the third sub-pixel SP3 can be arranged with the first sub-pixel SP1 along the first direction DR1, and the other of the second sub-pixel SP2 and the third sub-pixel SP3 can be arranged with the first sub-pixel SP1 along a second direction DR2. For example, the first sub-pixel SP1 and the second sub-pixel SP2 can be arranged along the first direction DR1, and the first sub-pixel SP1 and the third sub-pixel SP3 can be arranged with the second sub-pixel SP2 along the first direction DR1, and the other of the first sub-pixel SP1 and the third sub-pixel SP3 can be arranged with the second sub-pixel SP2 along the second direction DR2. Optionally, one of the first sub-pixel SP1 and the second sub-pixel SP2 can be arranged with the third sub-pixel SP3 along the first direction DR1, and the other of the first sub-pixel SP1 and the second sub-pixel SP2 can be arranged with the third sub-pixel SP3 along the second direction DR2.

[0096] The first sub-pixel SP1 can emit a first light, the second sub-pixel SP2 can emit a second light, and the third sub-pixel SP3 can emit a third light. Here, the first light can be light in the red band, the second light can be light in the green band, and the third light can be light in the blue band. The red band can be approximately 600nm to 750nm, the green band can be approximately 480nm to 560nm, and the blue band can be approximately 370nm to 460nm, but this disclosure is not limited thereto.

[0097] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include an inorganic light-emitting element having an inorganic semiconductor as the light-emitting element. For example, the inorganic light-emitting element may be a flip-chip micro-light-emitting diode (LED), but this disclosure is not limited thereto.

[0098] like Figure 3As shown, the areas of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be substantially the same as each other, but this disclosure is not limited thereto. At least one of the areas of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be different from another of the areas of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Optionally, any two of the areas of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be substantially the same as each other, and the other area of ​​the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be different from those two areas. Optionally, the areas of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be different from each other.

[0099] Figure 4 This is a block diagram illustrating a display device according to one or more embodiments.

[0100] Reference Figure 4 The display device 10 includes a display panel 100, a scan driver 110, a data driver 300G, a timing controller 600, and a power supply unit 500.

[0101] The display area DA of the display panel 100 may include sub-pixels SP1, SP2 and SP3 for displaying images, as well as scan write line GWL, scan initialization line GIL, scan control line GCL, sweep frequency signal line SWPL, PWM transmit line PWEL, pulse amplitude modulation (PAM) transmit line PAEL, PWM data line DL, first data line RDL, second data line GDL and third data line BDL connected to the sub-pixels SP1, SP2 and SP3.

[0102] The scan write line GWL, scan initialization line GIL, scan control line GCL, sweep frequency signal line SWPL, PWM transmitter line PWEL, and PAM transmitter line PAEL can extend along the first direction DR1 and can be set along the second direction DR2, which intersects the first direction DR1. The PWM data line DL, the first data line RDL, the second data line GDL, and the third data line BDL can extend along the second direction DR2 and can be set along the first direction DR1. The first data line RDL can be electrically connected to each other, the second data line GDL can be electrically connected to each other, and the third data line BDL can be electrically connected to each other.

[0103] Subpixels SP1, SP2, and SP3 may include a first subpixel SP1 that emits a first light, a second subpixel SP2 that emits a second light, and a third subpixel SP3 that emits a third light. The first light refers to light in the red band, the second light refers to light in the green band, and the third light refers to light in the blue band. For example, the peak wavelength of the first light may be located at approximately 600 nm to 750 nm, the peak wavelength of the second light may be located at approximately 480 nm to 560 nm, and the peak wavelength of the third light may be located at approximately 370 nm to 460 nm.

[0104] Each of sub-pixels SP1, SP2, and SP3 can be connected to one of the scan write lines GWL, one of the scan initialization lines GIL, one of the scan control lines GCL, one of the sweep frequency signal lines SWPL, one of the PWM transmit lines PWEL, and one of the PAM transmit lines PAEL. Additionally, each of the first sub-pixels SP1 can be connected to one of the PWM data lines DL and one of the first data lines RDL. Furthermore, each of the second sub-pixels SP2 can be connected to one of the PWM data lines DL and one of the second data lines GDL. Additionally, each of the third sub-pixels SP3 can be connected to one of the PWM data lines DL and one of the third data lines BDL.

[0105] The non-display area NDA of the display panel 100 may include a scan driver 110, a first demultiplexer unit DMX1, and a second demultiplexer unit DMX2.

[0106] The scan driver 110, used to apply signals to the scan write line GWL, scan initialization line GIL, scan control line GCL, sweep frequency signal line SWPL, PWM transmitter line PWEL, and PAM transmitter line PAEL, can be located in the non-display area NDA of the display panel 100. Figure 4 The scan driver 110 has been shown to be located at one edge of the display panel 100, but this disclosure is not limited thereto. The scan driver 110 may be located at the edges of both sides of the display panel 100.

[0107] The scan driver 110 may include a first scan signal driver 111, a second scan signal driver 112, a sweep frequency signal driver 113, and a transmit signal driver 114.

[0108] The first scan signal driver 111 can receive the first scan drive control signal GDCS1 from the timing controller 600. The first scan signal driver 111 can output a scan initialization signal to the scan initialization line GIL and a scan write signal to the scan write line GWL according to the first scan drive control signal GDCS1. That is, the first scan signal driver 111 can output two scan signals simultaneously: a scan initialization signal and a scan write signal.

[0109] The second scan signal driver 112 can receive the second scan drive control signal GDCS2 from the timing controller 600. The second scan signal driver 112 can output a scan control signal to the scan control line GCL according to the second scan drive control signal GDCS2.

[0110] The sweep signal driver 113 can receive the first transmit control signal ECS1 and the sweep control signal SPCS from the timing controller 600. The sweep signal driver 113 can output a PWM transmit signal to the PWM transmit line PWEL and a sweep signal to the sweep signal line SWPL according to the first transmit control signal ECS1. In other words, the sweep signal driver 113 can output both the PWM transmit signal and the sweep signal simultaneously.

[0111] The transmit signal driver 114 can receive the second transmit control signal ECS2 from the timing controller 600. The transmit signal driver 114 can output a PAM transmit signal to the PAM transmit line PAEL according to the second transmit control signal ECS2.

[0112] The first demultiplexer unit DMX1 switches the connection between each PWM data line DL and the global power line GVL. Additionally, the first demultiplexer unit DMX1 switches the connection between each first data line RDL and the first data voltage line RPL, switches the connection between each second data line GDL and the second data voltage line GPL, and switches the connection between each third data line BDL and the third data voltage line BPL.

[0113] The second demultiplexer unit DMX2 can be located between the fan-out line FL and the PWM data line DL. The second demultiplexer unit DMX2 can divide the PWM data voltage applied to each fan-out line FL into Q PWM data lines DL (here, Q is an integer of 2 or greater) or Q first data lines to third data lines RDL, GDL and BDL.

[0114] The first demultiplexer unit DMX1 can be configured to be adjacent to the second pad, and the second demultiplexer unit DMX2 can be configured to be adjacent to the first pad. That is, the first demultiplexer unit DMX1 can be configured to be adjacent to one side of the display panel 100 (e.g., the lower side of the display panel 100). The second demultiplexer unit DMX2 can be configured to be adjacent to the other side of the display panel 100 (e.g., the upper side of the display panel 100).

[0115] The timing controller 600 receives digital video data DATA and a timing signal TSS. Based on the timing signal TSS, the timing controller 600 generates a first scan drive control signal GDCS1, a second scan drive control signal GDSC2, a first transmit control signal ECS1, a second transmit control signal ECS2, and a sweep frequency control signal SPCS for controlling the operating timing of the scan driver 110. Additionally, the timing controller 600 can generate a PWM control signal DCS for controlling the operating timing of the source driver 300.

[0116] The timing controller 600 outputs a first scan drive control signal GDCS1, a second scan drive control signal GDSC2, a first transmit control signal ECS1, a second transmit control signal ECS2, and a sweep frequency control signal SPCS to the scan driver 110. The timing controller 600 outputs digital video data DATA and PWM control signal DCS to the data driver 300G.

[0117] The data driver 300G may include multiple source drivers 300. The data driver 300G converts digital video data DATA into analog PWM data voltage and outputs the analog PWM data voltage to the fan-out line FL.

[0118] The power supply unit 500 can generate a first data voltage and output it to a first data voltage line RPL, generate a second data voltage and output it to a second data voltage line GPL, and generate a third data voltage and output it to a third data voltage line BPL. The power supply unit 500 can also generate a global source voltage and output it to a global power line GVL.

[0119] Furthermore, the power supply unit 500 can generate multiple source voltages and output these multiple source voltages to the display panel 100. For example, the power supply unit 500 can output a first source voltage VDD1, a second source voltage VDD2, a third source voltage VSS, an initialization voltage VINT, a gate on-state voltage VGL, and a gate off-state voltage VGH to the display panel 100. The first source voltage VDD1 and the second source voltage VDD2 can be high-potential driving voltages used to drive the light-emitting elements of each of the sub-pixels SP1, SP2, and SP3. The third source voltage VSS can be a low-potential driving voltage used to drive the light-emitting elements of each of the sub-pixels SP1, SP2, and SP3. The initialization voltage VINT and the gate off-state voltage VGH can be applied to each of the sub-pixels SP1, SP2, and SP3, and the gate on-state voltage VGL and the gate off-state voltage VGH can be applied to the scan driver 110.

[0120] Figure 5 This is a circuit diagram illustrating a first sub-pixel according to one or more embodiments.

[0121] Reference Figure 5 According to one or more embodiments, the first sub-pixel SP1 can be connected to the k-th scan write line GWLk, the k-th scan initialization line GILk, the k-th scan control line GCLk, the k-th sweep frequency signal line SWPLk, the k-th PWM transmit line PWELk, and the k-th PAM transmit line PAELk. Additionally, the first sub-pixel SP1 can be connected to the j-th PWM data line DLj and the first data line RDL. Furthermore, the first sub-pixel SP1 can be connected to a first power line VDL1 that applies a first source voltage VDD1, a second power line VDL2 that applies a second source voltage VDD2, a third power line VSL that applies a third source voltage VSS, an initialization voltage line VIL that applies an initialization voltage VINT, and a gate cutoff voltage line VGHL that applies a gate cutoff voltage VGH.

[0122] The first sub-pixel SP1 may include a light-emitting element EL, a first pixel driving unit PDU1, a second pixel driving unit PDU2, and a third pixel driving unit PDU3.

[0123] The light-emitting element EL emits light according to the driving current generated by the second pixel driving unit PDU2. The light-emitting element EL can be disposed between the seventeenth transistor T17 and the third electric field line VSL. The first electrode of the light-emitting element EL can be connected to the second electrode of the seventeenth transistor T17, and the second electrode of the light-emitting element EL can be connected to the third electric field line VSL. The first electrode of the light-emitting element EL can be an anode electrode, and the second electrode of the light-emitting element EL can be a cathode electrode. The light-emitting element EL can be an inorganic light-emitting element comprising a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For example, the light-emitting element EL can be a micro-light-emitting diode made of inorganic semiconductor, but is not limited thereto.

[0124] The first pixel driving unit PDU1 controls the voltage of the third node N3 of the third pixel driving unit PDU3 by generating a control current based on the j-th PWM data voltage of the j-th PWM data line DLj. Since the pulse width of the driving current flowing to the light-emitting element EL can be adjusted by the control current of the first pixel driving unit PDU1, the first pixel driving unit PDU1 can be a pulse width modulation unit (PWM unit) that performs pulse width modulation on the driving current flowing to the light-emitting element EL.

[0125] The first pixel driving unit PDU1 may include a first transistor T1 to a seventh transistor T7 and a first capacitor PC1.

[0126] The first transistor T1 controls the control current flowing between the first electrode and the second electrode of the first transistor T1 based on the voltage applied to the gate electrode of the first transistor T1.

[0127] The second transistor T2 is turned on by the k-th scan write signal of the k-th scan write line GWLk, so as to supply the PWM data voltage of the j-th PWM data line DLj to the first electrode of the first transistor T1.

[0128] The third transistor T3 is turned on by the k-th scan initialization signal of the k-th scan initialization line GILk to connect the initialization voltage line VIL to the gate electrode of the first transistor T1. For this purpose, the gate electrode of the first transistor T1 can discharge to the initialization voltage VINT of the initialization voltage line VIL during the period when the third transistor T3 is turned on. In this case, the gate on-state voltage VGL of the k-th scan initialization signal can be different from the initialization voltage VINT of the initialization voltage line VIL. Specifically, because the voltage difference between the gate on-state voltage VGL and the initialization voltage VINT is greater than the threshold voltage of the third transistor T3, the third transistor T3 can be stably turned on even after the initialization voltage VINT is applied to the gate electrode of the first transistor T1. Therefore, when the third transistor T3 is turned on, the initialization voltage VINT can be stably applied to the gate electrode of the first transistor T1, regardless of the threshold voltage of the third transistor T3.

[0129] The third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32 connected in series with each other. Therefore, leakage of voltage from the gate electrode of the first transistor T1 through the third transistor T3 can be reduced.

[0130] The fourth transistor T4 is turned on by the k-th scan write signal of the k-th scan write line GWLk, so as to connect the gate electrode and the second electrode of the first transistor T1 to each other. For this purpose, the first transistor T1 can operate as a diode during the period when the fourth transistor T4 is turned on.

[0131] The fourth transistor T4 may include a third sub-transistor T41 and a fourth sub-transistor T42 connected in series with each other. Therefore, leakage of voltage from the gate electrode of the first transistor T1 through the fourth transistor T4 can be reduced.

[0132] The fifth transistor T5 is turned on by the kth PWM transmit signal of the kth PWM transmit line PWELk to connect the first electrode of the first transistor T1 to the first power line VDL1.

[0133] The sixth transistor T6 is turned on by the kth PWM transmit signal of the kth PWM transmit line PWELk to connect the second electrode of the first transistor T1 to the third node N3 of the third pixel driving unit PDU3.

[0134] The seventh transistor T7 can be turned on by the k-th scan control signal of the k-th scan control line GCLk to supply the gate cutoff voltage VGH of the gate cutoff voltage line VGHL to the first node N1 connected to the k-th sweep signal line SWPLk. Therefore, during the period when the initialization voltage VINT is applied to the gate electrode of the first transistor T1 and during the period when the PWM data voltage of the j-th PWM data line DLj and the threshold voltage of the first transistor T1 are programmed, the voltage change of the gate electrode of the first transistor T1 can be prevented from being reflected in the k-th sweep signal of the k-th sweep signal line SWPLk by the first capacitor PC1.

[0135] A first capacitor PC1 can be disposed between the gate electrode of the first transistor T1 and the first node N1. One electrode of the first capacitor PC1 can be connected to the gate electrode of the first transistor T1, and the other electrode of the first capacitor PC1 can be connected to the first node N1.

[0136] The first node N1 can be the contact point between the k-th sweep frequency signal line SWPLk, the second electrode of the seventh transistor T7, and the other electrode of the first capacitor PC1.

[0137] The second pixel driving unit PDU2 generates a driving current applied to the light-emitting element EL based on the first PWM data voltage of the first data line RDL. The second pixel driving unit PDU2 can be a pulse amplitude modulation unit (PAM unit) that performs pulse amplitude modulation. Alternatively, the second pixel driving unit PDU2 can be a constant current generating unit that generates a constant driving current based on the first PWM data voltage.

[0138] Furthermore, the second pixel driving unit PDU2 of each of the first sub-pixels SP1 can receive the same first PWM data voltage and generate the same driving current, regardless of the brightness of the first sub-pixel SP1. Similarly, the second pixel driving unit PDU2 of each of the second sub-pixels SP2 can receive the same second PWM data voltage and generate the same driving current, regardless of the brightness of the second sub-pixel SP2. The second pixel driving unit PDU2 of each of the third sub-pixels SP3 can receive the same third PWM data voltage and generate the same driving current, regardless of the brightness of the third sub-pixel SP3.

[0139] The second pixel driving unit PDU2 may include the eighth transistor T8 to the fourteenth transistor T14 and the second capacitor PC2.

[0140] The eighth transistor T8 controls the drive current flowing to the light-emitting element EL according to the voltage applied to its gate electrode.

[0141] The ninth transistor T9 is turned on by the k-th scan write signal of the k-th scan write line GWLk to apply the first PWM data voltage of the first data line RDL to the first electrode of the eighth transistor T8.

[0142] The tenth transistor T10 is turned on by the k-th scan initialization signal of the k-th scan initialization line GILk, connecting the initialization voltage line VIL to the gate electrode of the eighth transistor T8. Therefore, the gate electrode of the eighth transistor T8 can discharge to the initialization voltage VINT of the initialization voltage line VIL during the period when the tenth transistor T10 is turned on. In this case, the gate on-state voltage VGL of the k-th scan initialization signal can be different from the initialization voltage VINT of the initialization voltage line VIL. Specifically, because the voltage difference between the gate on-state voltage VGL and the initialization voltage VINT is greater than the threshold voltage of the tenth transistor T10, the tenth transistor T10 can be stably turned on even after the initialization voltage VINT is applied to the gate electrode of the eighth transistor T8. Therefore, when the tenth transistor T10 is turned on, the initialization voltage VINT can be stably applied to the gate electrode of the eighth transistor T8, regardless of the threshold voltage of the tenth transistor T10.

[0143] The tenth transistor T10 may include a fifth sub-transistor T101 and a sixth sub-transistor T102 connected in series with each other. Therefore, leakage of voltage from the gate electrode of the eighth transistor T8 through the tenth transistor T10 can be reduced.

[0144] The eleventh transistor T11 is turned on by the k-th scan write signal of the k-th scan write line GWLk, so as to connect the gate electrode and the second electrode of the eighth transistor T8 to each other. Therefore, the eighth transistor T8 can operate as a diode during the period when the eleventh transistor T11 is turned on.

[0145] The eleventh transistor T11 may include a seventh sub-transistor T111 and an eighth sub-transistor T112 connected in series with each other. Therefore, leakage of voltage from the gate electrode of the eighth transistor T8 through the eleventh transistor T11 can be reduced.

[0146] The twelfth transistor T12 is turned on by the kth PWM transmit signal of the kth PWM transmit line PWELk to connect the first electrode of the eighth transistor T8 to the second power line VDL2.

[0147] The thirteenth transistor T13 is turned on by the k-th scan control signal of the k-th scan control line GCLk to connect the first power line VDL1 to the second node N2.

[0148] The fourteenth transistor T14 is turned on via the k-th PWM transmit signal of the k-th PWM emitter line PWELk to connect the second power line VDL2 to the second node N2. Therefore, when the fourteenth transistor T14 is turned on, the second source voltage VDD2 of the second power line VDL2 can be supplied to the second node N2.

[0149] The second capacitor PC2 can be disposed between the gate electrode of the eighth transistor T8 and the second node N2. One electrode of the second capacitor PC2 can be connected to the gate electrode of the eighth transistor T8, and the other electrode of the second capacitor PC2 can be connected to the second node N2.

[0150] The second node N2 can be the contact point between the second electrode of the thirteenth transistor T13, the second electrode of the fourteenth transistor T14, and the other electrode of the second capacitor PC2.

[0151] The third pixel driving unit PDU3 adjusts the time period during which the driving current is applied to the light-emitting element EL according to the voltage of the third node N3.

[0152] The third pixel driving unit PDU3 may include the fifteenth transistor T15 to the nineteenth transistor T19 and the third capacitor PC3.

[0153] The fifteenth transistor T15 is turned on or off according to the voltage of the third node N3. When the fifteenth transistor T15 is on, the drive current of the eighth transistor T8 can be supplied to the light-emitting element EL, and when the fifteenth transistor T15 is off, the drive current of the eighth transistor T8 can not be supplied to the light-emitting element EL. Therefore, the on-time of the fifteenth transistor T15 can be substantially the same as the emission time of the light-emitting element EL.

[0154] The sixteenth transistor T16 is turned on by the k-th scan control signal of the k-th scan control line GCLk to connect the initialization voltage line VIL to the third node N3. Therefore, during the period when the sixteenth transistor T16 is turned on, the third node N3 can be discharged to the initialization voltage VINT of the initialization voltage line VIL.

[0155] The sixteenth transistor T16 may include a ninth sub-transistor T161 and a tenth sub-transistor T162 connected in series with each other. Therefore, it is possible to prevent the voltage of the third node N3 from leaking through the sixteenth transistor T16.

[0156] The seventeenth transistor T17 is turned on by the kth PAM emission signal of the kth PAM emission line PAELk, so as to connect the second electrode of the fifteenth transistor T15 to the first electrode of the light-emitting element EL.

[0157] The eighteenth transistor T18 is turned on by the k-th scan control signal of the k-th scan control line GCLk to connect the initialization voltage line VIL to the first electrode of the light-emitting element EL. For this purpose, the first electrode of the light-emitting element EL can discharge to the initialization voltage VINT of the initialization voltage line VIL during the period when the eighteenth transistor T18 is turned on.

[0158] The nineteenth transistor T19 is turned on by the test signal on the test signal line TSTL to connect the second electrode of the light-emitting element EL to the third power line VSL. Therefore, by turning on the nineteenth transistor T19 in test mode, the voltage or current of the first electrode of the light-emitting element EL can be sensed using the third power line VSL.

[0159] The third capacitor PC3 can be positioned between the third node N3 and the initialization voltage line VIL. One electrode of the third capacitor PC3 can be connected to the third node N3, and the other electrode of the third capacitor PC3 can be connected to the initialization voltage line VIL.

[0160] The third node N3 can be the contact point between the second electrode of the sixth transistor T6, the gate electrode of the fifteenth transistor T15, the first electrode of the ninth sub-transistor T161, and one of the electrodes of the third capacitor PC3.

[0161] Either the first electrode or the second electrode of each of the first transistors T1 to the nineteenth transistor T19 can be a source electrode, and the other of the first electrode or the second electrode of each of the first transistors T1 to the nineteenth transistor T19 can be a drain electrode. The active layer of each of the first transistors T1 to the nineteenth transistor T19 can be made of polycrystalline silicon, amorphous silicon, and / or oxide semiconductor. When the active layer of each of the first transistors T1 to the nineteenth transistor T19 is made of polycrystalline silicon, the active layer of each of the first transistors T1 to the nineteenth transistor T19 can be formed by a low-temperature polycrystalline silicon (LTPS) process.

[0162] In addition, it has already been Figure 5 The present disclosure primarily describes each of the first transistors T1 to the nineteenth transistor T19 as a P-type metal-oxide-semiconductor field-effect transistor (MOSFET), but this disclosure is not limited thereto. For example, each or at least some of the first transistors T1 to the nineteenth transistor T19 may also be formed as an N-type MOSFET.

[0163] The second sub-pixel SP2 and the third sub-pixel SP3 according to one or more embodiments can be compared with reference to Figure 5 The first sub-pixel SP1 is described substantially the same. Therefore, the descriptions of the second sub-pixel SP2 and the third sub-pixel SP3 according to one or more embodiments are omitted.

[0164] Figure 6 It is a layout diagram showing a first pad electrode, a second pad electrode, a third electric field line, and a lower light blocking pattern of a first sub-pixel according to one or more embodiments.

[0165] Reference Figure 6 The first pad electrode APD, the second pad electrode CPD, and the third electric field line VSL can be made of the same material and disposed in the same layer (e.g., disposed in the same layer). For example, the first pad electrode APD, the second pad electrode CPD, and the third electric field line VSL can be included in a fourth source metal layer and can be disposed in a third planarization film 190 (see...). Figure 7 )superior.

[0166] The first pad electrode APD is an electrode electrically connected to the first electrode of the light-emitting element EL, and the second pad electrode CPD is an electrode electrically connected to the second electrode of the light-emitting element EL. The first pad electrode APD and the second pad electrode CPD can be electrically disconnected from each other. The first pad electrode APD and the second pad electrode CPD can be configured to be physically spaced apart from each other (e.g., separated).

[0167] The first pad electrode APD can be configured as an island. The first pad electrode APD can be connected to the third connecting electrode CCE3 through the first connecting contact hole ACH1 (see...). Figure 7 ).

[0168] The first pad electrode APD can be surrounded by a second pad electrode CPD and a third electric field line VSL. The second pad electrode CPD can be disposed on a first side of the first pad electrode APD, and the third electric field line VSL can be disposed on other sides of the first pad electrode APD. In this case, a first gap GP1 can exist between the first side of the first pad electrode APD and the second pad electrode CPD. In addition, a second gap GP2 can exist between other sides of the first pad electrode APD and the third electric field line VSL.

[0169] For example, such as Figure 6 As shown, the second pad electrode CPD can be disposed to the left of the first pad electrode APD, and the third electric field line VSL can be disposed above, to the right, and below the first pad electrode APD. In this case, the first gap GP1 can exist between the left side of the first pad electrode APD and the second pad electrode CPD, and the second gap GP2 can exist between each of the upper, right, and lower sides of the first pad electrode APD and the third electric field line VSL.

[0170] The first side of the second pad electrode CPD can be connected to the third electric field line VSL. The third electric field line VSL can be disposed on the second and third sides of the second pad electrode CPD, and the first pad electrode APD can be disposed on the fourth side of the second pad electrode CPD. The first and third sides of the second pad electrode CPD can face each other, and the second and fourth sides of the second pad electrode CPD can also face each other. The second pad electrode CPD and the third electric field line VSL can be integrally formed together.

[0171] The third gap GP3 may exist between each of the second and third sides of the second pad electrode CPD and the third electric field line VSL, and the first gap GP1 may exist between the fourth side of the second pad electrode CPD and the first pad electrode APD.

[0172] For example, the upper side of the second pad electrode CPD can be connected to the third electric field line VSL, which can be located on the left and lower sides of the second pad electrode CPD, and the first pad electrode APD can be located on the right side of the second pad electrode CPD. In this case, the third gap GP3 can exist between each of the left and lower sides of the second pad electrode CPD and the third electric field line VSL, and the first gap GP1 can exist between the right side of the second pad electrode CPD and the first pad electrode APD.

[0173] The lower light-blocking pattern BML can be superimposed on the first gap GP1, the second gap GP2, and the third gap GP3. Therefore, light emitted from the light-emitting element EL disposed on the first pad electrode APD and the second pad electrode CPD, traveling in the downward direction of the display panel 100 through the first gap GP1, the second gap GP2, and the third gap GP3, can be blocked by the lower light-blocking pattern BML. This improves the phenomenon where light emitted from the light-emitting element EL is reflected from lines and device identifiers DID disposed on the rear surface of the display panel 100 and is thus perceived as rear surface reflection.

[0174] According to one or more embodiments, the first pad electrode APD, second pad electrode CPD, third electric field line VSL, and lower light blocking pattern BML of each of the second sub-pixel SP2 and the third sub-pixel SP3 can be compared with reference to... Figure 6 The first pad electrode APD, second pad electrode CPD, third electric field line VSL, and lower light blocking pattern BML of the first sub-pixel SP1 are substantially the same. Therefore, the description of the first pad electrode APD, second pad electrode CPD, third electric field line VSL, and lower light blocking pattern BML of each of the second sub-pixels SP2 and the third sub-pixels SP3 according to one or more embodiments is omitted.

[0175] Figure 7 It shows along Figure 6A cross-sectional view of an example display panel taken by line I1-I1'.

[0176] Reference Figure 7 The display panel 100 may include a substrate SUB, a thin film transistor layer, and a light-emitting element layer.

[0177] The substrate SUB can be made of an insulating material such as glass and / or polymer resin. For example, when the substrate SUB is made of a polymer resin, it may include polyimide. The substrate SUB can be a flexible substrate that can be bent, folded, and / or rolled up.

[0178] The thin-film transistor layer can be disposed on the substrate SUB. The thin-film transistor layer includes... Figure 5 The first transistor T1 to the nineteenth transistor T19, the lower light-blocking pattern BML, the buffer film BF, and the multiple insulating films 130, 141, 142, 160, 161, 180, 181 and 190 shown are included.

[0179] A bottom light blocking pattern (BML) can be disposed on the substrate SUB. The bottom light blocking pattern BML can be superimposed on the first gap GP1, second gap GP2, and third gap GP3 in a third direction DR3 (e.g., the thickness direction of the substrate SUB). Therefore, light emitted from the light-emitting element EL disposed on the first pad electrode APD and the second pad electrode CPD that travels downwards through the first gap GP1, second gap GP2, and third gap GP3 of the substrate SUB can be blocked by the bottom light blocking pattern BML. Therefore, the phenomenon that light emitted from the light-emitting element EL is reflected from lines and device identifiers DID disposed on the rear surface of the display panel 100 and is considered a rear surface reflection can be improved.

[0180] The lower light-blocking pattern (BML) can be formed as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or alloys thereof. The lower light-blocking pattern (BML) can be formed with a thickness of approximately 3,000 Å or greater for use as a light-blocking structure.

[0181] A buffer film (BF) can be disposed on a lower light-blocking pattern (BML) and a substrate (SUB). The buffer film (BF) may comprise multiple inorganic films that are alternately stacked. For example, the buffer film (BF) may be formed as multiple films in which one or more inorganic films, such as silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and / or aluminum oxide layers, are alternately stacked.

[0182] The first transistor T1 to the nineteenth transistor T19 can be disposed on the buffer film BF. The first transistor T1 to the nineteenth transistor T19 can be formed as thin-film transistors. For ease of explanation, [the following is already shown] Figure 7The image shows only the seventeenth transistor T17, which is one of the nineteenth transistors T19.

[0183] The active layer of the seventeenth transistor T17 can be disposed on the buffer film BF. The active layer of the seventeenth transistor T17 includes the channel CH17, the source electrode S17, and the drain electrode D17.

[0184] The gate insulating film 130 can be disposed on the active layer and buffer film BF of the seventeenth transistor T17. The gate insulating film 130 can be formed as, for example, silicon nitride (SiN). x ) membrane, silicon dioxide (SiO) x ) membrane, silicon oxynitride (SiON) membrane, titanium dioxide (TiO2) membrane x ) film and / or alumina (AlO) x Inorganic insulating membrane.

[0185] A first gate metal layer may be disposed on the gate insulating film 130. The first gate metal layer includes the gate electrode G17 of the seventeenth transistor T17. The gate electrode G17 of the seventeenth transistor T17 may be stacked with the channel CH17 on the third direction DR3, which is the thickness direction of the substrate SUB. The first gate metal layer may be formed as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and / or copper (Cu) and / or alloys thereof.

[0186] The first interlayer insulating film 141 can be disposed on the first gate metal layer and the gate insulating film 130. The first interlayer insulating film 141 can be formed as, for example, silicon nitride (SiN). x ) membrane, silicon dioxide (SiO) x ) membrane, silicon oxynitride (SiON) membrane, titanium dioxide (TiO2) membrane x ) film and / or alumina (AlO) x Inorganic insulating membrane.

[0187] The second gate metal layer can be disposed on the first interlayer insulating film 141. The second gate metal layer can be formed as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and / or copper (Cu) and / or alloys thereof.

[0188] The second interlayer insulating film 142 can be disposed on the second gate metal layer and the first interlayer insulating film 141. The second interlayer insulating film 142 can be formed as, for example, silicon nitride (SiN). x ) membrane, silicon dioxide (SiO) x ) membrane, silicon oxynitride (SiON) membrane, titanium dioxide (TiO2) membrane x ) film and / or alumina (AlO)x Inorganic insulating membrane.

[0189] A first source metal layer may be disposed on the second interlayer insulating film 142. The first source metal layer includes a first connection electrode CCE1. The first connection electrode CCE1 can be connected to the drain electrode D17 of the seventeenth transistor T17 through a fourth connection contact hole ACH4 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The first source metal layer may be formed as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or alloys thereof.

[0190] The first planarization film 160 may be disposed on the first source metal layer and the second interlayer insulating film 142. The first planarization film 160 may be formed as an organic insulating film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin, etc.

[0191] The first inorganic insulating film 161 can be disposed on the first planarization film 160. The first inorganic insulating film 161 can be formed as silicon nitride (SiN). x ) membrane, silicon dioxide (SiO) x ) membrane, silicon oxynitride (SiON) membrane, titanium dioxide (TiO2) membrane x ) film and / or alumina (AlO) x )membrane.

[0192] The second source metal layer can be disposed on the first inorganic insulating film 161. The second source metal layer includes a second connecting electrode CCE2. The second connecting electrode CCE2 can be connected to the first connecting electrode CCE1 through a third connecting contact hole ACH3 penetrating the first planarization film 160 and the first inorganic insulating film 161. The second source metal layer can be formed as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and / or copper (Cu) and / or alloys thereof.

[0193] The second planarization film 180 can be disposed on the second source metal layer and the first inorganic insulating film 161. The second planarization film 180 can be formed as an organic insulating film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin, etc.

[0194] The second inorganic insulating film 181 can be disposed on the second planarization film 180. The second inorganic insulating film 181 can be formed as silicon nitride (SiN). x ) membrane, silicon dioxide (SiO) x ) membrane, silicon oxynitride (SiON) membrane, titanium dioxide (TiO2) membrane x) film and / or alumina (AlO) x )membrane.

[0195] The third source metal layer can be disposed on the second inorganic insulating film 181. The third source metal layer includes a third connecting electrode CCE3. The third connecting electrode CCE3 can be connected to the second connecting electrode CCE2 through a second connecting contact hole ACH2 penetrating the second planarization film 180 and the second inorganic insulating film 181. The third source metal layer can be formed as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and / or copper (Cu) and / or alloys thereof.

[0196] The third planarization film 190 can be disposed on the third source metal layer and the second inorganic insulating film 181. The third planarization film 190 can be formed as an organic insulating film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin, etc.

[0197] A fourth source metal layer may be disposed on the third planarization film 190. The fourth source metal layer includes a first pad electrode APD, a second pad electrode CPD, and a third electric field line VSL. The first pad electrode APD can be connected to the third connection electrode CCE3 through a first connection contact hole ACH1 penetrating the third planarization film 190.

[0198] The fourth source metal layer can be formed as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and / or copper (Cu) and / or alloys thereof.

[0199] The first pad connection electrode PDE1 can be disposed on the first pad electrode APD, and the second pad connection electrode PDE2 can be disposed on the second pad electrode CPD. The thickness of the first pad connection electrode PDE1 can be less than the thickness of the first pad electrode APD, and the thickness of the second pad connection electrode PDE2 can be less than the thickness of the second pad electrode CPD.

[0200] The first pad connection electrode PDE1 can be electrically connected to the first electrode CTE1 of the light-emitting element EL, and the second pad connection electrode PDE2 can be electrically connected to the second electrode CTE2 of the light-emitting element EL. Each of the first pad connection electrode PDE1 and the second pad connection electrode PDE2 can be made of a transparent conductive material (TCO) such as indium tin oxide (ITO) and / or indium zinc oxide (IZO).

[0201] The fourth planarization film 210 can be disposed on a portion of the first pad electrode APD and the third electric field line VSL. The fourth planarization film 210 can be formed as an organic insulating film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin, etc.

[0202] A fourth inorganic insulating film 211 can be disposed on the fourth planarization film 210. The fourth inorganic insulating film 211 can be configured to cover the edges of the first pad electrode APD and the second pad electrode CPD. The fourth inorganic insulating film 211 can be formed as silicon nitride (SiN). x ) membrane, silicon dioxide (SiO) x ) membrane, silicon oxynitride (SiON) membrane, titanium dioxide (TiO2) membrane x ) film and / or alumina (AlO) x )membrane.

[0203] The light-emitting element layer can be disposed on the first pad connecting electrode PDE1 and the second pad connecting electrode PDE2. The light-emitting element layer may include a light-emitting element EL.

[0204] A flip-chip microLED has been shown where the light-emitting element EL has its first electrode CTE1 facing the first pad electrode APD and its second electrode CTE2 facing the second pad electrode CPD. The light-emitting element EL can be made of an inorganic material such as gallium nitride (GaN). The length of each of the three directions DR1, DR2, and DR3 of the light-emitting element EL can range from a few micrometers to several hundred micrometers. For example, the length of each of the three directions DR1, DR2, and DR3 of the light-emitting element EL can be approximately 100 μm or less.

[0205] Light-emitting elements (ELs) can be grown and formed on a semiconductor substrate such as a silicon wafer. Each EL can be directly transferred from the silicon wafer to the first pad connection electrode PDE1 and the second pad connection electrode PDE2 of the substrate SUB. Alternatively, each EL can be transferred to the first pad connection electrode PDE1 and the second pad connection electrode PDE2 of the substrate SUB by an electrostatic method using an electrostatic head or by an imprinting method using an elastic polymer material such as polydimethylsiloxane (PDMS) and / or silicon as the transfer substrate.

[0206] The light-emitting element (EL) can be a light-emitting structure comprising a substrate (SSUB), an n-type semiconductor (NSEM), an active layer (MQW), a p-type semiconductor (PSEM), a first electrode (CTE1), and a second electrode (CTE2).

[0207] The substrate SSUB can be a sapphire substrate, but this disclosure is not limited to this.

[0208] An n-type semiconductor NSEM can be disposed on one surface of a substrate SSUB. For example, an n-type semiconductor NSEM can be disposed on the lower surface of a substrate SSUB. The n-type semiconductor NSEM can be made of GaN doped with n-type dopants such as Si, Ge, Se and / or Sn.

[0209] The active quantum well (MQW) layer can be disposed on a portion of a surface of an n-type semiconductor NSEM. The active MQW layer can comprise materials having a single quantum well structure or a multiple quantum well structure. When the active MQW layer comprises a material with a multiple quantum well structure, it can have a structure in which multiple well layers and barrier layers are alternately stacked. In this case, the well layers can be made of InGaN, and the barrier layers can be made of GaN or AlGaN, but this disclosure is not limited thereto. Optionally, the active MQW layer can have a structure in which semiconductor materials with high band gaps and semiconductor materials with small band gaps are alternately stacked, and can include other group III to group V semiconductor materials depending on the wavelength of the emitted light.

[0210] The p-type semiconductor PSEM can be disposed on one surface of the active layer MQW. The p-type semiconductor PSEM can be made of GaN doped with p-type dopants such as Mg, Zn, Ca, Sr and / or Ba.

[0211] The first electrode CTE1 can be disposed on a p-type semiconductor PSEM, and the second electrode CTE2 can be disposed on another portion of the surface of an n-type semiconductor NSEM. The other portion of the surface of the n-type semiconductor NSEM on which the second electrode CTE2 is disposed can be spaced apart (e.g., separated) from the portion of the surface of the n-type semiconductor NSEM on which the active layer MQW is disposed.

[0212] The first electrode CTE1 can be attached to the first pad connection electrode PDE1 using a conductive adhesive component such as an anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). Alternatively, the first electrode CTE1 can be attached to the first pad connection electrode PDE1 using a soldering process.

[0213] The second electrode CTE2 can be bonded to the second pad connection electrode PDE2 using a conductive adhesive component such as ACF or ACP. Alternatively, the second electrode CTE2 can be attached to the second pad connection electrode PDE2 using a soldering process.

[0214] Figure 8 It is a layout diagram showing a first pad electrode, a second pad electrode, a first electric field line, a third electric field line, and a pad light blocking pattern of a first sub-pixel according to one or more embodiments.

[0215] Figure 8Implementation examples and Figure 6 The difference in this embodiment lies in the addition of a first power line VDL1 and a light-blocking pattern BP. Figure 8 In the embodiments, the terms "and" are omitted. Figure 6 The description of the content of the embodiment is repeated.

[0216] Reference Figure 8 When the lower light-blocking pattern BML is made of a metallic material with high light transmittance or is formed with a thickness of less than 3,000 Å, light emitted from the light-emitting element EL will pass through the lower light-blocking pattern BML. In this case, the light emitted from the light-emitting element EL will be reflected from the lines and device identifier DID provided on the rear surface of the display panel 100 and will be considered as rear surface reflection. Therefore, it is necessary to block the light traveling in the downward direction of the display panel 100 through the first gap GP1, the second gap GP2, and the third gap GP3 by other lines or light-blocking patterns as well as the lower light-blocking pattern BML.

[0217] The first electric field line VDL1 can be stacked with the first gap GP1 between the first pad electrode APD and the second pad electrode CPD. The thickness of the first electric field line VDL1 can be greater than the thickness of the lower light-blocking pattern BML. For example, the thickness of the lower light-blocking pattern BML can be approximately 500 Å to 1,500 Å, and the thickness of the first electric field line VDL1 can be approximately 2,500 Å or greater. Therefore, even if the lower light-blocking pattern BML is formed to have a thickness of less than 3,000 Å, the light emitted from the light-emitting element EL disposed on the first pad electrode APD and the second pad electrode CPD that travels in the downward direction of the display panel 100 through the first gap GP1 can be blocked by the first electric field line VDL1 and the lower light-blocking pattern BML.

[0218] The first electric field line VDL1 may extend in the second direction DR2. The maximum width Wvdl1 of the first electric field line VDL1 may be greater than the maximum width Wgp1 of the first gap GP1. For example, each of the distance L1 between one side of the first electric field line VDL1 and the side of the first gap GP1 adjacent to that side of the first electric field line VDL1, and the distance L2 between the other side of the first electric field line VDL1 and the other side of the first gap GP1 adjacent to that side of the first electric field line VDL1, may be at least 5 μm or greater.

[0219] Furthermore, the light-blocking pattern BP can be stacked with the second gap GP2 between the first pad electrode APD and the third electric field line VSL, and the third gap GP3 between the second pad electrode CPD and the third electric field line VSL. The thickness of the light-blocking pattern BP can be greater than the thickness of the lower light-blocking pattern BML. For example, the thickness of the lower light-blocking pattern BML can be approximately 500 Å to 1,500 Å, and the thickness of the light-blocking pattern BP can be approximately 2,500 Å or greater. Therefore, even if the lower light-blocking pattern BML is formed to have a thickness of less than 3,000 Å, the light emitted from the light-emitting element EL disposed on the first pad electrode APD and the second pad electrode CPD, traveling in the downward direction of the display panel 100 through the second gap GP2 and the third gap GP3, can be blocked by the light-blocking pattern BP and the lower light-blocking pattern BML.

[0220] The light-blocking pattern BP can have a rectangular frame shape or a rectangular window frame shape in a planar view. The light-blocking pattern BP can be superimposed on the portions where the second pad electrode CPD and the third electric field line VSL are connected to each other.

[0221] The light-blocking pattern BP can be electrically floated. That is, the light-blocking pattern BP does not need to be connected to another electrode and wire.

[0222] The maximum width Wbp of the light-blocking pattern BP can be greater than each of the maximum widths Wgp2 of the second gap GP2 and Wgp3 of the third gap GP3. For example, each of the distance between the outer side of the light-blocking pattern BP and the adjacent side of the second gap GP2 with the same outer side of the light-blocking pattern BP, and the distance between the inner side of the light-blocking pattern BP and the adjacent side of the second gap GP2 with the same inner side of the light-blocking pattern BP, can be at least 5 μm or greater. Additionally, each of the distance L3 between the outer side of the light-blocking pattern BP and the adjacent side of the third gap GP3 with the same outer side of the light-blocking pattern BP, and the distance L4 between the inner side of the light-blocking pattern BP and the adjacent side of the third gap GP3 with the same inner side of the light-blocking pattern BP, can be at least 5 μm or greater.

[0223] In short, such as Figure 8 As shown, the phenomenon that light emitted from the light-emitting element EL is reflected from the lines and device identifier DID disposed on the rear surface of the display panel 100 and is regarded as rear surface reflection can be improved by the first power line VDL1 and the pad light blocking pattern BP.

[0224] Figure 9 It shows along Figure 8 A cross-sectional view of an example display panel taken by line I2-I2'. Figure 10 It shows along Figure 8A cross-sectional view of an example display panel, taken by line I3-I3'. Figure 11 It shows along Figure 8 A cross-sectional view of an example display panel, taken by line I4-I4'.

[0225] Reference Figures 9 to 11 The light-blocking pattern BP can be included in the second gate metal layer. The light-blocking pattern BP can be disposed on the first interlayer insulating film 141. The light-blocking pattern BP can be covered by the second interlayer insulating film 142.

[0226] The light-blocking pattern BP can be superimposed on the third-direction DR3 with the second gap GP2 and the third gap GP3. Therefore, the light emitted from the light-emitting element EL disposed on the first pad electrode APD and the second pad electrode CPD, which travels in the downward direction of the display panel 100 through the second gap GP2 and the third gap GP3, can be blocked by the light-blocking pattern BP.

[0227] The light-blocking pattern BP can be positioned in the area overlapping with the second gap GP2 and the third gap GP3; however, the lower light-blocking pattern BML can be positioned in an area wider than the light-blocking pattern BP. Therefore, the area of ​​the lower light-blocking pattern BML can be larger than the area of ​​the light-blocking pattern BP.

[0228] The first electric field line VDL1 can be disposed at the third source metal layer. The first electric field line VDL1 can be disposed on the second inorganic insulating film 181. The first electric field line VDL1 can be covered by the third planarization film 190.

[0229] The first electric field line VDL1 can be superimposed on the first gap GP1 on the third direction DR3. Therefore, light emitted from the light-emitting element EL disposed on the first pad electrode APD and the second pad electrode CPD that travels in the downward direction of the display panel 100 through the first gap GP1 can be blocked by the first electric field line VDL1.

[0230] Because there is no second gate metal layer stacked with the first pad electrode APD and the second pad electrode CPD along the third direction DR3, therefore... Figures 9 to 11 The light-blocking pattern BP has been shown to be included in the second gate metal layer, but this disclosure is not limited thereto. For example, when there is no first gate metal layer superimposed on the first pad electrode APD and the second pad electrode CPD along the third direction DR3, the light-blocking pattern BP can be included in the first gate metal layer including the gate electrode G17 of the seventeenth transistor T17. Optionally, when there is no first source metal layer superimposed on the first pad electrode APD and the second pad electrode CPD along the third direction DR3, the light-blocking pattern BP can be disposed at the first source metal layer including the first connection electrode CCE1.

[0231] Figure 12 It is a layout diagram showing a first pad electrode, a second pad electrode, a first electric field line, a third electric field line, a first pad light blocking pattern, and a second pad light blocking pattern of a first sub-pixel according to one or more embodiments.

[0232] Figure 12 Implementation examples and Figure 8 The difference in the embodiment is that the light-blocking pattern BP includes a first light-blocking pattern BP1 and a second light-blocking pattern BP2 arranged spaced apart from each other (e.g., separated). Figure 12 In Chinese, omission and Figure 8 The description of the content of the embodiment is repeated.

[0233] Reference Figure 12 The light-blocking pattern BP includes a first light-blocking pattern BP1 superimposed on the first pad electrode APD on the third-direction DR3 and a second light-blocking pattern BP2 superimposed on the second pad electrode CPD on the third-direction DR3.

[0234] The first pad light blocking pattern BP1 can be superimposed on the second gap GP2 between the first pad electrode APD and the third electric field line VSL. The first pad light blocking pattern BP1 can be set along the second gap GP2. The second gap GP2 can be set on the upper, right, and lower sides of the first pad electrode APD, and the first pad light blocking pattern BP1 can be superimposed on the upper, right, and lower sides of the first pad electrode APD on the third-direction DR3.

[0235] The thickness of the first light-blocking pattern BP1 can be greater than the thickness of the lower light-blocking pattern BML. For example, the thickness of the lower light-blocking pattern BML can be approximately 500 Å to 1,500 Å, and the thickness of the first light-blocking pattern BP1 can be approximately 2,500 Å or greater. Therefore, even if the lower light-blocking pattern BML is formed to have a thickness of less than 3,000 Å, the light emitted from the light-emitting element EL disposed on the first pad electrode APD and the second pad electrode CPD, traveling in the downward direction of the display panel 100 through the second gap GP2, can be blocked by the first light-blocking pattern BP1 and the lower light-blocking pattern BML.

[0236] The maximum width Wbp1 of the first light-blocking pattern BP1 can be greater than the maximum width Wgp2 of the second gap GP2. For example, each of the distance L11 between the outer side of the first light-blocking pattern BP1 and the side of the second gap GP2 adjacent to the outer side of the first light-blocking pattern BP1, and the distance L12 between the inner side of the first light-blocking pattern BP1 and the other side of the second gap GP2 adjacent to the inner side of the first light-blocking pattern BP1, can be at least 5 μm or greater.

[0237] The second pad light blocking pattern BP2 can be superimposed on the third gap GP3 between the second pad electrode CPD and the third electric field line VSL. The second pad light blocking pattern BP2 can be set along the third gap GP3. The third gap GP3 can be set on the upper, right, and lower sides of the second pad electrode CPD, and the second pad light blocking pattern BP2 can be superimposed on the upper, right, and lower sides of the second pad electrode CPD on the third direction DR3.

[0238] The thickness of the second light-blocking pattern BP2 can be greater than the thickness of the lower light-blocking pattern BML. For example, the thickness of the lower light-blocking pattern BML can be approximately 500 Å to 1,500 Å, and the thickness of the second light-blocking pattern BP2 can be approximately 2,500 Å or greater. Therefore, even if the lower light-blocking pattern BML is formed to have a thickness of less than 3,000 Å, the light emitted from the light-emitting element EL disposed on the first pad electrode APD and the second pad electrode CPD, traveling in the downward direction of the display panel 100 through the third gap GP3, can be blocked by the second light-blocking pattern BP2 and the lower light-blocking pattern BML.

[0239] The second pad light-blocking pattern BP2 can be superimposed on the portion where the second pad electrode CPD and the third electric field line VSL are connected to each other.

[0240] The maximum width Wbp2 of the second light-blocking pattern BP2 can be greater than the maximum width Wgp3 of the third gap GP3. For example, each of the following distances can be at least 5 μm or greater: the distance L21 between the outer side of the second light-blocking pattern BP2 and the side of the third gap GP3 adjacent to the outer side of the second light-blocking pattern BP2; and the distance L22 between the inner side of the second light-blocking pattern BP2 and the other side of the third gap GP3 adjacent to the inner side of the second light-blocking pattern BP2.

[0241] Furthermore, the first light-blocking pattern BP1 and the second light-blocking pattern BP2 are spaced apart from each other (e.g., separated), but the gap between the first light-blocking pattern BP1 and the second light-blocking pattern BP2 overlaps with the first electric field line VDL1 on the third-direction DR3. Therefore, light emitted from the light-emitting element EL disposed on the first pad electrode APD and the second pad electrode CPD that travels in the downward direction of the display panel 100 through the gap between the first light-blocking pattern BP1 and the second light-blocking pattern BP2 can be blocked by the first electric field line VDL1.

[0242] In short, such as Figure 12As shown, the phenomenon that light emitted from the light-emitting element EL is reflected from the lines and device identifier DID disposed on the rear surface of the display panel 100 and is regarded as rear surface reflection can be improved by the first power line VDL1 and the pad light blocking pattern BP.

[0243] The first light-blocking pattern BP1 and the second light-blocking pattern BP2 can be electrically floated. That is, the first light-blocking pattern BP1 and the second light-blocking pattern BP2 can be independent of other electrodes and wires.

[0244] Because the first light-blocking pattern BP1 and the second light-blocking pattern BP2 are set to be spaced apart from each other (e.g., separated), the area of ​​the first light-blocking pattern BP1 and the area of ​​the second light-blocking pattern BP2 can each be smaller than 1 / 2. Figure 8 The area of ​​the light-blocking pattern BP.

[0245] Because the area of ​​the first light-blocking pattern BP1 is smaller than Figure 8 The area of ​​the light-blocking pattern BP is such that the size of the parasitic capacitance formed on the third-direction DR3 by the superposition between the first light-blocking pattern BP1 and another electrode or line can be smaller than that formed by the light-blocking pattern BP1. Figure 8 The size of the parasitic capacitance formed by the overlap between the first light-blocking pattern BP1 and another electrode or line is reduced. Therefore, the influence of the parasitic capacitance of the first light-blocking pattern BP1 on the other electrode or line overlapped with the first light-blocking pattern BP1 on the third-direction DR3 can be reduced.

[0246] Additionally, because the area of ​​the second light-blocking pattern BP2 is smaller than... Figure 8 The area of ​​the light-blocking pattern BP is such that the parasitic capacitance formed on the third-direction DR3 by the superposition between the second light-blocking pattern BP2 and another electrode or line can be smaller than that formed by the light-blocking pattern BP2. Figure 8 The size of the parasitic capacitance formed by the superposition between the second light-blocking pattern BP2 and another electrode or line is reduced. Therefore, the influence of the parasitic capacitance of the second light-blocking pattern BP2 on the other electrode or line superimposed with the second light-blocking pattern BP2 on the third-direction DR3 can be reduced.

[0247] Along Figure 12 The cross-section of the display panel taken by line I5-I5' and along Figure 8 The cross-sections of the display panel intercepted by line I2-I2' are essentially the same. Therefore, the section along... Figure 12 Description of the cross-section of the display panel taken by line I5-I5'.

[0248] Figure 13 It shows along Figure 12 A cross-sectional view of an example display panel taken by line I6-I6'. Figure 14 It shows along Figure 12 A cross-sectional view of an example display panel taken by line I7-I7'.

[0249] Reference Figure 13 and Figure 14 The first light-blocking pattern BP1 and the second light-blocking pattern BP2 may be included in the second gate metal layer. The first light-blocking pattern BP1 and the second light-blocking pattern BP2 may be disposed on the first interlayer insulating film 141. The first light-blocking pattern BP1 and the second light-blocking pattern BP2 may be covered by the second interlayer insulating film 142.

[0250] The first light-blocking pattern BP1 and the second light-blocking pattern BP2 can be superimposed on the third-direction DR3 with the second gap GP2 and the third gap GP3, respectively. Therefore, light emitted from the light-emitting element EL disposed on the first pad electrode APD and the second pad electrode CPD that travels in the downward direction of the display panel 100 through the second gap GP2 and the third gap GP3 can be blocked by the first light-blocking pattern BP1 and the second light-blocking pattern BP2.

[0251] The first light-blocking pattern BP1 can be disposed in the region overlapping with the second gap GP2, and the second light-blocking pattern BP2 can be disposed in the region overlapping with the third gap GP3. The lower light-blocking pattern BML can be disposed in a region wider than the first light-blocking pattern BP1 and the second light-blocking pattern BP2. Therefore, the area of ​​the lower light-blocking pattern BML can be larger than the area of ​​the first light-blocking pattern BP1 and the second light-blocking pattern BP2.

[0252] The first electric field line VDL1 can be disposed at the third source metal layer. The first electric field line VDL1 can be disposed on the second inorganic insulating film 181. The first electric field line VDL1 can be covered by the third planarization film 190.

[0253] The first electric field line VDL1 can be superimposed on the first gap GP1 on the third direction DR3. Therefore, light emitted from the light-emitting element EL disposed on the first pad electrode APD and the second pad electrode CPD that travels in the downward direction of the display panel 100 through the first gap GP1 can be blocked by the first electric field line VDL1.

[0254] The gap SU between the first light-blocking pattern BP1 and the second light-blocking pattern BP2 can be superimposed on the first gap GP1, but the first electric field line VDL1 can be superimposed on the gap SU between the first light-blocking pattern BP1 and the second light-blocking pattern BP2. Therefore, even though there is a gap SU between the first light-blocking pattern BP1 and the second light-blocking pattern BP2, the light emitted from the light-emitting element EL disposed on the first pad electrode APD and the second pad electrode CPD that travels in the downward direction of the display panel 100 through the first gap GP1 can be blocked by the first electric field line VDL1.

[0255] Because there is no second gate metal layer stacked with the first pad electrode APD and the second pad electrode CPD along the third direction DR3, therefore... Figures 12 to 14 The first pad light blocking pattern BP1 and the second pad light blocking pattern BP2 have been shown to be included in the second gate metal layer, but this disclosure is not limited thereto. For example, when there is no first gate metal layer superimposed on the first pad electrode APD and the second pad electrode CPD along the third direction DR3, the first pad light blocking pattern BP1 and the second pad light blocking pattern BP2 may be included in the first gate metal layer including the gate electrode G17 of the seventeenth transistor T17. Optionally, when there is no first source metal layer superimposed on the first pad electrode APD and the second pad electrode CPD along the third direction DR3, the first pad light blocking pattern BP1 and the second pad light blocking pattern BP2 may be disposed at the first source metal layer including the first connection electrode CCE1.

[0256] Figure 15 This is a perspective view showing a splicing display device comprising multiple display devices according to one or more embodiments.

[0257] Reference Figure 15 The video wall display device TDIS may include multiple display devices 11, 12, 13, and 14, as well as a seam portion SM. The multiple display devices 11, 12, 13, and 14 may be arranged in a matrix of M rows (M is a positive integer) and N columns (N is a positive integer). For example, the video wall display device TDIS may include a first display device 11, a second display device 12, a third display device 13, and a fourth display device 14.

[0258] The first display device 11 and the second display device 12 can be adjacent to each other in the first direction DR1. The first display device 11 and the third display device 13 can be adjacent to each other in the second direction DR2. The third display device 13 and the fourth display device 14 can be adjacent to each other in the first direction DR1. The second display device 12 and the fourth display device 14 can be adjacent to each other in the second direction DR2.

[0259] However, the number and arrangement of display devices 11, 12, 13 and 14 in the TDIS video wall display system are not limited to... Figure 15 The quantity and arrangement shown. The quantity and arrangement of display devices 11, 12, 13 and 14 in the TDIS video wall display system can be based on display device 10 (see...). Figure 1 The dimensions of each component in the TDI (Translation Components Layout and Display) splicing display device and the shape of the TDI splicing display device are determined.

[0260] Multiple display devices 11, 12, 13 and 14 may have the same size, but this disclosure is not limited thereto. For example, multiple display devices 11, 12, 13 and 14 may have different sizes.

[0261] Each of the plurality of display devices 11, 12, 13, and 14 may have a rectangular shape with a long side and a short side. The plurality of display devices 11, 12, 13, and 14 may have long or short sides that are connected to each other. Some or all of the plurality of display devices 11, 12, 13, and 14 may be located at the edge of the splicing display device TDIS and form one side of the splicing display device TDIS. At least one of the plurality of display devices 11, 12, 13, and 14 may be located at at least one corner of the splicing display device TDIS and may form two adjacent sides of the splicing display device TDIS. At least one of the plurality of display devices 11, 12, 13, and 14 may be surrounded by other display devices.

[0262] Each of the plurality of display devices 11, 12, 13 and 14 can be connected to a reference. Figure 1 The described display device 10 is substantially the same. Therefore, the description of each of the plurality of display devices 11, 12, 13 and 14 is omitted.

[0263] The seam portion SM may include a bonding member or an adhesive member. In this case, multiple display devices 11, 12, 13, and 14 can be connected to each other through the bonding member or adhesive member of the seam portion SM. The seam portion SM may be located between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, between the second display device 12 and the fourth display device 14, and between the third display device 13 and the fourth display device 14.

[0264] Figure 16 It shows in detail Figure 15 A magnified layout diagram of region Y.

[0265] Reference Figure 16In the plan view, the seam portion SM can have a cross shape or a plus (+) shape in the central area of ​​the first display device 11, the second display device 12, the third display device 13, and the fourth display device 14 of the splicing display device TDIS that are adjacent to each other. The seam portion SM can be located between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, between the second display device 12 and the fourth display device 14, and between the third display device 13 and the fourth display device 14.

[0266] The first display device 11 may include first pixels PX1 arranged in a matrix on the first direction DR1 and the second direction DR2 for displaying an image. The second display device 12 may include second pixels PX2 arranged in a matrix on the first direction DR1 and the second direction DR2 for displaying an image. The third display device 13 may include third pixels PX3 arranged in a matrix on the first direction DR1 and the second direction DR2 for displaying an image. The fourth display device 14 may include fourth pixels PX4 arranged in a matrix on the first direction DR1 and the second direction DR2 for displaying an image.

[0267] The minimum distance between adjacent first pixels PX1 in the first direction DR1 can be defined as the first horizontal spacing distance GH1, and the minimum distance between adjacent second pixels PX2 in the first direction DR1 can be defined as the second horizontal spacing distance GH2. The first horizontal spacing distance GH1 and the second horizontal spacing distance GH2 can be substantially the same as each other.

[0268] The seam portion SM can be positioned between a first pixel PX1 and a second pixel PX2 that are adjacent to each other along the first direction DR1. The minimum distance G12 between the first pixel PX1 and the second pixel PX2 that are adjacent to each other along the first direction DR1 can be the sum of the minimum distance GHS1 between the first pixel PX1 and the seam portion SM along the first direction DR1, the minimum distance GHS2 between the second pixel PX2 and the seam portion SM along the first direction DR1, and the width GSM1 of the seam portion SM along the first direction DR1.

[0269] The minimum distance G12, the first horizontal spacing distance GH1, and the second horizontal spacing distance GH2 between adjacent first pixels PX1 and second pixels PX2 in the first direction DR1 can be substantially the same. Therefore, the minimum distance GHS1 between the first pixel PX1 and the seam portion SM in the first direction DR1 can be less than the first horizontal spacing distance GH1, and the minimum distance GHS2 between the second pixel PX2 and the seam portion SM in the first direction DR1 can be less than the second horizontal spacing distance GH2. Furthermore, the width GSM1 of the seam portion SM in the first direction DR1 can be less than either the first horizontal spacing distance GH1 or the second horizontal spacing distance GH2.

[0270] The minimum distance between adjacent third pixels PX3 in the first direction DR1 can be defined as the third horizontal spacing distance GH3, and the minimum distance between adjacent fourth pixels PX4 in the first direction DR1 can be defined as the fourth horizontal spacing distance GH4. The third horizontal spacing distance GH3 and the fourth horizontal spacing distance GH4 can be substantially the same as each other.

[0271] The seam portion SM can be positioned between the third pixel PX3 and the fourth pixel PX4, which are adjacent to each other along the first direction DR1. The minimum distance G34 between the third pixel PX3 and the fourth pixel PX4, which are adjacent to each other along the first direction DR1, can be the sum of the minimum distance GHS3 between the third pixel PX3 and the seam portion SM along the first direction DR1, the minimum distance GHS4 between the fourth pixel PX4 and the seam portion SM along the first direction DR1, and the width GSM1 of the seam portion SM along the first direction DR1.

[0272] The minimum distance G34, the third horizontal spacing distance GH3, and the fourth horizontal spacing distance GH4 between adjacent third pixels PX3 and fourth pixels PX4 in the first direction DR1 can be substantially the same. Therefore, the minimum distance GHS3 between the third pixel PX3 and the seam portion SM in the first direction DR1 can be less than the third horizontal spacing distance GH3, and the minimum distance GHS4 between the fourth pixel PX4 and the seam portion SM in the first direction DR1 can be less than the fourth horizontal spacing distance GH4. Furthermore, the width GSM1 of the seam portion SM in the first direction DR1 can be less than either the third horizontal spacing distance GH3 or the fourth horizontal spacing distance GH4.

[0273] The minimum distance between adjacent first pixels PX1 in the second direction DR2 can be defined as the first vertical spacing distance GV1, and the minimum distance between adjacent third pixels PX3 in the second direction DR2 can be defined as the third vertical spacing distance GV3. The first vertical spacing distance GV1 and the third vertical spacing distance GV3 can be substantially the same as each other.

[0274] The seam portion SM can be positioned between the first pixel PX1 and the third pixel PX3 that are adjacent to each other along the second direction DR2. The minimum distance G13 between the first pixel PX1 and the third pixel PX3 that are adjacent to each other along the second direction DR2 can be the sum of the minimum distance GVS1 between the first pixel PX1 and the seam portion SM along the second direction DR2, the minimum distance GVS3 between the third pixel PX3 and the seam portion SM along the second direction DR2, and the width GSM2 of the seam portion SM along the second direction DR2.

[0275] The minimum distance G13, the first vertical spacing distance GV1, and the third vertical spacing distance GV3 between adjacent first pixels PX1 and third pixels PX3 in the second direction DR2 can be substantially the same. Therefore, the minimum distance GVS1 between the first pixel PX1 and the seam portion SM in the second direction DR2 can be less than the first vertical spacing distance GV1, and the minimum distance GVS3 between the third pixel PX3 and the seam portion SM in the second direction DR2 can be less than the third vertical spacing distance GV3. Furthermore, the width GSM2 of the seam portion SM in the second direction DR2 can be less than either the first vertical spacing distance GV1 or the third vertical spacing distance GV3.

[0276] The minimum distance between adjacent second pixels PX2 in the second direction DR2 can be defined as the second vertical spacing distance GV2, and the minimum distance between adjacent fourth pixels PX4 in the second direction DR2 can be defined as the fourth vertical spacing distance GV4. The second vertical spacing distance GV2 and the fourth vertical spacing distance GV4 can be substantially the same as each other.

[0277] The seam portion SM can be positioned between the second pixel PX2 and the fourth pixel PX4, which are adjacent to each other along the second direction DR2. The minimum distance G24 between the second pixel PX2 and the fourth pixel PX4, which are adjacent to each other along the second direction DR2, can be the sum of the minimum distance GVS2 between the second pixel PX2 and the seam portion SM along the second direction DR2, the minimum distance GVS4 between the fourth pixel PX4 and the seam portion SM along the second direction DR2, and the width GSM2 of the seam portion SM along the second direction DR2.

[0278] The minimum distance G24, the second vertical spacing distance GV2, and the fourth vertical spacing distance GV4 between adjacent second pixels PX2 and fourth pixels PX4 in the second direction DR2 can be substantially the same. Therefore, the minimum distance GVS2 between the second pixel PX2 and the seam portion SM in the second direction DR2 can be less than the second vertical spacing distance GV2, and the minimum distance GVS4 between the fourth pixel PX4 and the seam portion SM in the second direction DR2 can be less than the fourth vertical spacing distance GV4. Furthermore, the width GSM2 of the seam portion SM in the second direction DR2 can be less than either the second vertical spacing distance GV2 or the fourth vertical spacing distance GV4.

[0279] like Figure 16 As shown, in order to prevent the seam portion SM from being seen between images displayed by multiple display devices 11, 12, 13 and 14, the minimum distance between pixels of adjacent display devices can be substantially the same as the minimum distance between pixels of each display device.

[0280] Figure 17 It shows along Figure 16 A cross-sectional view of an example of a splicing display device, taken from line N-N'.

[0281] Reference Figure 17 The first display device 11 includes a first display module DPM1 and a first front cover COV1. The second display device 12 includes a second display module DPM2 and a second front cover COV2.

[0282] Each of the first display module DPM1 and the second display module DPM2 includes a substrate SUB, a seventeenth transistor T17, and a light-emitting element EL. Figure 17 The substrate SUB, the seventeenth transistor T17, and the light-emitting element EL shown are compared with the reference. Figure 7 The substrate SUB, the seventeenth transistor T17, and the light-emitting element EL are essentially the same, so their descriptions are omitted.

[0283] The distance GSUB between the substrate SUB of the first display device 11 and the substrate SUB of the second display device 12 can be greater than the distance GCOV between the first front cover COV1 and the second front cover COV2.

[0284] Each of the first front cover COV1 and the second front cover COV2 may include an adhesive member 51, a light transmittance adjustment layer 52 disposed on the adhesive member 51, and an anti-glare layer 53 disposed on the light transmittance adjustment layer 52.

[0285] The adhesive member 51 of the first front cover COV1 is used to bond the light-emitting element layer of the first display module DPM1 and the first front cover COV1 to each other. The adhesive member 51 of the second front cover COV2 is used to bond the light-emitting element layer of the second display module DPM2 and the second front cover COV2 to each other. The adhesive member 51 can be a transparent adhesive component that allows light to pass through. For example, the adhesive member 51 can be an optically transparent adhesive film or an optically transparent resin.

[0286] The anti-glare layer 53 can be designed to diffuse external light to prevent degradation of image visibility caused by the undiminished reflection of external light. Therefore, the contrast of the images displayed by the first display device 10 and the second display device 20 can be increased due to the anti-glare layer 53.

[0287] The transmittance adjustment layer 52 can be designed to reduce the transmittance of external light or light reflected from the first display module DPM1 and the second display module DPM2. For this purpose, the distance GSUB between the substrate SUB of the first display module DPM1 and the substrate SUB of the second display module DPM2 can be prevented from being seen from the outside.

[0288] The anti-glare layer 53 can be implemented as a polarizing plate, and the transmittance adjustment layer 52 can be implemented as a phase delay layer, but this disclosure is not limited thereto.

[0289] Along Figure 16 Examples and references of splicing display devices using lines O-O', P-P', and Q-Q'. Figure 17 The example of a splicing display device cut along line N-N' is essentially the same, so its description is omitted.

[0290] However, it should be understood that the aspects and features of the embodiments of this disclosure are not limited to those set forth herein. The above and other aspects of this disclosure will become more apparent to those skilled in the art to which this disclosure pertains by referring to the claims and their equivalents, which will be included therein.

Claims

1. A display device, characterized in that, The display device includes: Base; A first pad electrode is disposed on the substrate; The second pad electrode is spaced apart from the first pad electrode on the substrate; The light-emitting element includes a first electrode connected to the first pad electrode and a second electrode connected to the second pad electrode; A first electric field line, spaced apart from the first pad electrode on the substrate, is connected to a first side of the second pad electrode and configured to receive a first source voltage; and The light-blocking pattern is superimposed on the first gap between the first pad electrode and the first electric field line and the second gap between the second pad electrode and the first electric field line.

2. The display device according to claim 1, characterized in that, The display device further includes a second power line, which is superimposed on a third gap between the first pad electrode and the second pad electrode, and is configured to receive a second source voltage.

3. The display device according to claim 1, characterized in that, The display device further includes a lower light blocking pattern, which is superimposed on the pad light blocking pattern in the thickness direction of the substrate.

4. The display device according to claim 3, characterized in that, The area of ​​the lower light blocking pattern is larger than the area of ​​the pad light blocking pattern.

5. The display device according to claim 3, characterized in that, The thickness of the lower light blocking pattern is less than the thickness of the pad light blocking pattern.

6. The display device according to claim 1, characterized in that, The light-blocking pattern includes: A first light-blocking pattern is superimposed on the first gap; and The second light-blocking pattern is superimposed on the second gap and spaced apart from the first light-blocking pattern.

7. The display device according to claim 6, characterized in that, The display device also includes a second power line configured to receive a second source voltage.

8. The display device according to claim 7, characterized in that, The second electric field line is superimposed on the third gap between the first pad electrode and the second pad electrode.

9. An electronic device, the electronic device comprising a display device, characterized in that, The display device includes: Base; A first pad electrode is disposed on the substrate; The second pad electrode is spaced apart from the first pad electrode on the substrate; The light-emitting element includes a first electrode connected to the first pad electrode and a second electrode connected to the second pad electrode; A first electric field line, spaced apart from the first pad electrode on the substrate, is connected to a first side of the second pad electrode and is configured to receive a first source voltage; A light-blocking pattern is superimposed on a first gap between the first pad electrode and the first electric field line, and a second gap between the second pad electrode and the first electric field line; and The light-blocking pattern is superimposed on the light-blocking pattern in the thickness direction of the substrate.

10. The electronic device according to claim 9, characterized in that, The electronic devices include televisions, laptops, monitors, billboards, Internet of Things devices, mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players, navigation devices, or ultra-mobile PCs.

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