A power factor correction integrated device

Abstract

The utility model discloses a kind of power factor correction integrated devices, belong to semiconductor technical field, including DBC board, IGBT chip, first FRD chip, second FRD chip, plastic package and multiple pins, IGBT chip, first FRD chip and second FRD chip are all welded and fixed on conductive copper foil, plastic package is wrapped in DBC board, IGBT chip, first FRD chip and second FRD chip inside and constitutes integrated device, plastic package back is equipped with the heat conduction hole compatible with heat conduction copper foil, heat conduction copper foil is located in heat conduction hole, and heat conduction copper foil and plastic package back are located in the same plane;Each pin is welded on conductive copper foil.The utility model one is to solve the problem that the existing discrete device leads to PCB board area of occupation, power factor correction circuit integration is poor;Two is to solve the problem that the existing discrete device structure is complex, and the device heat dissipation performance is not good, manufacturing cost is high due to long heat dissipation path.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor technology, and specifically relates to a power factor correction integrated device. Background Technology

[0002] Power factor correction (PFC) circuits, as core modules for improving energy efficiency and reducing harmonic pollution, have become crucial for technological upgrades across various industries through performance optimization. From smart home appliances and laptop power supplies in the consumer electronics sector to inverters and charging piles for new energy vehicles in industrial manufacturing, PFC circuits achieve efficient energy conversion through current shaping technology, significantly improving equipment energy efficiency.

[0003] At the core component level of power factor correction circuits, insulated gate bipolar transistor (IGBT) chips and fast recovery diode (FRD) chips undertake the core functions of switching control and freewheeling protection. However, the current mainstream molded discrete device architecture is gradually becoming a constraint on technological development. On the one hand, the independent packaging of IGBT and FRD chips results in a dispersed PCB layout, which not only occupies a large amount of board space, increases the size and weight of the device, but also limits the improvement of circuit integration, making it difficult to meet the market demand for miniaturization and lightweighting. On the other hand, the bottleneck of heat dissipation performance is becoming increasingly prominent. Taking the FRD device disclosed in CN202405247U as an example, the low thermal conductivity (approximately 0.2 W / m·K) of the epoxy substrate severely hinders the heat conduction of the chip, causing the junction temperature to rise rapidly and the long-term reliability of the device to decrease. Although the IGBT package structure disclosed in CN222106688U adopts a multi-layer heat dissipation component, the complex design of silicone grease, thermal pads and release holes not only significantly increases the manufacturing cost, but also reduces the heat dissipation efficiency due to the accumulation of thermal resistance, failing to meet the heat dissipation requirements of high power density application scenarios.

[0004] The existence of the aforementioned technical problems urgently requires innovative packaging technology and structural design to overcome the dual limitations of existing discrete devices in terms of integration and heat dissipation performance, and to promote the development of PFC circuits towards high integration and high efficiency. Utility Model Content

[0005] To overcome the aforementioned problems in the prior art, this utility model provides an integrated power factor correction device. Firstly, it addresses the issue of large PCB board area and poor integration of the power factor correction circuit due to the discrete packaging of existing IGBT and FRD chips. Secondly, it solves the problems of poor thermal conductivity of existing FRD devices due to their epoxy base and poor heat dissipation performance and high manufacturing cost caused by the complex design and long heat dissipation paths of existing IGBT packaging structures. The aim is to achieve high integration and good heat dissipation of the power factor correction device through an innovative packaging structure.

[0006] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0007] A power factor correction integrated device, comprising:

[0008] DBC board, including ceramic board, with thermally conductive copper foil fixed on the back of the ceramic board, and first conductive copper foil, second conductive copper foil, first transition copper foil, second transition copper foil and third transition copper foil fixed on the front of the ceramic board respectively.

[0009] An IGBT chip includes a base G, an emitter E, and a collector C. The collector C is soldered and fixed on a first conductive copper foil. The base G and the emitter E are electrically connected to a first transition copper foil and a second transition copper foil, respectively.

[0010] The first FRD chip has its negative electrode soldered and fixed on the first conductive copper foil, and its positive electrode is electrically connected to the second transition copper foil.

[0011] The negative electrode of the second FRD chip is soldered and fixed on the second conductive copper foil, and the positive electrode of the second FRD chip is electrically connected to the third transition copper foil.

[0012] The molding compound encapsulates the DBC board, IGBT chip, first FRD chip and second FRD chip to form an integrated device. The back of the molding compound has thermally conductive holes that are adapted to the thermally conductive copper foil. The thermally conductive copper foil is located in the thermally conductive holes and is on the same plane as the back of the molding compound.

[0013] The device has multiple pins, with one end of each pin soldered onto a first conductive copper foil, a second conductive copper foil, a first adapter copper foil, a second adapter copper foil, and a third adapter copper foil, respectively. The other end of each pin extends out of the encapsulation.

[0014] The pins include a G pin, an E pin, a C pin, a positive pin, and a negative pin, all located at the bottom of the DBC board. The G pin, E pin, and positive pin are respectively soldered and fixed on the first, second, and third transition copper foils, and the C pin and negative pin are respectively soldered and fixed on the first and second conductive copper foils.

[0015] The first conductive copper foil and the second conductive copper foil are arranged side by side on the upper part of the ceramic plate, and the first transition copper foil, the second transition copper foil and the third transition copper foil are arranged side by side on the lower part of the ceramic plate. The right side of the first conductive copper foil and the right side of the second conductive copper foil are respectively provided with a first extension and a second extension extending towards the lower part of the ceramic plate, and the C electrode pin and the negative electrode pin are respectively welded and fixed on the first extension and the second extension.

[0016] The first extension is located between the second and third transition copper foils, and the second extension is located to the right of the third transition copper foil.

[0017] The first adapter copper foil is electrically connected to the base G via a straight copper sheet, the third adapter copper foil is electrically connected to the second FRD chip via a straight copper sheet, and the second adapter copper foil is electrically connected to the emitter E and the first FRD chip via a T-shaped copper sheet.

[0018] The area of ​​the thermally conductive copper foil is smaller than that of the ceramic plate. There are blank areas on the back of the ceramic plate that are not covered by the thermally conductive copper foil, and these blank areas are covered by a plastic sealant.

[0019] A positioning area is provided between the first conductive copper foil and the second conductive copper foil on the front side of the ceramic plate. The positioning area forms a positioning hole after the molding body is encapsulated.

[0020] The encapsulation body has a through-hole for mounting.

[0021] The mounting hole is located in the middle area of ​​the upper part of the encapsulation.

[0022] The minimum length and width of the encapsulated body are 16mm and 21mm.

[0023] Compared with the prior art, the beneficial effects of this utility model are as follows:

[0024] 1. Improved integration and reduced space occupation: By integrating the IGBT chip, the first FRD chip, and the second FRD chip onto the DBC board and unifying them with a plastic package, the minimum length of the plastic package can reach 16mm*21mm. This changes the traditional form of independent packaging for discrete components. This integration method significantly reduces the layout space on the PCB board, allowing the chips to be arranged closely, effectively reducing the area occupied by the components on the PCB board, improving the integration of the power factor correction circuit, meeting the development needs of miniaturization and lightweighting of electronic devices, and providing the possibility for compact design of equipment.

[0025] 2. Improved device stability and reliability: By using a molding compound to cover the blank area around the ceramic plate, the molding compound can be used to fix the DBC board from both sides, thereby ensuring that the components are stably fixed in the molding compound and effectively improving the reliability of the integrated device.

[0026] 3. Optimized heat dissipation performance: The ceramic plate of the DBC board has excellent insulation and high thermal conductivity, which, together with the thermally conductive copper foil, can quickly conduct the heat generated by the chip to the heat sink. Thermally conductive holes adapted to the thermally conductive copper foil are opened on the back of the molding compound, ensuring that the thermally conductive copper foil and the back of the molding compound are on the same plane. This reduces thermal resistance in the heat dissipation path and significantly improves heat dissipation efficiency compared to traditional epoxy substrates or complex heat dissipation components. The heat generated by the chip can be quickly conducted to the heat sink through the DBC board, effectively reducing the chip junction temperature, ensuring the reliability and stability of the device under high power operation, and extending the device's lifespan.

[0027] 4. Simplified structure and reduced cost: Eliminating the complex designs of thermal paste, heat-conducting sheets, and heat dissipation holes found in existing IGBT packaging structures, this integrated device achieves heat dissipation through a simple and efficient DBC board and heat-conducting hole design, simplifying the overall structure. Simultaneously, integrated packaging reduces the materials and process steps required for individual packaging of discrete devices, lowering material and processing costs in the production process, improving production efficiency, and making the product more cost-competitive in the market.

[0028] 5. Facilitates electrical connection and structural installation: The rational pin layout clearly distinguishes the G, E, C, positive, and negative pins, which are soldered to their respective copper foils. This ensures the accuracy and stability of the connection between the device and external circuits, facilitating circuit design and assembly. Furthermore, the mounting holes on the plastic package facilitate the installation and fixation of the integrated device in equipment, enhancing the versatility and flexibility of device installation. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the planar structure of the front of the power factor correction integrated device;

[0030] Figure 2 for Figure 1 A schematic diagram of the left-side cross-sectional structure;

[0031] Figure 3 A schematic diagram of the planar structure on the back of a rate factor correction integrated device;

[0032] Figure 4 This is a schematic diagram of the three-dimensional structure of a rate factor correction integrated device.

[0033] The markings in the diagram are as follows: 1. DBC board, 2. Ceramic plate, 3. Thermally conductive copper foil, 4. First conductive copper foil, 5. Second conductive copper foil, 6. First adapter copper foil, 7. Second adapter copper foil, 8. Third adapter copper foil, 9. IGBT chip, 10. First FRD chip, 11. Second FRD chip, 12. Molded package, 13. Thermal via, 14. Gate pin, 15. Exit pin, 16. Collector pin, 17. Positive pin, 18. Negative pin, 19. First extension, 20. Second extension, 21. T-shaped copper sheet, 22. Positioning hole, 23. Mounting hole. Detailed Implementation

[0034] like Figure 1-4 As shown, this utility model provides a power factor correction integrated device, comprising:

[0035] DBC board 1 includes a ceramic plate 2. A thermally conductive copper foil 3 is fixed on the back of the ceramic plate 2, and a conductive copper foil is fixed on the front. The conductive copper foil is separated into a first conductive copper foil 4, a second conductive copper foil 5, a first transition copper foil 6, a second transition copper foil 7, and a third transition copper foil 8 that are spaced apart from each other by an etching process.

[0036] The IGBT chip 9 includes a base G, an emitter E, and a collector C. The collector C is soldered and fixed on the first conductive copper foil 4. The base G and the emitter E are electrically connected to the first transition copper foil 6 and the second transition copper foil 7, respectively.

[0037] The first FRD chip 10 has its negative electrode soldered and fixed on the first conductive copper foil 4, and its positive electrode is electrically connected to the second transition copper foil 7.

[0038] The negative electrode of the second FRD chip 11 is soldered and fixed on the second conductive copper foil 5, and the positive electrode of the second FRD chip 11 is electrically connected to the third transition copper foil 8.

[0039] The molding compound 12 encapsulates the DBC board 1, IGBT chip 9, first FRD chip 10 and second FRD chip 11 to form an integrated device. The back of the molding compound 12 is also provided with a heat-conducting hole 13 adapted to the heat-conducting copper foil 3. The heat-conducting copper foil 3 is located in the heat-conducting hole 13 and the heat-conducting copper foil 3 and the back of the molding compound 12 are on the same plane.

[0040] The device has multiple pins. One end of each pin is soldered to the first conductive copper foil 4, the second conductive copper foil 5, the first transition copper foil 6, the second transition copper foil 7, and the third transition copper foil 8, respectively. The other end of each pin extends out of the encapsulation body 12.

[0041] Specifically, such as Figure 1-4As shown, the pins include G pin 14, E pin 15, C pin 16, positive pin 17, and negative pin 18, all located at the lower end of the DBC board 1. G pin 14, E pin 15, and positive pin 17 are respectively soldered and fixed on the first transition copper foil 6, the second transition copper foil 7, and the third transition copper foil 8. C pin 16 and negative pin 18 are respectively soldered and fixed on the first conductive copper foil 4 and the second conductive copper foil 5.

[0042] It should be noted that the present invention can select chips with different voltages and currents according to specific business scenarios. For example, the commonly used chip is the 20A IGBT chip 9, which can be paired with a 20A first FRD chip 10 and a 10A second FRD chip 11. The chip parameters can be adjusted according to the needs of different circuits.

[0043] In this embodiment, as Figure 1 As shown, the first adapter copper foil 6 is electrically connected to the base G via a straight copper strip, the third adapter copper foil 8 is electrically connected to the second FRD chip 11 via a straight copper strip, and the second adapter copper foil 7 is electrically connected to the emitter E and the first FRD chip 10 via a T-shaped copper strip 21. Specifically, the two ends of the straight copper strip between the first adapter copper foil 6 and the base G are respectively soldered and fixed to the first adapter copper foil 6 and the base G. The two ends of the straight copper strip between the third adapter copper foil 8 and the second FRD chip 11 are respectively soldered and fixed to the third adapter copper foil 8 and the second FRD chip 11. One end of the T-shaped copper strip 21 is soldered and fixed to the second adapter copper foil 7, and the other end of the T-shaped part is soldered and fixed to the emitter E and the first FRD chip 10, thereby achieving a stable connection between each chip and the pin.

[0044] In this embodiment, as Figure 1-4 As shown, the molding compound 12 is also provided with a mounting hole 23 that penetrates the molding compound 12. The mounting hole 23 is located in the middle area of ​​the upper part of the molding compound 12, which facilitates the rapid assembly of the device.

[0045] In this embodiment, as Figure 1 , 4 As shown, a positioning area is provided between the first conductive copper foil 4 and the second conductive copper foil 5 on the front side of the ceramic plate 2. After the molding body 12 is molded, the positioning area forms a positioning hole 22. The positioning area facilitates positioning during the molding of the device, which can improve the accuracy of device molding and the product qualification rate.

[0046] In a preferred embodiment, such as Figure 1As shown, the first conductive copper foil 4 and the second conductive copper foil 5 are arranged side by side on the upper part of the ceramic plate 2, and the first transition copper foil 6, the second transition copper foil 7, and the third transition copper foil 8 are arranged side by side on the lower part of the ceramic plate 2. The right side of the first conductive copper foil 4 and the right side of the second conductive copper foil 5 are respectively provided with a first extension 19 and a second extension 20 extending towards the lower part of the ceramic plate 2. The first extension 19 is located between the second transition copper foil 7 and the third transition copper foil 8, and the second extension 20 is located to the right of the third transition copper foil 8. The collector pin 16 and the negative pin 18 are respectively soldered and fixed to the first extension 19 and the second extension 20. Through reasonable layout, the minimum length and width of the molding compound 12 can reach 16mm*21mm, while in the prior art, the length and width of the molding compound 12 after packaging a single IGBT device is 20×16mm, and the length and width of the molding compound 12 after packaging a single FRD device is 15×10mm. As can be seen from the comparison, this embodiment effectively improves the integration of the device and reduces the size of the device, which is more conducive to improving assembly efficiency, simplifying assembly process, reducing assembly cost, and saving assembly resources.

[0047] In a preferred embodiment, such as Figure 1 As shown, the area of ​​the thermally conductive copper foil 3 is smaller than the area of ​​the ceramic plate 2. There are blank areas around the back of the ceramic plate 2 that are not covered by the thermally conductive copper foil 3, and these blank areas are covered by the molding compound 12. Correspondingly, there are also blank areas around the front of the ceramic plate 2 that are not covered by the conductive copper foil, and these blank areas are also covered by the molding compound 12. Based on this structure, the front and back edges of the ceramic plate 2 are clamped and fixed by the molding compound 12, which is equivalent to stably embedding and fixing the ceramic plate 2 into the molding compound 12, thereby improving the structural strength and stability of the device.

[0048] The installation process of this utility model is as follows:

[0049] 1. Clean the surface of the conductive copper foil on the front side of DBC board 1 to ensure that there is no oil or impurities on the surface of the conductive copper foil for subsequent soldering.

[0050] 2. Accurately place the collector C of the IGBT chip 9 in the welding area of ​​the first conductive copper foil 4, and use a vacuum sintering process to melt the solder to achieve a firm weld between the IGBT chip 9 and the first conductive copper foil 4; then weld copper sheets between the base G of the IGBT chip 9 and the first transition copper foil 6 and between the emitter E and the second transition copper foil 7 to achieve electrical connection.

[0051] 3. Following the same welding process, the negative electrode of the first FRD chip 10 is welded to the first conductive copper foil 4, and the positive electrode is electrically connected to the second transition copper foil 7 through a copper sheet; the negative electrode of the second FRD chip 11 is welded to the second conductive copper foil 5, and the positive electrode is electrically connected to the third transition copper foil 8 through a copper sheet.

[0052] 4. Solder and fix each pin onto the first conductive copper foil 4, the second conductive copper foil 5, the first transition copper foil 6, the second transition copper foil 7, and the third transition copper foil 8 respectively. Place the DBC board 1 with the soldered chip and pins into the pre-designed mold, and inject epoxy resin material through an injection molding machine to form a complete encapsulation body 12. After injection molding, the back of the encapsulation body 12 has a heat-conducting hole 13 that matches the heat-conducting copper foil 3. The heat-conducting copper foil 3 is located in the heat-conducting hole 13, and the heat-conducting copper foil 3 and the back of the encapsulation body 12 are on the same plane, thus completing the fabrication of the power factor correction integrated device.

[0053] In use, the thermally conductive copper foil 3 can be directly welded and fixed to the heat sink, which enables the heat generated by each chip to be dissipated in a timely and uniform manner through the ceramic plate 2 and the thermally conductive copper foil 3. Its structure is simpler and the heat dissipation path is shorter, which effectively improves the heat dissipation performance of the device.

[0054] In addition, temperature tests conducted under the same operating conditions show that the operating temperature of the integrated device provided by this invention is basically the same as that of an existing single independent module. This is due to the excellent heat dissipation capability of the DBC board. Therefore, after integration, this invention also has the advantage of good heat dissipation.

[0055] In addition, based on the structure of using a DBC board and embedding the DBC board into a molded enclosure, the applicant also conducted drop tests on the integrated devices. The test process was as follows: 50 integrated devices were selected and dropped freely 10 times from a height of 1.5 meters. After testing, the outer surface of the molded enclosure of all integrated devices showed no cracks or missing corners, and the electrical parameters did not change. This proves that the integrated devices provided by this utility model have higher mechanical strength and better stability and reliability.

[0056] The above description is only a specific embodiment of the present utility model. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All features or steps in all methods or processes disclosed may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A power factor correction integrated device, characterized in that... include: DBC board (1) includes a ceramic board (2), with a thermally conductive copper foil (3) fixed on the back of the ceramic board (2), and a first conductive copper foil (4), a second conductive copper foil (5), a first transition copper foil (6), a second transition copper foil (7) and a third transition copper foil (8) fixed on the front side respectively. The IGBT chip (9) includes a base G, an emitter E and a collector C. The collector C is soldered and fixed on the first conductive copper foil (4). The base G and the emitter E are electrically connected to the first transition copper foil (6) and the second transition copper foil (7), respectively. The first FRD chip (10) has its negative electrode soldered and fixed on the first conductive copper foil (4), and its positive electrode is electrically connected to the second transfer copper foil (7). The negative electrode of the second FRD chip (11) is soldered and fixed on the second conductive copper foil (5), and the positive electrode of the second FRD chip (11) is electrically connected to the third transfer copper foil (8). The molding compound (12) encapsulates the DBC board (1), IGBT chip (9), first FRD chip (10) and second FRD chip (11) to form an integrated device. The back of the molding compound (12) is provided with a heat-conducting hole (13) that is compatible with the heat-conducting copper foil (3). The heat-conducting copper foil (3) is located in the heat-conducting hole (13), and the heat-conducting copper foil (3) and the back of the molding compound (12) are on the same plane. The pins are numerous, with one end of each pin soldered onto the first conductive copper foil (4), the second conductive copper foil (5), the first adapter copper foil (6), the second adapter copper foil (7), and the third adapter copper foil (8), respectively. The other end of each pin extends out of the encapsulation body (12).

2. The power factor correction integrated device according to claim 1, characterized in that: The pins include a G pin (14), an E pin (15), a C pin (16), a positive pin (17), and a negative pin (18), all located at the lower end of the DBC board (1). The G pin (14), E pin (15), and positive pin (17) are respectively soldered and fixed on the first adapter copper foil (6), the second adapter copper foil (7), and the third adapter copper foil (8). The C pin (16) and negative pin (18) are respectively soldered and fixed on the first conductive copper foil (4) and the second conductive copper foil (5).

3. The power factor correction integrated device according to claim 2, characterized in that: The first conductive copper foil (4) and the second conductive copper foil (5) are arranged side by side on the upper part of the ceramic plate (2), and the first transition copper foil (6), the second transition copper foil (7) and the third transition copper foil (8) are arranged side by side on the lower part of the ceramic plate (2). The right side of the first conductive copper foil (4) and the right side of the second conductive copper foil (5) are respectively provided with a first extension (19) and a second extension (20) extending towards the lower part of the ceramic plate (2), and the C electrode pin (16) and the negative electrode pin (18) are respectively welded and fixed on the first extension (19) and the second extension (20).

4. The power factor correction integrated device according to claim 3, characterized in that: The first extension (19) is located between the second transition copper foil (7) and the third transition copper foil (8), and the second extension (20) is located to the right of the third transition copper foil (8).

5. The power factor correction integrated device according to claim 1, characterized in that: The first adapter copper foil (6) is electrically connected to the base G through a straight copper sheet, the third adapter copper foil (8) is electrically connected to the second FRD chip (11) through a straight copper sheet, and the second adapter copper foil (7) is electrically connected to the emitter E and the first FRD chip (10) through a T-shaped copper sheet (21).

6. A power factor correction integrated device according to any one of claims 1-5, characterized in that: The area of ​​the thermally conductive copper foil (3) is smaller than that of the ceramic plate (2). There is a blank area on the back of the ceramic plate (2) that is not covered by the thermally conductive copper foil (3), and the blank area is covered by the encapsulant (12).

7. The power factor correction integrated device according to claim 1, characterized in that: A positioning area is provided between the first conductive copper foil (4) and the second conductive copper foil (5) on the front side of the ceramic plate (2). The positioning area forms a positioning hole (22) after the plastic sealant (12) is sealed.

8. The power factor correction integrated device according to claim 1, characterized in that: The encapsulation body (12) has an installation hole (23) that penetrates the encapsulation body (12).

9. A power factor correction integrated device according to claim 8, characterized in that: The mounting hole (23) is located in the middle area of ​​the upper part of the encapsulation body (12).

10. A power factor correction integrated device according to claim 3, characterized in that: The minimum length and width of the encapsulated body (12) are 16mm*21mm.

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