A burn-in system for digital signal processing chips

Abstract

The utility model discloses a kind of digital signal processing chip's aging system, it is mainly composed of aging board, a plurality of BGA fixture installation ports are equipped on the aging board, and the digital signal processing chip to be aged is then built-in in the BGA fixture installation port etc.The utility model's function covers comprehensively, the addressing function of digital signal processing chip to be aged, ROM / RAM function, boot loading function, FIR function, FFT function, timer function etc. can be carried out comprehensive aging test to different GPIO pin state by being set, cover the core function module of chip, improve the function coverage of aging test.

Description

Technical Field

[0001] This utility model relates to the field of chip aging technology, specifically to an aging system for digital signal processing chips. Background Technology

[0002] Currently, during chip manufacturing, various potential defects may exist due to different reasons. These defects may not manifest immediately under normal operating conditions, but they can lead to chip failure during long-term use. Therefore, chip aging is a crucial step in the chip manufacturing process. Chip aging, also known as "chip aging test" or "chip burn-in test," aims to identify potential early failure products in advance, thereby improving the reliability of the chip in actual use. Because there are many types of chips, and existing aging systems are designed for chips with simple functions, they are completely unsuitable for complex digital signal processing chips with a large number of pins, such as the TMS320C6713 chip in the TMS320C6000 series, and cannot effectively age them.

[0003] In conclusion, designing and developing a aging system for complex digital signal processing chips is urgently needed. Utility Model Content

[0004] In order to overcome the shortcomings of the existing technology, this utility model proposes a aging system for digital signal processing chips.

[0005] To solve the above-mentioned technical problems, this utility model provides the following technical solution: a digital signal processing chip curing system, mainly composed of a curing board, on which a number of BGA fixture mounting ports are provided. The digital signal processing chip to be cured is built into the BGA fixture mounting ports. The curing board is also provided with a driving circuit and a signal transmission circuit connected to the digital signal processing chip to be cured through the BGA fixture mounting ports, a power supply circuit connected to the digital signal processing chip to be cured, the driving circuit and the signal transmission circuit, and a filtering circuit, a BOOT boot loading circuit, a storage function ROM / RAM circuit and a clock circuit, all connected to the digital signal processing chip to be cured.

[0006] Furthermore, a fuse is connected in series in each electrical circuit on the aging board and connected to the digital signal processing chip to be aged.

[0007] A shorting cap is also provided on the old refining board, and the digital signal processing chip forms GPIO pins through the shorting cap.

[0008] To improve the efficiency of aging tests, the BGA fixture has 8 mounting ports.

[0009] To facilitate the provision of appropriate voltages to different circuits, a level conversion chip with model number SN74CBTD3384PW is provided in the power supply circuit.

[0010] Meanwhile, the aging board is equipped with a 3.3V operating voltage input terminal and a 1.2V operating voltage input terminal that are connected to the digital signal processing chip to be aged.

[0011] Compared with the prior art, this utility model has the following advantages and beneficial effects:

[0012] 1. This utility model has comprehensive functional coverage. By setting different GPIO pin states, it can perform comprehensive aging tests on the addressing function, ROM / RAM function, boot loading function, FIR function, FFT function, timer function, etc. of the digital signal processing chip to be aged, covering the core functional modules of the chip and improving the functional coverage of the aging test.

[0013] 2. This invention offers high aging efficiency. By designing eight independent BGA fixture mounting ports (stations) on the aging board, eight chips can be aged simultaneously. More importantly, each station can perform different or the same functional tests in parallel, significantly improving aging efficiency compared to traditional single-station aging methods.

[0014] 3. This utility model can perform real-time status monitoring and alarm. During the aging process, the working status of each station can be checked in real time. When the working status is abnormal, an audible and visual alarm can be triggered in time to avoid damage to the chip due to long-term operation under abnormal conditions, thereby improving the reliability of aging and the chip yield.

[0015] 4. The hardware design of the utility model is perfect and reliable. The aging board adopts a variety of protection measures, such as 100mA and 500mA fuse overcurrent protection, multi-stage filtering power supply design, and BGA high-precision fixture to ensure good chip contact, which can reduce signal interference and ensure stable circuit operation during the aging process.

[0016] 5. This utility model is easy to operate and maintain. The GPIO pin status is set by the shorting cap, making the operation simple and intuitive. The aging board supports long-term stable operation in high-temperature environments, and test data can be exported to generate reports during the post-processing stage, which is convenient for chip screening and fault location. At the same time, the aging board itself is easy to maintain and can be reused, reducing aging costs. Attached Figure Description

[0017] Figure 1 This is a schematic block diagram of the aging system of this utility model.

[0018] The reference numerals in the attached figures are as follows: 1—Digital signal processing chip to be aged, 2—Driver circuit, 3—Signal transmission circuit, 4—Power supply circuit, 5—Filtering circuit, 6—BOOT boot loading circuit, 7—Memory function ROM / RAM circuit, 8—Clock circuit. Detailed Implementation

[0019] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Those skilled in the art will appreciate that these descriptions are merely descriptive and exemplary and should not be construed as limiting the scope of protection of the present invention.

[0020] Example 1

[0021] like Figure 1 As shown, the curing system in this embodiment mainly consists of a curing board (i.e., a PCB board). This curing board has eight BGA fixture mounting ports. These ports are used to mount the digital signal processing chips 1 to be cured. During testing, the digital signal processing chips 1 to be cured are internally mounted and fixed in these BGA fixture mounting ports. Then, the curing system is started, allowing simultaneous curing of all eight digital signal processing chips 1. These eight BGA fixture mounting ports can also be called workstations, each connected to one digital signal processing chip 1 to be cured. These eight workstations are independent of each other. The curing board of this invention can simultaneously perform curing tests on all eight digital signal processing chips 1. Each workstation can perform different functional tests or the same functional tests in parallel, significantly improving curing efficiency compared to traditional single-workstation curing methods.

[0022] Meanwhile, the aging board also includes a drive circuit 2 and a signal transmission circuit 3, each connected to the digital signal processing chip 1 to be aged via the BGA fixture mounting ports; a power supply circuit 4, connected to the digital signal processing chip 1, drive circuit 2, and signal transmission circuit 3; and a filter circuit 5, a bootloader circuit 6, a storage function ROM / RAM circuit 7, and a clock circuit 8, all connected to the digital signal processing chip 1 to be aged. That is, the drive circuit 2, signal transmission circuit 3, filter circuit 5, bootloader circuit 6, storage function ROM / RAM circuit 7, and clock circuit 8 are all connected to these eight BGA fixture mounting ports, and are connected to the eight digital signal processing chips 1 to be aged via these eight BGA fixture mounting ports.

[0023] The digital signal processing chip 1 to be aged is a TMS320C6713 chip. To ensure the normal operation of the digital signal processing chip 1 and to avoid damage from large currents, a fuse is connected in series in each electrical circuit on the aging board that is connected to the digital signal processing chip 1 to be aged.

[0024] The aging board also has a 3.3V operating voltage input terminal and a 1.2V operating voltage input terminal, which are obtained by the power supply circuit 4 through transformer output. When the digital signal processing chip 1 to be aged is installed in the BGA fixture mounting port, the 3.3V operating voltage input terminal and the 1.2V operating voltage input terminal will provide the digital signal processing chip 1 with the two different operating voltages mentioned above.

[0025] A shorting cap is also provided on the circuit board, through which the digital signal processing chip 1 forms GPIO pins. A shorting cap, when fitted onto two pins on the circuit board (or soldered to two solder joints), electrically connects these two pins using internal conductive components. This effectively forms a conductor in the circuit, allowing current to bypass the original disconnection point or components such as resistors and capacitors, thus achieving a "short circuit" state. By inserting and removing the shorting cap, the circuit's on / off state can be quickly switched without soldering, facilitating debugging and maintenance.

[0026] In this embodiment, the GPIO pins formed by the shorting cap include GP15 to GP11. Depending on the testing requirements, this embodiment can set GP15 to GP11 to 00010 for addressing function aging tests; set GP15 to GP11 to 00011 for ROM / RAM function aging tests; set GP15 to GP11 to 00100 for bootloader function aging tests; set GP15 to GP11 to 00110 for FIR function aging tests; set GP15 to GP11 to 00111 for FFT function aging tests; and set GP15 to GP11 to 01000 for timer function aging tests.

[0027] The driving circuit 2 is used to drive the digital signal processing chip 1 to be aged for testing. If the digital signal processing chip 1 to be aged can drive the storage function ROM / RAM circuit 7 through the driving circuit 2, it indicates that the driving function of the digital signal processing chip 1 to be aged is normal; otherwise, it indicates that its driving function is abnormal.

[0028] The digital signal processing chip 1, which needs aging, requires multiple power supplies and a stable power management circuit. The storage function ROM / RAM circuit 7 integrates an AM29LV400B Flash chip and an MT48LC4M32B2TG SDRAM chip. The AM29LV400B stores non-volatile data such as firmware (e.g., bootloader) and configuration parameters, while the MT48LC4M32B2TG serves as a high-speed data cache (e.g., audio / video frame buffer). The Flash and SDRAM chips share a 3.3V power supply. During operation, it is crucial to ensure consistent address space allocation and input data, prevent the chip's enable pin from floating, and use series resistors and capacitors to address potential signal oscillations and power decoupling issues in the drive circuit 2.

[0029] The signal transmission circuit 3 is used to achieve compatible signal transmission between the chip and peripheral devices through circuits such as level conversion, clock driving or data interface, to ensure stable transmission and reception of test signals during the aging process, thereby completing the aging test of each function of the chip.

[0030] The BOOT loading circuit 6 is used to load the program stored in the ROM / RAM circuit 7 into the on-chip program register and execute it when the digital signal processing chip 1 is powered on. Its core function is to utilize the large space and low data loss characteristics of external memory (such as AM29LV400B FLASH) to store complete system programs and application programs. At the same time, it loads frequently used programs into the on-chip high-speed RAM for execution through boot loading, improving computing efficiency. Meanwhile, it ensures that the related circuits work together through the storage interface, power supply, clock, and GPIO control to achieve the hardening and verification of this function, ensuring that the chip can start and run programs normally in actual applications.

[0031] To ensure the actual performance, a level conversion chip of model SN74CBTD3384PW is also set in the power supply circuit 4 to realize the conversion between 5V and 3.3V levels and ensure signal compatibility between devices with different voltages.

[0032] As described above, this utility model can be implemented quite well.

Claims

1. A aging system for a digital signal processing chip, mainly composed of an aging board, characterized in that, The aging board is provided with a number of BGA fixture mounting ports. The digital signal processing chip (1) to be aged is built into the BGA fixture mounting port. The aging board is also provided with a driving circuit (2) and a signal transmission circuit (3) connected to the digital signal processing chip (1) to be aged through the BGA fixture mounting port, a power supply circuit (4) connected to the digital signal processing chip (1), the driving circuit (2) and the signal transmission circuit (3) to be aged, and a filter circuit (5), a BOOT boot loading circuit (6), a storage function ROM / RAM circuit (7) and a clock circuit (8) all connected to the digital signal processing chip (1) to be aged.

2. The aging system for a digital signal processing chip according to claim 1, characterized in that, A fuse is connected in series in each circuit on the aging board and in each circuit connected to the digital signal processing chip (1) to be aged.

3. The aging system for a digital signal processing chip according to claim 2, characterized in that, A shorting cap is also provided on the old refining board, and the digital signal processing chip (1) forms GPIO pins through the shorting cap.

4. The aging system for a digital signal processing chip according to claim 3, characterized in that, The BGA fixture has 8 mounting ports.

5. The aging system for a digital signal processing chip according to claim 4, characterized in that, A level conversion chip with model number SN74CBTD3384PW is provided in the power supply circuit (4).

6. The aging system for a digital signal processing chip according to claim 3, characterized in that, The aging board has a 3.3V working voltage input terminal and a 1.2V working voltage input terminal connected to the digital signal processing chip (1) to be aged.

Images