A magnetic integrated secondary low-voltage side winding circuit

Abstract

The utility model discloses a kind of magnetic integrated type secondary side low-voltage side winding circuit, it includes primary side full bridge part, secondary side high-voltage side and secondary side low-voltage side, the secondary side low-voltage side is connected with M9NNMOS pipe, M10NNMOS pipe and M12NNMOS pipe in parallel, the secondary side low-voltage side is accessed primary side full bridge part after a plurality of first resistors and a plurality of capacitors are connected in parallel and then with M11NNMOS pipe series connection.In this application, when the NMOS pipe of secondary side high-voltage side opens, the secondary side low-voltage side M11NNMOS pipe is opened simultaneously to reduce winding floating voltage and reduce the voltage stress of M9 and M10 NMOS.

Description

Technical Field

[0001] This utility model relates to a magnetically integrated secondary low-voltage side winding circuit. Background Technology

[0002] Existing magnetic integrated circuit topologies, such as Figure 1 As shown, M1-M4 form the primary side full bridge, M5-M8 form the secondary high-voltage side, M9-M10 form the secondary low-voltage side, M12 is a buck switch, D1 is a buck freewheeling diode, and L7 is a buck energy storage inductor.

[0003] The high-voltage DC side adopts an LC resonant DAB structure, while the low-voltage DC side adopts a full-bridge + buck structure. The high-voltage DC side achieves bidirectional energy flow by controlling the phase shift angle of the primary and secondary sides, while the low-voltage DC side achieves load-regulated output at different phase shift angles through the subsequent BUCK stage.

[0004] When the low-voltage side secondary tube is turned on, because the low-voltage DC side adopts full-wave rectification, M9 and M10 on the low-voltage side of the secondary side bear twice the secondary winding voltage. In addition, the low-voltage side winding of the secondary side will generate floating voltage. Therefore, M9 and M10 bear twice the winding voltage + floating voltage + peak voltage at this time, resulting in greater voltage stress. Utility Model Content

[0005] The main objective of this invention is to provide a magnetically integrated secondary low-voltage side winding circuit, which aims to solve the aforementioned technical problems.

[0006] To achieve the above objectives, this utility model proposes a magnetically integrated secondary low-voltage side winding circuit, which includes a primary full-bridge section, a secondary high-voltage side, and a secondary low-voltage side. The secondary low-voltage side is connected in parallel with M9NNMOS transistors, M10NNMOS transistors, and M12NNMOS transistors. The secondary low-voltage side connects multiple first resistors and multiple capacitors in parallel, and then connects them in series with M11NNMOS transistors before connecting them to the primary full-bridge section.

[0007] In one embodiment, the number of the first resistors is four.

[0008] In one embodiment, the resistance of the first resistor is 10K.

[0009] In one embodiment, the capacitor has a capacitance of 10 nF.

[0010] In one embodiment, the secondary low-voltage side further includes an NPN transistor, the collector of which is connected to the power supply voltage terminal, the emitter of which is grounded, and the base of which is connected to the primary full-bridge section.

[0011] In one embodiment, the magnetically integrated secondary low-voltage side winding circuit further includes a second resistor connected between the collector of the NPN transistor and the power supply voltage terminal.

[0012] In one embodiment, the magnetically integrated secondary low-voltage side winding circuit further includes a third resistor connected between the collector of the NPN transistor and the M11NNMOS transistor.

[0013] In one embodiment, the magnetically integrated secondary low-voltage side winding circuit further includes a fourth resistor connected between the gate and source of the M11NNMOS transistor.

[0014] In one embodiment, a fifth resistor is connected in parallel between the emitter and base of the NPN transistor.

[0015] In one embodiment, the magnetically integrated secondary low-voltage side winding circuit further includes a sixth resistor, which is connected in series with the base of the NPN transistor.

[0016] In this invention, the magnetically integrated secondary low-voltage side winding circuit includes a primary full-bridge section, a secondary high-voltage side, and a secondary low-voltage side. The secondary low-voltage side is connected in parallel with M9NNMOS transistors, M10NNMOS transistors, and M12NNMOS transistors. Multiple first resistors and multiple capacitors are connected in parallel on the secondary low-voltage side, and then connected in series with an M11NNMOS transistor before being connected to the primary full-bridge section. Therefore, in this invention, when the NMOS transistor on the secondary high-voltage side is turned on, the M11NNMOS transistor on the secondary low-voltage side is simultaneously turned on to reduce the winding float voltage and lower the voltage stress on the M9 and M10 NMOS transistors. When the M11NNMOS transistor is turned on, the secondary low-voltage side winding is clamped by a circuit consisting of four first resistors connected in parallel and the M11NNMOS transistor connected in series. These multiple first resistors act as a load on the secondary low-voltage side winding to pull down the winding float voltage, thus solving the problem of float voltage in the secondary low-voltage side winding. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 This is a topology diagram of a magnetically integrated circuit in the prior art;

[0019] Figure 2This is a circuit diagram of the magnetically integrated secondary low-voltage side winding of the first embodiment of this utility model;

[0020] Figure 3 This is a circuit diagram of the magnetically integrated secondary low-voltage side winding of the second embodiment of this utility model.

[0021] Explanation of the symbols in the attached diagram: R2-R5, first resistor; C6-C8, capacitor; R6, second resistor; R7, third resistor; R8, fourth resistor; R9, fifth resistor; R10, sixth resistor.

[0022] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0024] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in this utility model embodiment are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0025] Furthermore, in this utility model, the use of terms such as "first," "second," etc., is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this utility model, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0026] Furthermore, the technical solutions of the various embodiments of this utility model can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0027] Existing magnetic integrated circuit topologies, such as Figure 1As shown, M1-M4 form the primary side full bridge, M5-M8 form the secondary high-voltage side, M9-M10 form the secondary low-voltage side, M12 is a buck switch, D1 is a buck freewheeling diode, and L7 is a buck energy storage inductor.

[0028] The high-voltage DC side adopts an LC resonant DAB structure, while the low-voltage DC side adopts a full-bridge + buck structure. The high-voltage DC side achieves bidirectional energy flow by controlling the phase shift angle of the primary and secondary sides, while the low-voltage DC side achieves load-regulated output at different phase shift angles through the subsequent BUCK stage.

[0029] When the low-voltage side secondary tube is turned on, because the low-voltage DC side adopts full-wave rectification, M9 and M10 on the low-voltage side of the secondary side bear twice the secondary winding voltage. In addition, the low-voltage side winding of the secondary side will generate floating voltage. Therefore, M9 and M10 bear twice the winding voltage + floating voltage + peak voltage at this time, resulting in greater voltage stress.

[0030] This utility model provides a first embodiment, please refer to it. Figure 2 A resistor +NMOS and its driving circuit are connected in parallel on the low-voltage side winding of the secondary side. When the high-voltage side NMOS transistor is turned on, the NMOS transistor M11 connected in parallel on the low-voltage side winding of the secondary side is turned on. This can be understood as the resistor +NMOS being connected in parallel on the low-voltage side winding of the transformer to reduce the voltage stress on the low-voltage side NMOS transistors M9 and M10 caused by the high-voltage side transistor being turned on.

[0031] Please refer to Figure 3 The present invention provides a second embodiment in which a magnetically integrated secondary low-voltage side winding circuit includes a primary full-bridge section, a secondary high-voltage side, and a secondary low-voltage side. The secondary low-voltage side is connected in parallel with M9NNMOS transistors, M10NNMOS transistors, and M12NNMOS transistors. The secondary low-voltage side connects four 10K first resistors (R2-R5) and three 10nF capacitors (C6-C8) in parallel, and then connects them in series with M11NNMOS transistors to the primary full-bridge section.

[0032] In one embodiment, the secondary low-voltage side further includes an NPN transistor, the collector of which is connected to the power supply voltage terminal, the emitter of which is grounded, and the base of which is connected to the primary full-bridge section. The magnetically integrated secondary low-voltage side winding circuit further includes a second resistor R6, a third resistor R7, a fourth resistor R8, a fifth resistor R9, and a sixth resistor R10. The second resistor R6 is connected between the collector of the NPN transistor and the power supply voltage terminal, the third resistor R7 is connected between the collector of the NPN transistor and the M11NNMOS transistor, the fourth resistor R8 is connected between the gate and source of the M11NNMOS transistor, the fifth resistor R9 is connected in parallel between the emitter and base of the NPN transistor, and the sixth resistor R10 is connected in series with the base of the NPN transistor.

[0033] In this technical solution, when the NMOS transistor on the high-voltage side of the secondary side is turned on, the M11NNMOS transistor on the low-voltage side of the secondary side is turned on simultaneously to reduce the winding floating voltage and reduce the voltage stress of the M9 and M10 NMOS transistors. When the M11NNMOS transistor is turned on, the winding on the low-voltage side of the secondary side is clamped by a circuit consisting of four first resistors connected in parallel and series with the M11NNMOS transistor. The multiple first resistors act as the load of the winding on the low-voltage side of the secondary side to pull down the winding floating voltage, thereby solving the problem of floating voltage in the winding on the low-voltage side of the secondary side.

[0034] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. All equivalent structural transformations made under the concept of the present utility model and using the contents of the present utility model specification and drawings, or direct / indirect applications in other related technical fields, are included in the patent protection scope of the present utility model.

Claims

1. A magnetically integrated secondary low-voltage side winding circuit, comprising a primary full-bridge part, a secondary high-voltage side and a secondary low-voltage side, wherein the secondary low-voltage side is connected in parallel with an M9N NMOS tube, an M10N NMOS tube and an M12N NMOS tube, characterized in that, The secondary low-voltage side connects a plurality of first resistors and a plurality of capacitors in parallel, and then connects the plurality of first resistors and the plurality of capacitors in series with an M11N N-MOS transistor, and then connects the M11N N-MOS transistor to the primary full-bridge part.

2. The magnetically integrated secondary low-voltage winding circuit of claim 1, wherein, The number of the first resistors is four.

3. The magnetically integrated secondary low-voltage winding circuit of claim 1, wherein, The resistance of the first resistors is 10K.

4. The magnetically integrated secondary low-voltage winding circuit of claim 3, wherein, The capacitance of the capacitors is 10nf.

5. The magnetically integrated secondary low-voltage winding circuit of claim 1, wherein, The secondary low-voltage side further comprises an NPN transistor, a collector of the NPN transistor is connected to a power supply voltage terminal, an emitter of the NPN transistor is grounded, and a base of the NPN transistor is connected to the primary full-bridge part.

6. The magnetically integrated secondary low-voltage winding circuit of claim 5, wherein, The magnetic integrated secondary low-voltage side winding circuit further comprises a second resistor, the second resistor is connected between the collector of the NPN transistor and the power supply voltage terminal.

7. The magnetically integrated secondary low-voltage winding circuit of claim 5, wherein, The magnetic integrated secondary low-voltage side winding circuit further comprises a third resistor, the third resistor is connected between the collector of the NPN transistor and the M11N N-MOS transistor.

8. The magnetically integrated secondary low-voltage winding circuit of claim 7, wherein, The magnetic integrated secondary low-voltage side winding circuit further comprises a fourth resistor, the fourth resistor is connected between the G terminal and the S terminal of the M11N N-MOS transistor.

9. The magnetically integrated secondary low-voltage winding circuit of claim 5, wherein, A fifth resistor is connected in parallel between the emitter and the base of the NPN transistor.

10. The magnetically integrated secondary low-voltage winding circuit of claim 5, wherein, The magnetic integrated secondary low-voltage side winding circuit further comprises a sixth resistor, the sixth resistor is connected in series with the base of the NPN transistor.

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