Three-level double-buck conversion circuit for post-stage of energy storage inverter integrated device

Abstract

A three-level double-buck conversion circuit for a post-stage of an energy storage inverter integrated device, comprising an energy storage battery, a bidirectional DC-DC converter, switching tubes S1, S2, S3, S4, S5, S6, S7, diodes D1, D2, D3, D4, D5, D6, D7, inductors L1 and L2, and capacitors C1 and C2. The three-level double-buck conversion circuit comprises a bidirectional switching tube composed of switching tube S4, diodes D3, D4, D5, and D6, and a double-buck circuit structure composed of switching tubes S2 and S3, diodes D1 and D2, and inductors L1 and L2. The three-level double-buck conversion circuit of the present application organically integrates three-level technology and a double-buck circuit structure, and has the advantages of low switching tube voltage stress, high reliability, and high efficiency.

Description

Technical Field

[0001] This invention relates to the field of power electronic energy conversion technology, specifically a three-level dual buck converter circuit for the downstream stage of an integrated energy storage inverter device. Background Technology

[0002] Energy storage systems are a crucial component of microgrids, playing a key role in their safe and reliable operation. As an essential component of energy storage systems, the performance of integrated energy storage inverters significantly impacts the stable operation of the microgrid.

[0003] Traditional energy storage inverter systems primarily use two-level inverters as their downstream inverters. However, the power semiconductor devices in a two-level inverter topology typically bear the entire DC bus voltage, resulting in significant switching losses. This hinders further performance improvements in the integrated energy storage inverter system. To reduce the voltage stress on the switching transistors and power losses in two-level inverters, researchers both domestically and internationally have optimized the inverter topology by incorporating multilevel technology into the inverter circuit topology to construct multilevel inverters. Compared to two-level inverters, multilevel inverters, due to their higher number of output levels, exhibit a more sinusoidal output waveform, lower voltage stress on the switching transistors, and higher efficiency. Summary of the Invention

[0004] This invention provides a three-level dual buck converter circuit for the downstream stage of an integrated energy storage inverter device. This inverter circuit combines multi-level technology with a dual buck circuit structure. Compared with the traditional two-level inverter circuit, it reduces the voltage stress on the switching transistors and the output harmonic content, thereby improving the output power quality and efficiency.

[0005] The technical solution adopted in this invention is as follows:

[0006] A three-level dual buck converter circuit for the downstream stage of an integrated energy storage inverter device includes switching transistors S1, S2, S3, S4, S5, S6, and S7; diodes D1, D2, D3, D4, D5, D6, and D7; filter inductors L1 and L2; and capacitors C1 and C2.

[0007] The positive terminal of capacitor C1 is connected to the drain of switching transistor S1, and the connection node forms the terminal p.

[0008] The negative terminal of capacitor C2 is connected to the source of switch S7, and the connection node forms the terminal m.

[0009] The negative terminal of capacitor C1 is connected to the positive terminal of capacitor C2, the anode of diode D3, and the negative terminal of diode D5, and the connection nodes form the endpoint n.

[0010] The drain of switch S7 is connected to the source of switch S5, the source of switch S6, the anode of diode D1, and the anode of diode D2, and the connection node forms the endpoint d.

[0011] The source of switch S1 is connected to the drain of switch S2 and the drain of switch S3 respectively, and their connection nodes form the endpoint c.

[0012] The source of the switching transistor S3 is connected to the other end of the inductor L2 and the cathode of the diode D2, and the connection node forms the endpoint b.

[0013] The source of switch S2 is connected to the cathode of diode D1, the anode of diode D4, the cathode of diode D6, and the anode of diode D7, and the connection node forms the endpoint a.

[0014] The cathode of diode D7 is connected to one end of inductor L1; the drain of switching transistor S5 is connected to the load R. L One end of the inductor L1 is connected to the other end of the switch; the drain of the switch S6 is connected to the load R. L The other end is connected to one end of inductor L2;

[0015] The drain of switch S4 is connected to the cathodes of diodes D3 and D4, respectively; the source of switch S4 is connected to the anodes of diodes D5 and D6, respectively.

[0016] In this converter circuit, switching transistor S2, switching transistor S3, diode D1, diode D2, inductor L1, and inductor L2 form a dual buck circuit structure.

[0017] The switching transistors S1 to S7 are MOSFETs or IGBTs with body diodes.

[0018] The endpoints p and m are connected to the output side of the bidirectional DC-DC converter, and the input side of the bidirectional DC-DC converter is connected to the energy storage battery.

[0019] The capacitors C1 and C2 are split capacitors with equal capacitance values.

[0020] The conversion circuit has six operating modes when working normally, including the mode with output AC voltage u. o There are three operating modes in each of the positive and negative half-cycles:

[0021] (1) Output AC voltage u o The three working modes of the positive half-cycle are as follows:

[0022] Mode 1: Switches S1, S2, S6, and S7 are turned on, while the remaining switches are turned off. The energy storage battery supplies power to inductor L1 and load R. L Provides energy, inductor L1 current i L1 Linear increase. In this mode, the output current i o =iL1 Output voltage u o >0, the voltage u between endpoints a and b ab =+U s .

[0023] Mode 2: Switches S4, S6, and S7 are on, while the remaining switches are off. Capacitor C2 is connected to inductor L1 and load R. L Provides energy, inductor L1 current i L1 As the voltage rises linearly, the voltage across capacitor C2 decreases; the energy storage battery charges capacitor C1, causing the voltage across capacitor C1 to rise. In this mode, the output current i... o =i L1 Output voltage u o >0, the voltage u between endpoints a and b ab =+U s / 2.

[0024] Mode 3: Switch S6 is on, all other switches are off. Inductor L1 current i L1 The current flows through diode D1 and is supplied to the load R. L Provides energy, current i L1 The voltage decreases linearly. Capacitors C1 and C2 are charging, and the voltage across them rises. In this mode, the output current i... o =i L1 Output voltage u o >0, the voltage u between endpoints a and b ab =0.

[0025] (2) Output AC voltage u o The three operating modes of the negative half-cycle are as follows:

[0026] Mode 4: Switch S5 is on, all other switches are off. Inductor L2 current i L2 The current flows through diode D2 and is supplied to the load R. L Provides energy, current i L2 The voltage decreases linearly. The energy storage battery charges capacitors C1 and C2, causing the voltages of capacitors C1 and C2 to rise. In this mode, the output current i... o =-i L2 Output voltage u o <0, the voltage u between endpoints a and b ab =0.

[0027] Mode 5: Switches S1, S3, S4, and S5 are on, while the remaining switches are off. Capacitor C1 is connected to inductor L2 and load R. L Provides energy, inductor L2 current i L2As the voltage rises linearly, the voltage across capacitor C1 decreases; the energy storage battery charges capacitor C2, causing its voltage to rise. In this mode, the output current i... o =-i L2 Output voltage u o <0, the voltage u between endpoints a and b ab =-U s / 2.

[0028] Mode 6: Switches S1, S3, S5, and S7 are on, while the remaining switches are off. The energy storage battery supplies power to inductor L2 and load R. L Provides energy, inductor L2 current i L2 Linear increase. In this mode, the output current i o =-i L2 Output voltage u o <0, the voltage u between endpoints a and b ab =-U s .

[0029] The present invention provides a three-level dual buck converter circuit for the downstream stage of an integrated energy storage inverter device, with the following technical advantages:

[0030] 1) This invention adopts a dual buck structure, which retains the advantages of dual buck inverters such as no reverse recovery problem of switch body diodes and no bridge arm shoot-through risk, reduces conduction loss and improves the reliability of inverter.

[0031] 2) This invention uses a switching transistor S4 and diodes D3, D4, D5, and D6 connected together to form a bidirectional switching transistor, which has a simple structure and reduces the complexity of control.

[0032] 3) Based on the traditional two-level dual-buck inverter circuit topology, this invention employs three-level technology, that is, introducing a bidirectional switching transistor between the midpoint of the two split capacitors and one bridge arm of the inverter, resulting in a level u. ab =1 / 2U s The implementation provides a conduction path, thereby enabling the inverter to achieve three-level output, reducing the voltage stress of the switching transistor, and reducing the output harmonic content.

[0033] 4) The present invention uses switching transistors S1 and S7 to clamp the input DC voltage, thereby improving the reliability of the inverter circuit. Attached Figure Description

[0034] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0035] Figure 1 This is the main topology diagram of the three-level dual buck converter circuit of the present invention.

[0036] Figure 2This is a schematic diagram of the operating mode of the three-level dual buck converter circuit of the present invention;

[0037] Figure 3 This is a schematic diagram of the second working mode of the three-level dual buck converter circuit of the present invention;

[0038] Figure 4 This is a schematic diagram of the third operating mode of the three-level dual buck converter circuit of the present invention;

[0039] Figure 5 This is a schematic diagram of the fourth operating mode of the three-level dual buck converter circuit of the present invention;

[0040] Figure 6 This is a schematic diagram of the fifth operating mode of the three-level dual buck converter circuit of the present invention;

[0041] Figure 7 This is a schematic diagram of the sixth working mode of the three-level dual buck converter circuit of the present invention.

[0042] Figure 8 This diagram shows the six operating modes of the switching transistors S1 to S7 in the three-level dual buck converter circuit of this invention.

[0043] Figure 9 This is a diagram showing the pulse signal distribution for the switching transistors S1 to S7 in the three-level dual buck converter circuit of this invention.

[0044] Figure 10 The output voltage u of the three-level dual buck converter circuit of this invention in a stable state o and output current i o Waveform diagram.

[0045] Figure 11 The current i in inductor L1 of the three-level dual buck converter circuit of this invention is in a steady state. L1 Waveform diagram.

[0046] Figure 12 The current i in inductor L2 of the three-level dual buck converter circuit of this invention is in a steady state. L2 Waveform diagram.

[0047] Figure 13 The voltage u between terminals a and b in the three-level dual buck converter circuit of this invention under steady state is... ab Waveform diagram.

[0048] Figure 14 The voltage u of the DC split capacitors C1 and C2 in the three-level dual buck converter circuit of this invention under steady state. c1 u c2 Waveform diagram. Detailed Implementation

[0049] like Figure 1As shown, a three-level dual buck converter circuit for the downstream stage of an integrated energy storage inverter device is provided. The converter circuit includes an energy storage battery, a bidirectional DC-DC converter, switching transistors S1 to S7, diodes D1 to D7, inductors L1 and L2, and capacitors C1 and C2.

[0050] The positive terminal of capacitor C1 is connected to the drain of switching transistor S1, and the connection node forms the terminal p.

[0051] The negative terminal of capacitor C2 is connected to the source of switch S7, and the connection node forms the terminal m.

[0052] The negative terminal of capacitor C1 is connected to the positive terminal of capacitor C2, the anode of diode D3, and the negative terminal of diode D5, and the connection nodes form the endpoint n.

[0053] The drain of switch S7 is connected to the source of switch S5, the source of switch S6, the anode of diode D1, and the anode of diode D2, and the connection node forms the endpoint d.

[0054] The source of switch S1 is connected to the drain of switch S2 and the drain of switch S3 respectively, and their connection nodes form the endpoint c.

[0055] The source of the switching transistor S3 is connected to the other end of the inductor L2 and the cathode of the diode D2, and the connection node forms the endpoint b.

[0056] The source of switch S2 is connected to the cathode of diode D1, the anode of diode D4, the cathode of diode D6, and the anode of diode D7, and the connection node forms the endpoint a.

[0057] The cathode of diode D7 is connected to one end of inductor L1; the drain of switching transistor S5 is connected to the load R. L One end of the inductor L1 is connected to the other end of the switch; the drain of the switch S6 is connected to the load R. L The other end is connected to one end of inductor L2;

[0058] The drain of switch S4 is connected to the cathodes of diodes D3 and D4, respectively; the source of switch S4 is connected to the anodes of diodes D5 and D6, respectively.

[0059] The switching transistors S1 to S7 are all MOSFETs (Power Field Effect Transistors) with body diodes or IGBTs (Insulated Gate Bipolar Transistors).

[0060] In the conversion circuit, the switching transistors S2 and S3, diodes D1 and D2, and inductors L1 and L2 form a dual buck circuit structure.

[0061] The switching transistor S4, diodes D3, D4, D5, and D6 are connected to form a bidirectional switching transistor with a voltage level of ±1 / 2U. s This provides a circulation path for implementation.

[0062] The capacitors C1 and C2 are split capacitors with equal capacitance values. Since capacitors C1 and C2 are of equal value and are connected in series, the voltage across each capacitor is the DC voltage U output from the bidirectional DC-DC converter. s Half of it provides the conditions for the implementation of three levels.

[0063] The specific experimental parameters of the circuit are as follows:

[0064] A three-level dual-buck converter circuit for the downstream stage of an integrated energy storage inverter device, outputting AC voltage u o The effective value is 220V, the frequency is 50Hz, and the DC voltage U on the output side of the bidirectional DC-DC converter is... s The voltage is 400V, the DC-side split capacitors C1 = C2 = 4700μF, the switching frequency is 20kHz, the filter inductors L1 = L2 = 3mH, and the load R... L The resistance is 80Ω.

[0065] A three-level dual-buck converter circuit used in the downstream stage of an integrated energy storage inverter has six operating modes during normal operation, including the mode with output AC voltage u. o There are three working modes in each of the positive and negative half-cycles.

[0066] (1) Output AC voltage u o The three working modes of the positive half-cycle are as follows:

[0067] like Figure 2 As shown, in mode 1: switches S1, S2, S6, and S7 are on, while the remaining switches are off. The energy storage battery supplies power to inductor L1 and load R. L Provides energy, inductor L1 current i L1 Linear increase. In this mode, the output current i o =i L1 Output voltage u o >0, the voltage u between endpoints a and b ab =+U s .

[0068] like Figure 3 As shown, in mode two: switches S4, S6, and S7 are on, while the remaining switches are off. Capacitor C2 is connected to inductor L1 and load R. L Provides energy, inductor L1 current i L1 As the voltage rises linearly, the voltage across capacitor C2 decreases; the energy storage battery charges capacitor C1, causing the voltage across capacitor C1 to rise. In this mode, the output current i... o =i L1 Output voltage u o >0, the voltage u between endpoints a and b ab =+Us / 2.

[0069] like Figure 4 As shown, in mode 3: switch S6 is on, and the other switches are off. The current i in inductor L1... L1 The current flows through diode D1 and is supplied to the load R. L Provides energy, current i L1 The voltage decreases linearly. Capacitors C1 and C2 are charging, and the voltage across them rises. In this mode, the output current i... o =i L1 Output voltage u o >0, the voltage u between endpoints a and b ab =0.

[0070] (2) Output AC voltage u o The three operating modes of the negative half-cycle are as follows:

[0071] like Figure 5 As shown, in mode four: switch S5 is on, and the other switches are off. The current i in inductor L2... L2 The current flows through diode D2 and is supplied to the load R. L Provides energy, current i L2 The voltage decreases linearly. The energy storage battery charges capacitors C1 and C2, causing the voltages of capacitors C1 and C2 to rise. In this mode, the output current i... o =-i L2 Output voltage u o <0, the voltage u between endpoints a and b ab =0.

[0072] like Figure 6 As shown, in mode five: switches S1, S3, S4, and S5 are on, while the remaining switches are off. Capacitor C1 is connected to inductor L2 and load R. L Provides energy, inductor L2 current i L2 As the voltage rises linearly, the voltage across capacitor C1 decreases; the energy storage battery charges capacitor C2, causing its voltage to rise. In this mode, the output current i... o =-i L2 Output voltage u o <0, the voltage u between endpoints a and b ab =-U s / 2.

[0073] like Figure 7 As shown, in mode six: switches S1, S3, S5, and S7 are on, while the remaining switches are off. The energy storage battery supplies power to inductor L2 and load R. L Provides energy, inductor L2 current i L2 Linear increase. In this mode, the output current i o =-iL2 Output voltage u o <0, the voltage u between endpoints a and b ab =-U s .

[0074] Figure 8 This diagram illustrates the six operating modes of switching transistors S1 to S7 in the three-level dual buck converter circuit of this invention, where "0" and "1" represent the off and on states of the switching transistors, respectively. Figure 8 As shown, the circuit has three operating modes in both the positive and negative half-cycles. In the positive half-cycle, the output voltage u o >0, voltage u ab There are three states, namely +U s +1 / 2U s 0, while in the negative half-cycle, the output voltage u o <0, voltage u ab There are three states, namely -U s -1 / 2U s 0.

[0075] Figure 9 This is a pulse signal distribution diagram corresponding to switches S1 to S7 in the three-level dual buck converter circuit of this invention. For ease of analysis, it is based on voltage u. ab Based on the changing pattern, the pulse signal distribution of each switching transistor is divided into four small intervals. By using PWM control to distribute the pulse signal according to the pattern [Interval 1] → [Interval 2] → [Interval 1] → [Interval 3] → [Interval 4] → [Interval 3], the voltage u can be adjusted. ab It is a three-level circuit.

[0076] Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 The output voltage u of the three-level dual buck converter circuit of this invention under steady-state conditions is respectively... o and output current i o Waveform diagram, inductor L1 current i L1 Waveform diagram, inductor L2 current i L2 Waveform diagram, voltage u between endpoints a and b ab Waveform diagram, and voltage u of DC split capacitors C1 and C2 c1 u c2 Waveform diagram.

[0077] like Figure 10 As shown, the output AC current i o Multiply by a gain of 10 and add to the output AC voltage u o By comparison, it can be seen that the output AC voltage u oWith output AC current i o All maintained good sinusoidal characteristics.

[0078] Figure 11 The current i flowing through inductor L1 L1 The waveform diagram shows that inductor L1 only operates during the positive half-cycle, which is consistent with the theoretical analysis.

[0079] Figure 12 The current i flowing through inductor L2 L2 The waveform diagram shows that inductor L2 only operates during the negative half-cycle, which is consistent with the theoretical analysis.

[0080] Figure 13 Let u be the voltage between endpoints a and b. ab The waveform clearly shows that the voltage u ab The three-level circuit was implemented, proving that the invented circuit topology has three-level functionality.

[0081] Figure 14 The voltage u of the DC split capacitors C1 and C2 c1 u c2 The waveform diagram shows that the DC-side split capacitor voltage can achieve self-balancing in steady state.

[0082] The three-level dual buck converter circuit of this invention organically integrates three-level technology and dual buck circuit structure, and has the advantages of low voltage stress on the switching transistor, high reliability and high efficiency.

Claims

1. A three-level dual buck converter circuit for the downstream stage of an integrated energy storage inverter device, comprising switching transistors S1, S2, S3, S4, S5, S6, S7, diodes D1, D2, D3, D4, D5, D6, D7, filter inductors L1 and L2, and capacitors C1 and C2; characterized in that: The positive terminal of capacitor C1 is connected to the drain of switching transistor S1, and the connection node forms the terminal p. The negative terminal of capacitor C2 is connected to the source of switch S7, and the connection node forms the terminal m. The negative terminal of capacitor C1 is connected to the positive terminal of capacitor C2, the anode of diode D3, and the negative terminal of diode D5, and the connection nodes form the endpoint n. The drain of switch S7 is connected to the source of switch S5, the source of switch S6, the anode of diode D1, and the anode of diode D2, and the connection node forms the endpoint d. The source of switch S1 is connected to the drain of switch S2 and the drain of switch S3 respectively, and their connection nodes form the endpoint c. The source of the switching transistor S3 is connected to the other end of the inductor L2 and the cathode of the diode D2, and the connection node forms the endpoint b. The source of switch S2 is connected to the cathode of diode D1, the anode of diode D4, the cathode of diode D6, and the anode of diode D7, and the connection node forms the endpoint a. The cathode of diode D7 is connected to one end of inductor L1; the drain of switching transistor S5 is connected to the load R. L One end of the inductor L1 is connected to the other end of the switch; the drain of the switch S6 is connected to the load R. L The other end is connected to one end of inductor L2; The drain of switch S4 is connected to the cathodes of diodes D3 and D4, respectively; the source of switch S4 is connected to the anodes of diodes D5 and D6, respectively.

2. The three-level dual buck converter circuit for the downstream stage of an integrated energy storage inverter device according to claim 1, characterized in that: In this converter circuit, switching transistor S2, switching transistor S3, diode D1, diode D2, inductor L1, and inductor L2 form a dual buck circuit structure.

3. The three-level dual buck converter circuit for the downstream stage of an integrated energy storage inverter device according to claim 1, characterized in that: The switching transistors S1 to S7 are MOSFETs or IGBTs with body diodes.

4. The three-level dual buck converter circuit for the downstream stage of an integrated energy storage inverter device according to claim 1, characterized in that: The endpoints p and m are connected to the output side of the bidirectional DC-DC converter, and the input side of the bidirectional DC-DC converter is connected to the energy storage battery.

5. The three-level dual buck converter circuit for the downstream stage of an integrated energy storage inverter device according to claim 1, characterized in that: The capacitors C1 and C2 are split capacitors with equal capacitance values.

6. The three-level dual buck converter circuit for the downstream stage of an integrated energy storage inverter device according to claim 4, characterized in that: The conversion circuit has six operating modes when working normally, including the output AC voltage... u o There are three operating modes in each of the positive and negative half-cycles: (1) Output AC voltage u o The three working modes of the positive half-cycle are as follows: Mode 1: Switches S1, S2, S6, and S7 are turned on, while the remaining switches are turned off; the energy storage battery supplies power to inductor L1 and load R. L Provides energy, current in inductor L1 i L1 Linear increase; in this mode, the output current rises linearly. i o = i L1 Output AC voltage u o >0, voltage between endpoints a and b u ab =+U s U s This represents the DC voltage at the output of the bidirectional DC-DC converter. Mode 2: Switches S4, S6, and S7 are turned on, and the remaining switches are turned off; capacitor C2 is connected to inductor L1 and load R. L Provides energy, current in inductor L1 i L1 As the voltage rises linearly, the voltage of capacitor C2 decreases; the energy storage battery charges capacitor C1, causing the voltage of capacitor C1 to rise; under this mode, the output current... i o = i L1 Output voltage u o >0, voltage between endpoints a and b u ab =+U s / 2; Mode 3: Switch S6 is on, all other switches are off; inductor L1 current... i L1 The current flows through diode D1 and is supplied to the load R. L Provides energy, electric current i L1 The voltage decreases linearly; capacitors C1 and C2 are in a charging state, and the voltage across capacitors C1 and C2 rises; in this mode, the output current... i o = i L1 Output AC voltage u o >0, voltage between endpoints a and b u ab =0; (2) Output AC voltage u o The three operating modes of the negative half-cycle are as follows: Mode 4: Switch S5 is on, all other switches are off; inductor L2 current... i L2 The current flows through diode D2 and is supplied to the load R. L Provides energy, electric current i L2 The voltage decreases linearly; the energy storage battery charges capacitors C1 and C2, causing the voltages of capacitors C1 and C2 to rise; in this mode, the output current... i o = -i L2 Output AC voltage u o <0, voltage between endpoints a and b u ab =0; Mode 5: Switches S1, S3, S4, and S5 are turned on, and the remaining switches are turned off; capacitor C1 is connected to inductor L2 and load R. L Provides energy, inductor L2 current i L2 As the voltage rises linearly, the voltage of capacitor C1 decreases; the energy storage battery charges capacitor C2, causing the voltage of capacitor C2 to rise; under this mode, the output current... i o = -i L2 Output AC voltage u o <0, voltage between endpoints a and b u ab =-U s / 2; Mode 6: Switches S1, S3, S5, and S7 are turned on, while the remaining switches are turned off; the energy storage battery supplies power to inductor L2 and load R. L Provides energy, inductor L2 current i L2 Linear increase; in this mode, the output current rises linearly. i o = -i L2 Output AC voltage u o <0, voltage between endpoints a and b u ab =-U s .

Images