Circuit board, display backboard and display screen for driving light emitting chip

Abstract

The utility model discloses a kind of circuit board, display backboard and display screen, circuit board includes first solder resist layer, first wiring layer, first insulating layer, second wiring layer, substrate, control circuit layer and second solder resist layer that are sequentially laminated, first wiring layer includes multiple parallel arrangement sub-circuit layer, sub-circuit layer includes signal line, multiple block conductors and multiple bonding wire groups for bonding light emitting chip, the extension direction of signal line and the arrangement direction of multiple bonding wire groups are consistent with the extension direction of its corresponding sub-circuit layer, multiple bonding wire groups are connected with signal line, multiple bonding wire groups are connected with second wiring layer, signal line and second wiring layer are connected with control circuit layer respectively, the current signal polarity of signal line and second wiring layer transmission is opposite;Block conductor is provided between adjacent two bonding wire groups, and block conductor is spaced apart with bonding wire group and signal line. The circuit board improves ink color consistency, also improves board bending board warping.

Description

Technical Field

[0001] This utility model relates to the field of display, and in particular to a circuit board, display backplane and display screen for driving light-emitting chips. Background Technology

[0002] The substrate in the copper-free area (low residual copper rate) of the LED board has a different coefficient of thermal expansion than the copper layer area. During high-temperature curing, the ink shrinks more significantly, resulting in inconsistent color depth. For example, the copper-free area appears dark, while the copper layer area appears bright. The ink in the copper layer area is easily spread thin due to surface tension, while the ink in the copper-free area accumulates thicker, causing visual color difference. In addition, the copper layer area has strong reflectivity, while the substrate in the copper-free area absorbs more light, which not only affects the consistency of ink color development but also affects the light output effect of the LED board. Furthermore, a large difference in residual copper rate will cause uneven mechanical properties of the entire PCB board, reducing the board's bending resistance. Utility Model Content

[0003] In view of the shortcomings of the above-mentioned related technologies, the purpose of this utility model is to provide a circuit board, display backplate and display screen for driving light-emitting chips, which improves the consistency of ink color rendering, improves visual color difference, and also improves board bending and warping.

[0004] This utility model provides a circuit board for driving a light-emitting chip, comprising a first solder resist layer, a first wiring layer, a second wiring layer, a substrate, a control circuit layer, and a second solder resist layer stacked in sequence, wherein a first insulating layer is disposed between the first wiring layer and the second wiring layer.

[0005] The first wiring layer includes multiple parallel sub-line layers. Each sub-line layer includes signal lines, multiple block conductors, and multiple bonding wire groups for bonding light-emitting chips. The extension direction of the signal lines and the arrangement direction of the multiple bonding wire groups are consistent with the extension direction of their corresponding sub-line layers. Each of the multiple bonding wire groups is connected to the signal lines and to the second wiring layer. The signal lines and the second wiring layer are respectively connected to the control wiring layer. The polarities of the current signals transmitted by the signal lines and the second wiring layer are opposite. A block conductor is disposed between two adjacent bonding wire groups, and the block conductor is spaced apart from both the bonding wire groups and the signal lines.

[0006] Optionally, the bonding wire group includes at least one sub-bonding wire group, the sub-bonding wire group including a pad group and an auxiliary line, one end of the pad group being connected to the signal line, and the other end of the pad group being connected to the second wiring layer through the auxiliary line.

[0007] Optionally, the pad group includes a first pad and a second pad, and the first solder mask layer has openings at positions corresponding to the first pad and the second pad to expose the first pad and the second pad, respectively.

[0008] Optionally, the bonding wire group includes three sub-bonding wire groups arranged along the extension direction of the sub-line layer.

[0009] Optionally, the three sub-bonding wire groups are respectively a red light-emitting chip sub-bonding wire group, a green light-emitting chip sub-bonding wire group, and a blue light-emitting chip sub-bonding wire group.

[0010] Optionally, the pad group includes a first pad group and a second pad group, the auxiliary line includes a first auxiliary line and a second auxiliary line, the signal line includes a first signal line and a second signal line extending along the extension direction of the sub-line layer, and the sub-bonding line group is disposed between the first signal line and the second signal line;

[0011] One end of the first pad group is connected to the first signal line, one end of the second pad group is connected to the second signal line, and the other end of the first pad group is connected to the other end of the second pad group in sequence through the first auxiliary line and the second auxiliary line. The connection node between the first auxiliary line and the second auxiliary line is connected to the second wiring layer.

[0012] Optionally, the block-shaped conductor is disposed between the first signal line and the second signal line, and the block-shaped conductor extends along an extension direction perpendicular to the first signal line or the second signal line.

[0013] Optionally, the first insulating layer has a via at the position corresponding to the connection node between the first auxiliary line and the second auxiliary line, and the block wire has a clearance groove on both sides of the bonding wire group in the arrangement direction to prevent interference with the via.

[0014] Optionally, the gap between the block conductor and the bonding wire group is not less than 0.1 mm, and the gap between the block conductor and the signal line is not less than 0.1 mm.

[0015] Optionally, the control circuit layer includes a drive circuit layer and a power circuit layer stacked sequentially on the substrate, with a second insulating layer disposed between the drive circuit layer and the power circuit layer, the signal line and the second wiring layer respectively connected to the drive circuit layer, and the drive circuit layer connected to the power circuit layer.

[0016] This utility model also provides a display backplate, including a plurality of light-emitting chips and the circuit board for driving the light-emitting chips, wherein the light-emitting chips are bonded to the bonding wire group.

[0017] Optionally, the light-emitting chip can be MiniLED or MicroLED.

[0018] This utility model also provides a display screen, including a housing and the aforementioned display back panel, wherein the display back panel is mounted on the housing.

[0019] This invention relates to a circuit board, display backplane, and display screen for driving light-emitting chips. By adding block-shaped conductors to copper-free areas on the circuit board, the difference in residual copper rate across the entire layer can be reduced. Areas with higher residual copper rates enhance the mechanical strength of the circuit board. Reducing the difference in residual copper rate between the top and bottom layer wiring helps to improve board bending and warping. It also improves the consistency of ink color development, reduces visual color difference, and allows for more uniform heat dissipation of the entire module, reducing visual effect differences caused by chip light decay and improving the high grayscale display effect of the module. Attached Figure Description

[0020] Figure 1 A schematic diagram of the layer structure of a circuit board for driving a light-emitting chip is provided for embodiments of this utility model;

[0021] Figure 2 A schematic diagram of the circuit board for driving the light-emitting chip is provided for an embodiment of this utility model;

[0022] Figure 3 for Figure 2 A schematic diagram of the structure of part D in the middle.

[0023] Explanation of reference numerals in the attached figures:

[0024] 1-First solder mask layer; 2-First wiring layer; 21-Sub-line layer; 212-Block conductor; 213-Bond wire group; 214-Sub-bond wire group; 21a-First pad group; 21b-Second pad group; 21c-First auxiliary line; 21d-Second auxiliary line; 21e-First signal line; 21f-Second signal line; 21g-Groove; 3-Second wiring layer; 4-Substrate; 5-Drive circuit layer; 6-Power circuit layer; A-Via. Detailed Implementation

[0025] To facilitate understanding of this utility model, a more complete description will be given below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of this utility model. However, this utility model can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this utility model.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0027] In the description of this utility model, the terms "first," "second," etc., are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0028] It should be noted that the illustrations provided in the embodiments of this utility model are only schematic representations of the basic concept of this utility model. The illustrations only show the components related to this utility model and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0029] The specific embodiments of this utility model will be further described below with reference to the accompanying drawings.

[0030] See Figures 1 to 3 As shown, this utility model discloses a circuit board for driving a light-emitting chip, including a first solder mask layer 1, a first wiring layer 2, a second wiring layer 3, a substrate 4, a control circuit layer and a second solder mask layer stacked in sequence, and a first insulating layer is disposed between the first wiring layer 2 and the second wiring layer 3.

[0031] The first wiring layer 2 includes multiple parallel sub-line layers 21. Each sub-line layer 21 includes signal lines, multiple block conductors 212, and multiple bonding wire groups 213 for bonding light-emitting chips. The extension direction of the signal lines and the arrangement direction of the multiple bonding wire groups 213 are consistent with the extension direction of their respective sub-line layers 21. Each of the multiple bonding wire groups 213 is connected to the signal lines and to the second wiring layer 3. The signal lines and the second wiring layer 3 are respectively connected to the control circuit layer. The polarities of the current signals transmitted by the signal lines and the second wiring layer 3 are opposite. A block conductor 212 is disposed between two adjacent bonding wire groups 213, and the block conductor 212 is spaced apart from both the bonding wire groups 213 and the signal lines.

[0032] This invention relates to a circuit board, display backplane, and display screen for driving light-emitting chips. By adding block-shaped conductors to copper-free areas of the circuit board, the difference in residual copper content across the entire layer can be reduced. Areas with higher residual copper content enhance the mechanical strength of the circuit board. Reducing the difference in residual copper content between the top and bottom layer wiring helps improve board bending and warping. It also improves ink color consistency and reduces visual color difference. Furthermore, in single-layer designs, due to the significant difference in heat dissipation efficiency between copper-free and copper-plated areas, adding block-shaped conductors to the copper-free areas allows for more uniform heat dissipation of the entire module, reducing visual differences caused by chip light decay and improving the high grayscale display effect of the module.

[0033] In this embodiment, the current signal polarity of the signal line is positive, and the current signal polarity of the second wiring layer 3 is negative. In some embodiments, the current signal polarity of the signal line is negative, and the current signal polarity of the second wiring layer 3 is positive.

[0034] In this embodiment, both the first wiring layer 2 and the second wiring layer 3 are made of copper. That is, the material of the block conductor 212 is also copper. In other embodiments, other metal materials may be used, and this is not limited here.

[0035] In this embodiment, the gap between the block conductor 212 and the bonding wire group 213 is not less than 0.1 mm, and the gap between the block conductor 212 and the signal line is not less than 0.1 mm. To prevent the block conductor 212 from interfering with the surrounding lines, the gap between the block conductor 212 and the surrounding lines must be ensured to be not less than 0.1 mm.

[0036] In this embodiment, the bonding wire group 213 includes at least one sub-bonding wire group 214. The sub-bonding wire group 214 includes a pad group and an auxiliary line. One end of the pad group is connected to the signal line, and the other end of the pad group is connected to the second wiring layer 3 through the auxiliary line.

[0037] In this embodiment, the pad group includes a first pad and a second pad. The first solder mask layer 1 has openings at positions corresponding to the first pad and the second pad, respectively, for exposing the first pad and the second pad. Similarly, the second solder mask layer also has openings at positions corresponding to the pads for exposing the pads, which will not be described in detail here.

[0038] In this embodiment, the bonding wire group 213 includes three sub-bonding wire groups 214 arranged along the extension direction of the sub-line layer 21. In some embodiments, the three sub-bonding wire groups are respectively a red light-emitting chip sub-bonding wire group, a green light-emitting chip sub-bonding wire group, and a blue light-emitting chip sub-bonding wire group, but are not limited thereto.

[0039] In this embodiment, the pad group includes a first pad group 21a and a second pad group 21b, the auxiliary line includes a first auxiliary line 21c and a second auxiliary line 21d, the signal line includes a first signal line 21e and a second signal line 21f extending along the extension direction of the sub-line layer 21, and the sub-bonding line group 214 is disposed between the first signal line 21e and the second signal line 21f.

[0040] One end of the first pad group 21a is connected to the first signal line 21e, and one end of the second pad group 21b is connected to the second signal line 21f. The other end of the first pad group 21a is connected to the other end of the second pad group 21b sequentially through the first auxiliary line 21c and the second auxiliary line 21d. The connection node between the first auxiliary line 21c and the second auxiliary line 21d is connected to the second wiring layer 3. Both the first pad group 21a and the second pad group 21b include a first pad and a second pad for bonding light-emitting chips. The light-emitting chips bonded by the first pad group 21a and the second pad group 21b can be of the same color or different colors, which is not limited here.

[0041] In this embodiment, the block-shaped conductor 212 is disposed between the first signal line 21e and the second signal line 21f, and the block-shaped conductor 212 extends along an extension direction perpendicular to the first signal line 21e or the second signal line 21f.

[0042] In this embodiment, the first insulating layer has a via A at the position corresponding to the connection node between the first auxiliary line 21c and the second auxiliary line 21d. The block conductor 212 has clearance grooves 21g on both sides of the bonding wire group 213 in the arrangement direction to prevent interference with the via A. At this time, the block conductor 212 is H-shaped. By rationally designing the pixel circuit, the number of vias is reduced, ensuring the strength of the circuit board and simplifying the process.

[0043] In this embodiment, the control circuit layer includes a drive circuit layer 5 and a power circuit layer 6 sequentially stacked on the substrate 4. A second insulating layer is disposed between the drive circuit layer 5 and the power circuit layer 6. The signal line and the second wiring layer 3 are respectively connected to the drive circuit layer 5, and the drive circuit layer 5 is connected to the power circuit layer 6. The drive circuit layer 5 is used to send drive signals to the signal line and the second wiring layer 3, respectively, and the power circuit layer 6 is used to provide power to the drive circuit layer 5.

[0044] In this embodiment, both the first and second insulating layers are made of prepreg (PP). In other embodiments, other types of insulating materials may also be used, which are not limited here.

[0045] In this embodiment, both the drive circuit layer 5 and the power circuit layer 6 are made of copper. In other embodiments, other metal materials may be used, and this is not limited here.

[0046] This utility model also discloses a display backplate, including a plurality of light-emitting chips and the circuit board described above for driving the light-emitting chips, wherein the light-emitting chips are bonded to the bonding wire group 213.

[0047] In this embodiment, the light-emitting chip can be a MiniLED, MicroLED, nano-sized LED, or LED of other sizes. It is not limited here, and the specific selection can be made according to the actual situation.

[0048] This utility model also discloses a display screen, including a housing and the aforementioned display back panel, wherein the display back panel is mounted on the housing.

[0049] As one implementation method, the display screen can be a television, VR, AR, smart wearable device, mobile phone, vehicle display, etc.

[0050] This invention relates to a circuit board, display backplane, and display screen for driving light-emitting chips. By adding block-shaped conductors to copper-free areas on the circuit board, the difference in residual copper rate across the entire layer can be reduced. Areas with higher residual copper rates enhance the mechanical strength of the circuit board. Reducing the difference in residual copper rate between the top and bottom layer wiring helps to improve board bending and warping. It also improves the consistency of ink color development, reduces visual color difference, and allows for more uniform heat dissipation of the entire module, reducing visual effect differences caused by chip light decay and improving the high grayscale display effect of the module.

[0051] It should be understood that the application of this utility model is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A circuit board for driving a light-emitting chip, characterized in that, It includes a first solder mask layer, a first wiring layer, a second wiring layer, a substrate, a control circuit layer, and a second solder mask layer stacked in sequence, with a first insulating layer disposed between the first wiring layer and the second wiring layer; The first wiring layer includes multiple parallel sub-line layers. Each sub-line layer includes signal lines, multiple block conductors, and multiple bonding wire groups for bonding light-emitting chips. The extension direction of the signal lines and the arrangement direction of the multiple bonding wire groups are consistent with the extension direction of their corresponding sub-line layers. Each of the multiple bonding wire groups is connected to the signal lines and to the second wiring layer. The signal lines and the second wiring layer are respectively connected to the control wiring layer. The polarities of the current signals transmitted by the signal lines and the second wiring layer are opposite. A block conductor is disposed between two adjacent bonding wire groups, and the block conductor is spaced apart from both the bonding wire groups and the signal lines.

2. The circuit board for driving a light-emitting chip as described in claim 1, characterized in that, The bonding wire group includes at least one sub-bonding wire group, the sub-bonding wire group includes a pad group and an auxiliary line, one end of the pad group is connected to the signal line, and the other end of the pad group is connected to the second wiring layer through the auxiliary line.

3. The circuit board for driving a light-emitting chip as described in claim 2, characterized in that, The pad group includes a first pad and a second pad, and the first solder mask layer has openings at positions corresponding to the first pad and the second pad to expose the first pad and the second pad, respectively.

4. The circuit board for driving a light-emitting chip as described in claim 2 or 3, characterized in that, The bonding wire group includes three sub-bonding wire groups arranged along the extension direction of the sub-line layer.

5. The circuit board for driving a light-emitting chip as described in claim 4, characterized in that, The three sub-bonding line groups are the red light-emitting chip sub-bonding line group, the green light-emitting chip sub-bonding line group, and the blue light-emitting chip sub-bonding line group.

6. The circuit board for driving a light-emitting chip as described in claim 4, characterized in that, The pad group includes a first pad group and a second pad group, the auxiliary line includes a first auxiliary line and a second auxiliary line, the signal line includes a first signal line and a second signal line extending along the extension direction of the sub-line layer, and the sub-bonding line group is disposed between the first signal line and the second signal line; One end of the first pad group is connected to the first signal line, one end of the second pad group is connected to the second signal line, and the other end of the first pad group is connected to the other end of the second pad group in sequence through the first auxiliary line and the second auxiliary line. The connection node between the first auxiliary line and the second auxiliary line is connected to the second wiring layer.

7. The circuit board for driving a light-emitting chip as described in claim 6, characterized in that, The block-shaped conductor is disposed between the first signal line and the second signal line, and the block-shaped conductor extends along an extension direction perpendicular to the first signal line or the second signal line.

8. The circuit board for driving a light-emitting chip as described in claim 7, characterized in that, The first insulating layer has a via at the position corresponding to the connection node between the first auxiliary line and the second auxiliary line, and the block wire has a clearance groove on both sides of the bonding wire group in the arrangement direction to prevent interference with the via.

9. The circuit board for driving a light-emitting chip as described in claim 1, 2, 3, 5, 6, 7, or 8, characterized in that, The gap between the block conductor and the bonding wire assembly shall not be less than 0.1 mm, and the gap between the block conductor and the signal line shall not be less than 0.1 mm.

10. The circuit board for driving a light-emitting chip as described in claim 1, 2, 3, 5, 6, 7, or 8, characterized in that, The control circuit layer includes a drive circuit layer and a power circuit layer stacked sequentially on the substrate. A second insulating layer is disposed between the drive circuit layer and the power circuit layer. The signal line and the second wiring layer are respectively connected to the drive circuit layer, and the drive circuit layer is connected to the power circuit layer.

11. A display back panel, characterized in that, It includes a plurality of light-emitting chips and a circuit board for driving the light-emitting chips as described in any one of claims 1 to 10, wherein the light-emitting chips are bonded to the bonding wire group.

12. The display back panel as described in claim 11, characterized in that, The light-emitting chip is either MiniLED or MicroLED.

13. A display screen, characterized in that, It includes a housing and a display back panel as described in claim 11 or 12, the display back panel being mounted on the housing.

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