Digital compatible measurement spectrometer hardware circuitry

Abstract

The utility model discloses a digital coincidence measurement spectrometer hardware circuit system, including two passageways coincidence detector, multichannel nuclear pulse digitization signal processing board card and host computer, two passageways coincidence detector includes support frame and two groups of cerium bromide scintillator detector, the radiation source is installed in the clamping groove, and is located between two groups of cerium bromide scintillator detector, two groups of cerium bromide scintillator detector with the radiation source coaxial setting, each group cerium bromide scintillator detector includes cerium bromide scintillator, photomultiplier and preamplifier, multichannel nuclear pulse digitization signal processing board card includes signal conditioning circuit module, two passageways ADC module, digital signal processing module and communication module, the utility model discloses a digital coincidence measurement spectrometer hardware circuit system can better handle background noise and background radiation to improve the accuracy and reliability of coincidence result, provide more accurate coincidence result.

Description

Technical Field

[0001] This utility model relates to the field of radioactivity measurement technology, specifically to a hardware circuit system for a digital coincidence measurement spectrometer. Background Technology

[0002] Radioactivity is an indicator describing the intensity of radioactivity of a nuclide. As one of the important parameters in nuclear physics, radioactivity measurement is widely used in many nuclear science and related fields. The coincidence measurement method is considered one of the most accurate methods for measuring the radioactivity of cascade decay radionuclides. Under certain conditions, the coincidence measurement method, compared to the ordinary single-counter activity measurement method, makes the measurement results independent of many factors such as detection efficiency, solid angle, and self-absorption of the radioactive source itself, thus resulting in more accurate measurements. Currently, the realization of coincidence measurement mainly uses simulation methods. One commonly used coincidence discrimination method in simulation methods is to use the γ-γ double-peak summation coincidence method to select a simplified energy spectrum. By using the summation of the energies of the cascade rays as a gate signal for characteristic peak selection, the background is removed and the full-energy peaks are highlighted.

[0003] However, simulation methods may introduce a certain degree of error when processing complex signals containing background noise and background radiation; and for high pulse count rates, simulation methods are affected by dead time effects, which are not easy to compensate for flexibly using simulation methods, which may lead to an underestimation of the activity of the radioactive source; in addition, simulation methods also have certain limitations on the range and type of radioactive source activity. Utility Model Content

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a digital coincidence measurement spectrometer hardware circuit system. This system can better handle background noise and background radiation, thereby improving the accuracy and reliability of the coincidence results and providing more precise results.

[0005] The technical solution of this utility model to solve the above-mentioned technical problems is:

[0006] A hardware circuit system for a digital coincidence measurement spectrometer includes a dual-channel coincidence detector, a multi-channel nuclear pulse digitization signal processing board, and a host computer.

[0007] The dual-channel coincidence detector includes a support frame and two sets of cerium bromide scintillator detectors mounted on the support frame. The support frame has a clamping slot for holding a radioactive source. The radioactive source is installed in the clamping slot and positioned between the two sets of cerium bromide scintillator detectors. The two sets of cerium bromide scintillator detectors and the radioactive source are coaxially arranged. Each set of cerium bromide scintillator detectors includes a cerium bromide scintillator, a photomultiplier tube, and a preamplifier. The cerium bromide scintillator captures the radiation emitted by the radioactive source and generates a light signal, which is then sent to the photomultiplier tube. The photomultiplier tube converts the received light signal into an electrical pulse signal and sends it to the preamplifier. The preamplifier processes the electrical pulse signal and outputs a high signal-to-noise ratio signal to a multi-channel nuclear pulse digital signal processing board.

[0008] The multi-channel nuclear pulse digital signal processing board includes a signal conditioning circuit module, a dual-channel ADC module, a digital signal processing module, and a communication module. The signal conditioning circuit module includes an input protection circuit module, a polarity reversal circuit module, a programmable gain circuit module, a DC offset circuit module, and a single-ended to differential circuit module. The high signal-to-noise ratio signal input from the dual-channel coincidence detector sequentially passes through these modules to complete polarity conversion, gain and bias adjustment, forming a differential signal which is then output to the dual-channel ADC module. The dual-channel ADC module converts this differential signal into a digital signal and outputs it to the digital signal processing module. The digital signal processing module uses an FPGA chip. The communication module uploads the digital information acquired by the digital signal processing module to a host computer.

[0009] Preferably, the distance between the cerium bromide scintillator detector and the radiation source is less than 0.1 mm, wherein the radiation source is a 60Co surface radiation source.

[0010] Preferably, the input protection circuit module includes a TLP3250 optocoupler, a passive attenuation circuit, and a protection diode clamping circuit; the high signal-to-noise ratio signal output by the preamplifier enters the input protection circuit module through the SMA interface, and passes sequentially through the TLP3250 optocoupler, the passive attenuation circuit, and the protection diode clamping circuit in the input protection circuit module.

[0011] Preferably, the polarity reversal circuit module includes an inverter and a selection switch, wherein the selection switch is used to select whether to reverse the polarity of the output signal of the inverter.

[0012] Preferably, the programmable gain circuit module includes a digital-to-analog converter and a voltage-controlled gain amplifier, wherein the digital-to-analog converter is model AD5686R and the voltage-controlled gain amplifier is model AD8337.

[0013] Preferably, the DC offset circuit module includes a digital-to-analog converter and an operational amplifier, wherein the digital-to-analog converter is of model AD5686R and is used to generate a DC bias voltage; the operational amplifier is used to superimpose the DC bias voltage onto the original signal.

[0014] Preferably, the single-ended to differential circuit module uses a single-ended to differential chip of model ADA4932-2, which is used to convert analog single-ended signals into differential signals and input them into the differential input pins of the analog-to-digital converter.

[0015] Preferably, the dual-channel ADC module uses an AD9269-80 analog-to-digital converter, which is used to convert differential signals into digital signals and send them to the digital signal processing module.

[0016] Preferably, the FPGA chip is model EP4CE115.

[0017] Preferably, the communication module is an Ethernet communication expansion board, and the Ethernet communication expansion board uses a functional chip of model YT8531C. Compared with the prior art, it has the following advantages:

[0018] 1. The hardware circuit system of the digital coincidence measurement spectrometer of this utility model utilizes the powerful parallel computing capability of the FPGA chip to perform more complex and tedious data simulation, analysis and result optimization, thereby further improving the accuracy of radioactive source activity measurement.

[0019] 2. The digital coincidence measurement spectrometer hardware circuit system of this utility model adopts an FPGA chip as the core of the digital signal processing module, which can be used to process various signals. Compared with traditional DSP chips, FPGA chips have higher flexibility and programmability, and the functions and structure of the processor can be customized as needed. At the same time, FPGA chips also have strong parallel processing capabilities, which can process large amounts of data and complex algorithms, with higher processing speed and lower latency. Attached Figure Description

[0020] Figure 1 This is a hardware structure diagram of the digital coincidence measurement spectrometer hardware circuit system of this utility model.

[0021] Figure 2 This is a block diagram of a digital coincidence measurement spectrometer.

[0022] Figure 3 This is a flowchart of the signal processing for a dual-channel coincidence detector.

[0023] Figure 4 This is a schematic diagram of a polarity reversal circuit module.

[0024] Figure 5 This is the pin diagram of the AD8337 chip.

[0025] Figure 6 This is a schematic diagram of an adder using an operational amplifier.

[0026] Figure 7 This is the circuit diagram for a single-ended to differential circuit module.

[0027] Figure 8 This is the pin diagram of the AD9269 chip.

[0028] Figure 9 This is a pinout diagram of the YT8531C chip.

[0029] Figure 10 This is the circuit diagram for the communication module.

[0030] Figure 11 This is a schematic diagram of the PHY address.

[0031] Figure 12 This is the PCB layout of an Ethernet communication expansion board.

[0032] Figure 13 This is a block diagram of the power module.

[0033] Figure 14 This is the circuit diagram for the LM2596 power conversion module.

[0034] Figure 15 This is the circuit diagram for the LM317 / LM337 power conversion module. Detailed Implementation

[0035] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the implementation of the present invention is not limited thereto.

[0036] See Figure 1 and Figure 2 The hardware circuit system of the digital coincidence measurement spectrometer of this utility model includes a dual-channel coincidence detector, a multi-channel nuclear pulse digital signal processing board, and a host computer.

[0037] See Figure 1 and Figure 2 The dual-channel coincidence detector includes a support frame and two sets of cerium bromide scintillator detectors mounted on the support frame.

[0038] See Figure 3 The support frame is provided with a clamping groove for placing a radioactive source; the radioactive source is installed in the clamping groove and located between two sets of cerium bromide scintillator detectors, and the two sets of cerium bromide scintillator detectors and the radioactive source are coaxially arranged.

[0039] In this embodiment, the radioactive source is 60 Co-faced radiation source; the distance between the cerium bromide scintillator detector and the radiation source is less than 0.1 mm to ensure that the cerium bromide scintillator detector can have a high absorption rate of the radiation emitted by the radiation source.

[0040] See Figure 1 Each set of cerium bromide scintillator detectors includes a cerium bromide scintillator, a photomultiplier tube, and a preamplifier. The cerium bromide scintillator is used to capture the rays emitted by the radiation source and generate an optical signal, which is then sent to the photomultiplier tube. The photomultiplier tube is used to convert the received optical signal into an electrical pulse signal and send it to the preamplifier. The preamplifier is used to process the electrical pulse signal and output a high signal-to-noise ratio signal to a multi-channel nuclear pulse digital signal processing board.

[0041] In this embodiment, the high signal-to-noise ratio signal after being processed by the preamplifier needs to be processed by the preamplifier again.

[0042] See Figure 1 and Figure 2 The multi-channel nuclear pulse digital signal processing board includes a signal conditioning circuit module, a dual-channel ADC module, a digital signal processing module, and a communication module.

[0043] The signal conditioning circuit module is a key component for achieving high-precision measurement and signal processing. It includes an input protection circuit module, a polarity reversal circuit module, a programmable gain circuit module, a DC offset circuit module, a single-ended to differential circuit module, and an ADC driver circuit module. The programmable gain circuit module adjusts the signal amplification factor according to actual needs, ensuring the signal falls within the effective dynamic range of the analog-to-digital converter (ADC). The DC offset circuit module primarily adjusts the signal baseline to maximize the utilization of the ADC's effective dynamic range. The ADC driver circuit module improves the signal's anti-interference capability and signal quality. The high signal-to-noise ratio signal from the dual-channel coincidence detector input sequentially passes through the input protection circuit module, polarity reversal circuit module, programmable gain circuit module, DC offset circuit module, and single-ended to differential circuit module to complete polarity conversion, gain, and bias adjustment, forming a differential signal which is then output to the dual-channel ADC module. The dual-channel ADC module converts this differential signal into a digital signal and outputs it to the digital signal processing module.

[0044] The digital signal processing module uses an FPGA chip, which uses a digital measurement algorithm to process the digital signal and finally measure information such as amplitude and time.

[0045] The communication module is used to send the amplitude, time and other information collected by the digital signal processing module to the host computer to realize the digital coincidence measurement function.

[0046] See Figure 1 and Figure 2 The input protection circuit module includes a TLP3250 optocoupler, a passive attenuation circuit, and a protection diode clamping circuit. The high signal-to-noise ratio (SNR) signal output from the preamplifier enters the input protection circuit module via an SMA interface, and sequentially passes through the TLP3250 optocoupler, the passive attenuation circuit, and the protection diode clamping circuit. This configuration ensures that the high SNR signal output from the preamplifier, after entering the input protection circuit module via the SMA interface, undergoes isolation and passive attenuation via the TLP3250 optocoupler, and is then clamped by the protection diode to achieve overvoltage protection.

[0047] In this embodiment, the TLP3250 optocoupler is a high-bandwidth (up to 100MHz or more) high-speed optical MOS transistor from Toshiba.

[0048] See Figure 4 The polarity reversal circuit module includes an inverter and a selection switch. The selection switch is used to select whether to reverse the polarity of the output signal of the inverter. In this embodiment, the polarity reversal circuit module uses a high-speed operational amplifier as the inverter, and the polarity can be selected by program-controlled multiplexer (i.e., selection switch). For bipolar input ADC schemes, the cost is high and the sampling rate does not meet the project requirements. The randomness of the core pulse signal amplitude will cause the DC offset circuit module to have difficulty and cumbersome adjustment when adjusting the signal amplitude range. Therefore, this embodiment uses a program-controlled multiplexer + inverting operational amplifier to make up for the shortcomings of the first two schemes, thereby achieving the purpose of programmable polarity control. The principle of the polarity reversal circuit module in this embodiment is as follows: Figure 4 As shown.

[0049] See Figure 5 The programmable gain circuit module includes a digital-to-analog converter (DAC) and a voltage-controlled gain amplifier (VGA). The DAC uses Analog Devices' 16-bit DAC chip AD5686R; the VGA also uses Analog Devices' VGA chip AD8337 to provide the control voltage.

[0050] The AD5686R is a low-power, four-channel, 16-bit buffered voltage-output digital-to-analog converter (DAC) with an internal 2.5V, 2ppm / ℃ reference voltage source (default enable and gain selection pins; full-scale output is 2.5V (gain=1) or 5V (gain=2). Both the AD5686R and AD8337 operate from a single 2.7V to 5.5V supply. They are designed to ensure monotonicity and feature gain error of less than 0.1% FSR and offset error of 1.5mV. They are available in 3mm×3mm LFCSP and TSSOP packages and utilize a multi-functional SPI interface with clock rates up to 50MHz.

[0051] The AD8337 is a low-noise, single-ended, linearly distributed gain, general-purpose variable gain amplifier (VGA) that can be used from DC to 100MHz; it has a -3dB bandwidth of 280MHz; its excellent bandwidth uniformity and low output reference noise throughout the gain range make the AD8337 ideal for gain fine-tuning applications and driving high-speed analog-to-digital converters (ADCs).

[0052] With the above settings, the working principle of the programmable gain circuit module is as follows: the FPGA chip sends SPI control frames to set the data value of the 16-bit DAC chip AD5686R to generate an accurate control voltage, thereby controlling the gain of the voltage-controlled gain amplifier (VGA) AD8337.

[0053] See Figure 6 The system employs a positive and negative power supply system to adapt to various detectors that generate positive and negative pulse signals under different bias voltages. However, a differential ADC (analog-to-digital converter with a differential input interface) converts the positive and negative pulse signals into differential voltage signals with DC offset during sampling. For a specific detection system, its output core pulse signal will only be either purely positive or purely negative. Therefore, when using a 16-bit resolution differential ADC, only half of its voltage range can actually be utilized, meaning the actual usable resolution is reduced to 15 bits. To fully utilize the complete voltage range of the differential ADC, a DC offset circuit module is added to the system. When processing positive pulse signals, the DC offset circuit module adjusts the baseline of the pulse signal to approach the negative range of the ADC, thereby fully utilizing the entire range of the differential ADC. Therefore, it is necessary to set up a DC offset circuit module in the signal conditioning circuit. The DC offset circuit module includes a digital-to-analog converter and an operational amplifier. The digital-to-analog converter also uses Analog Devices' 16-bit DAC chip AD5686R to generate a DC bias voltage. The operational amplifier uses a high-speed op-amp as an adder to superimpose the DC bias voltage onto the original signal.

[0054] See Figure 7 The single-ended to differential circuit module is used to input the signal processed by the front-end analog circuit into the analog-to-digital converter (ADC) in the form of a differential signal through the single-ended to differential chip for high-speed sampling. Differential transmission is used to reduce interference during the transmission of sensitive signals.

[0055] In this embodiment, since the high-precision ADC uses differential input to effectively suppress common-mode noise and improve the signal-to-noise ratio, it is necessary to convert the analog single-ended signal into a differential signal before the ADC input. Therefore, the single-ended to differential circuit is crucial in the design. It uses a special circuit architecture to convert the analog single-ended signal into a differential form, which not only resists external noise and interference but also enhances the signal driving capability, making it particularly suitable for stable transmission under high-impedance load environments. Therefore, this embodiment uses Analog Devices' ADA4932-2 to convert the analog single-ended signal into a differential signal and further optimizes the signal quality through an anti-aliasing filter circuit, thereby significantly improving the ADC's signal-to-noise ratio and ensuring accurate energy spectrum measurement. The ADA4932-2 provides two independent differential amplification channels, which increases the system's integration and flexibility, ensuring a fast response to rapidly changing signals. Furthermore, the optimized pin arrangement design of the ADA4932-2 helps simplify the PCB layout, thereby reducing signal distortion and enhancing the overall system performance.

[0056] See Figure 8 The dual-channel ADC module is used to convert differential signals into digital signals and send them to the digital signal processing module. It adopts the AD9269 from Analog Devices. The AD9269 is a single-chip, dual-channel, 16-bit, 80MSPS analog-to-digital converter (ADC) that is powered by a 1.8V power supply and has a built-in high-performance sample-and-hold circuit and an on-chip reference voltage source. Each ADC channel of the dual-channel ADC module is provided with a data output clock (DCO) to ensure the correct latching timing of the receiving logic. When reading the sampled data using the FPGA chip, it is only necessary to read the data output pin at the rising edge of the data output clock (DCO) of each channel.

[0057] The main function of the analog-to-digital converter in this embodiment is to convert continuously changing analog signals (such as voltage, current, etc.) into discrete digital signals so that computers or other digital systems can process, store, and transmit them. The analog-to-digital conversion process usually includes three basic steps: sampling, quantization, and encoding. The performance indicators of the analog-to-digital converter usually include resolution, sampling rate, linearity, signal-to-noise ratio (SNR), total harmonic distortion (THD), conversion rate, and accuracy. Depending on the application requirements, different types of ADCs can be selected, such as successive approximation ADCs and parallel ADCs. In this embodiment, the AD9269-80 from Analog Devices (ADI) can be used to achieve analog-to-digital conversion. The AD9269-80 is a dual-channel ADC with a resolution of 16 bits per channel at a data rate of 80 MSPS, which means it can provide 65,536 levels of voltage quantization accuracy. The AD9269-80 adopts a multi-stage differential pipeline architecture, integrates high-performance sample-and-hold circuitry and an on-chip reference voltage source, has low noise and distortion characteristics, uses a 1.8V power supply, optimizes power consumption, and is widely applicable to various applications such as communication, medical imaging, radar, and nuclear energy spectrum measurement.

[0058] The structure of AD9269-80 is as follows: Figure 8 As shown: The high-speed differential analog signal from the single-ended to differential circuit module is sampled into a discrete digital signal by the high-speed analog-to-digital converter (ADC) and then sent to the FPGA chip for processing.

[0059] See Figure 1 and Figure 2 Since the FPGA chip in this embodiment does not require special interfaces or a large number of multipliers, the cost-effective Cyclone IV series devices from Altera are sufficient to meet the system design requirements. The BGA-484 package is easy to design, therefore the EP4CE115 series, which offers the most resources among this type of chip package, is selected. The EP4CE115 is a medium-to-large-sized FPGA device in Altera's Cyclone IV series, possessing abundant logic resources and high-performance characteristics, suitable for various embedded systems and digital signal processing applications. Furthermore, given the relatively high system clock frequency of 80MHz, to reduce the latency of internal logic units and the chip's own heat generation, the highest speed class I7 suffix is ​​chosen for its model designation.

[0060] After selecting the FPGA chip, the design of the peripheral circuit mainly includes three parts: the non-volatile program loading and download circuit of the system storage, the data transmission circuit between the FPGA and the ADC, and the data interaction interface circuit between the FPGA and the ZYNQ main controller.

[0061] The EP4CE115 chip resources are shown in Table 1:

[0062] Table 1: EP4CE115 Chip Resources

[0063] Logic Cells 114480 Embedded memory (Kbits) 3888 Embedded 18×18 multiplier 266 PLL 4 Global clock network 20 General Purpose Input / Output (GPIO) 528 IO voltage 1.2V, 1.8V, 2.5V

[0064] See Figure 9 The communication module is an Ethernet communication expansion board, which uses a YT8531C functional chip. The YT8531C is a highly integrated Ethernet transceiver that conforms to 10BASE-Te, 100BASE-TX, and 1000BASE-T IEEE 802.3 standards. The YT8531C provides all necessary physical layer functions and can send and receive Ethernet packets via a CAT.5E UTP cable. Data transmission between the MAC and PHY is handled through a simplified Gigabit Media Independent Interface (RGMII).

[0065] The YT8531C supports various RGMII signal voltages, including 3.3V, 2.5V, and 1.8V. It offers several advantages:

[0066] (1) High integration and rich functionality:

[0067] Supports speeds of 10 / 100 / 1000Mbps to meet various application needs. Supports RGMII interface, compatible with multiple MAC chips; built-in functions such as auto-negotiation, polarity detection and correction, echo suppression, baseline drift correction, digital adaptive equalization, etc., to ensure reliable data transmission;

[0068] (2) Flexible power management:

[0069] Supports 3.3V, 2.5V, and 1.8V signal voltages to adapt to different system power requirements. Supports external power supply or internal LDO to power I / O pins, simplifying circuit design and providing greater flexibility;

[0070] (3) Easy-to-use management interface:

[0071] It supports MDIO and MDC serial interfaces for easy chip configuration and monitoring; it also supports multiple LED status indicators for easy understanding of the chip's operating status.

[0072] (4) Miniaturized packaging:

[0073] It uses a 40-pin QFN package, saving board space.

[0074] In summary, the YT8531C boasts advantages such as high integration, rich functionality, flexible power management, ease of use, and a convenient management interface, making it a suitable choice for various embedded systems requiring Ethernet physical layer functionality. Its pinout diagram is shown below. Figure 9 As shown;

[0075] See Figure 10 The YT8531C supports Synchronous Ethernet (Sync-E) functionality, providing a 125MHz or 25MHz synchronous clock source. It supports 18KB large frames (Jumbo Frames), supports the RGMII interface, and offers multiple voltage options. An internal switching regulator (LDO) provides 1.2V to the chip's AVDDL / DVDDL pins, supplying the necessary voltage for the chip's analog and digital circuits. Pins 36 and 37 are the YT8531C's crystal oscillator pins, providing a stable 25MHz clock signal for data transmission and control functions.

[0076] Figure 10 LED_1000 and LED_ACT are LED signals output by the PHY, used to control the LEDs on the RJ45 interface; MDP0 / N0~MDP3 / N3 are differential signal lines between the PHY and the RJ45 interface, used to transmit data.

[0077] The YT8531C has eight analog and digital power supply voltage inputs. The analog circuitry includes an AFE, equalizer, and echo canceller; the digital circuitry includes an RGMII interface, control logic, and a status register. These circuits require high accuracy and stability in the power supply. Furthermore, the internal reference voltage also needs to be obtained from these inputs. Therefore, these power supply pins need to be decoupled to ground to filter out noise and maintain stable pin voltages.

[0078] According to the chip datasheet, the PHY address of the YT8531C chip is determined by the PHYAD0, PHYAD1 and PHYAD2 pins, as shown in Table 2. The PHY address has a total of 3 bits, and the pins PHYAD[2:0] can be set to pull-up or pull-down through the hardware circuit, that is, assigned to high level or low level, i.e. 0 or 1, to represent different addresses.

[0079] Table 2: PHY Address Selection

[0080]

[0081] from Figure 11 As can be seen, the Ethernet PHY chip PHYAD2 is connected to a pull-up resistor, while PHYAD1 and PHYAD0 are connected to pull-down resistors. Therefore, the PHY address is 5'h04.

[0082] In summary, Ethernet data transmission cannot be separated from the support of Ethernet PHY (physical layer) chips. The physical layer defines the electrical signals, line states, clock references, data encoding, and circuits required for data transmission and reception, and provides standard interfaces to data link layer devices.

[0083] In addition, board-to-board connectors are used to connect the Ethernet communication expansion board and the FPGA core board, as well as the FPGA core board and four external analog signal SMA interfaces. Ferrite beads are used to connect the analog ground and digital ground of the SMA interfaces to minimize interference from the digital circuitry to the analog circuitry. During the actual PCB layout design, considering the potential interference of noise to data transmission, power supply filter capacitors are distributed near the chip pins. To address the timing issues of the two differential signals in the Ethernet circuit, equal-length routing is used to ensure that data transmission takes equal time on the differential lines, thus avoiding phase differences caused by unequal line lengths and preventing data transmission errors.

[0084] See Figure 13 The hardware circuit system of the digital coincidence measurement spectrometer of this utility model also includes a power supply module. Since it needs to comply with the NIM standard, which specifies standard voltages of DC ±24.00V, ±12.00V, ±6.00V and AC 117V, and the standard voltage required by the plug-in is obtained through the NIM chassis, this embodiment uses DC 12V to power the entire system. The power supply design of the entire system is as follows: Figure 13 As shown.

[0085] The analog circuitry of a multi-channel core pulse digital signal processing board mainly consists of a signal conditioning circuit module and a dual-channel ADC module. Therefore, the requirements for the output noise level and power supply ripple rejection ratio (PSRR) of the power supply module are the highest. To ensure that the analog signal is not interfered with, the selection of the analog power management chip for powering the analog circuit primarily considers LDO chips with high PSRR. Secondly, due to the design of the multi-channel core pulse digital signal processing board, although most of the operational amplifiers used in the analog circuits are low-power products, the highest power consumption voltage-controlled gain amplifier, AD8337, has a quiescent power consumption of 1 kW. The maximum analog power supply current of the high-speed ADC chip AD9269-80 is 120mA, but this also places certain requirements on the current output of the power supply module. This embodiment uses the LT3094 and LT3045, two ultra-low noise, ultra-high PSRR linear regulators, to provide ±5V power to the operational amplifier in the analog circuit, with a maximum output current of 500mA. The low-noise, fast transient response LT1963-2.5 and LT1963-1.8 are used to provide power and low-noise reference levels for the analog terminals of components such as the DAC and ADC, with a maximum output current of 1500mA. The peripheral circuit design of these chips is simple, and they have the advantages of low output power supply ripple and high output current, which can effectively improve the system's immunity to power supply noise, thereby ensuring the system's stability and accuracy.

[0086] The digital circuitry section of the multi-channel nuclear pulse digital signal processing board is the main power-consuming area of ​​the system. The regulated power supply requirements are +3.3V, +2.5V, +1.8V, and +1.2V, involving the power supply and level reference of multiple chips such as the ADC, FPGA, and USB. Therefore, the requirements for the drive current and dynamic response capability of the power supply chip are high. Thus, this embodiment uses the low-noise, fast-transient-response LT1963-2.5, LT1963-1.8, and TLV62130 to achieve low-noise voltages of +2.5V, +1.8V, and +1.2V, respectively, mainly for the reference level of the digital terminal of the high-speed ADC and the core power supply of the FPGA chip. The LM3940 and TPS731 are used to output +3.3V and +2.5V to drive the high-speed USB transmission circuit.

[0087] The Ethernet communication expansion board primarily powers the Ethernet communication circuit and the multi-channel core pulse digital signal processing board. To ensure circuit performance, the LM2596 is selected, featuring a 3A output current drive capability, a regulated output of 3.3V, and high efficiency, low ripple, high line regulation, and load regulation. Furthermore, the LM2596 incorporates built-in functions such as hysteresis enable, over-temperature protection, over-current protection, and secondary over-current protection. The peripheral circuitry for the LM2596 is constructed as follows... Figure 14 As shown.

[0088] To ensure circuit performance and achieve the required voltage value, the LM317 and LM337, with an adjustable output voltage range of 1.25V to 37V, capable of providing over 1.5A of current and featuring overload protection, were selected. These are adjustable three-terminal positive and negative voltage regulators, respectively. The output voltage can be set using only two external resistors. Internally, they contain a 1.25V voltage reference. The two external resistors R1 and R2 form a voltage divider, feeding a portion of the output voltage back to the adjustment terminal (ADJ). This feedback voltage is then compared with the internal reference voltage. Based on the comparison result, the output current is adjusted to maintain the output voltage at the set value. The external circuit construction for the LM317 and LM337 is as follows. Figure 15 As shown:

[0089] Output voltage calculation formula:

[0090] ;

[0091] In the formula: The reference voltage is 1.25V. Typically 50μA, which is negligible in most cases; therefore, the output voltage... =1.25×(1+816 / 240)+(0×816)=5.5V; therefore, the system design is satisfied.

[0092] See Figures 1-15 The working principle of the hardware circuit system of the digital coincidence measurement spectrometer of this utility model is as follows:

[0093] The radiation source is installed in the clamping slot of the support frame, and then the radiation emitted by the radiation source is captured by the cerium bromide scintillators in the two sets of cerium bromide scintillator detectors in the dual-channel coincidence detector, generating an optical signal. The generated optical signal is sent to the photomultiplier tube; the photomultiplier tube converts the received optical signal into an electrical pulse signal and sends it to the preamplifier; the preamplifier is used to process the electrical pulse signal and output a high signal-to-noise ratio signal to the multi-channel nuclear pulse digital signal processing board.

[0094] The signal conditioning circuit module in the multi-channel nuclear pulse digital signal processing board conditions the high signal-to-noise ratio signal. Specifically, the polarity of the high signal-to-noise ratio signal is reversed by the polarity reversal circuit module, and the polarity-reversed signal is sent to the programmable gain circuit module. This module adjusts the signal gain, allowing the signal amplification factor to be adjusted as needed to ensure the signal falls within the effective dynamic range of the analog-to-digital converter (ADC). After gain adjustment, the signal is sent to the DC offset circuit module, which adjusts the signal bias, primarily by adjusting the signal baseline to maximize the utilization of the ADC's effective dynamic range. Finally, the analog single-ended signal is converted to a differential signal by the single-ended to differential circuit module and sent to the dual-channel ADC module.

[0095] The dual-channel ADC module converts the differential signal into a digital signal and outputs it to the digital signal processing module. The digital signal processing module uses an FPGA chip to process the digital signal, and finally measures information such as amplitude and time, and sends it to the host computer through the communication module.

[0096] When the host computer receives information such as amplitude and time, it extracts the trigger input timestamps and amplitude values ​​of the two channels and then compares them. If the timestamps of the two pulses are close to equal, and the amplitude values ​​of the two pulses fall within the threshold ranges of the 1.17MeV γ window and the 1.33MeV γ window, respectively, a coincidence event can be identified. To facilitate the observation of the triggered pulse signals, the above-mentioned coincidence event identification function is described as being performed on the host computer.

[0097] The above are preferred embodiments of the present utility model, but the embodiments of the present utility model are not limited to the above content. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present utility model shall be considered equivalent substitutions and shall be included within the protection scope of the present utility model.

Claims

1. A hardware circuit system for a digital coincidence measurement spectrometer, characterized in that, This includes a dual-channel coincidence detector, a multi-channel nuclear pulse digital signal processing board, and a host computer. The dual-channel coincidence detector includes a support frame and two sets of cerium bromide scintillator detectors mounted on the support frame. The support frame has a clamping slot for holding a radioactive source. The radioactive source is installed in the clamping slot and positioned between the two sets of cerium bromide scintillator detectors. The two sets of cerium bromide scintillator detectors and the radioactive source are coaxially arranged. Each set of cerium bromide scintillator detectors includes a cerium bromide scintillator, a photomultiplier tube, and a preamplifier. The cerium bromide scintillator captures the radiation emitted by the radioactive source and generates a light signal, which is then sent to the photomultiplier tube. The photomultiplier tube converts the received light signal into an electrical pulse signal and sends it to the preamplifier. The preamplifier processes the electrical pulse signal and outputs a high signal-to-noise ratio signal to a multi-channel nuclear pulse digital signal processing board. The multi-channel nuclear pulse digital signal processing board includes a signal conditioning circuit module, a dual-channel ADC module, a digital signal processing module, and a communication module. The signal conditioning circuit module includes an input protection circuit module, a polarity reversal circuit module, a programmable gain circuit module, a DC offset circuit module, and a single-ended to differential circuit module. The high signal-to-noise ratio signal input from the dual-channel coincidence detector sequentially passes through these modules to complete polarity conversion, gain and bias adjustment, forming a differential signal which is then output to the dual-channel ADC module. The dual-channel ADC module converts this differential signal into a digital signal and outputs it to the digital signal processing module. The digital signal processing module uses an FPGA chip. The communication module uploads the digital information acquired by the digital signal processing module to a host computer.

2. The hardware circuit system of the digital coincidence measurement spectrometer according to claim 1, characterized in that, The distance between the cerium bromide scintillator detector and the radiation source is less than 0.1 mm, wherein the radiation source is... 60 Co-face radiation source.

3. The hardware circuit system of the digital coincidence measurement spectrometer according to claim 2, characterized in that, The input protection circuit module includes a TLP3250 optocoupler, a passive attenuation circuit, and a protection diode clamping circuit. The high signal-to-noise ratio signal output by the preamplifier enters the input protection circuit module through the SMA interface and passes sequentially through the TLP3250 optocoupler, the passive attenuation circuit, and the protection diode clamping circuit in the input protection circuit module.

4. The hardware circuit system of the digital coincidence measurement spectrometer according to claim 3, characterized in that, The polarity reversal circuit module includes an inverter and a selection switch, wherein the selection switch is used to select whether to reverse the polarity of the output signal of the inverter.

5. The hardware circuit system of the digital coincidence measurement spectrometer according to claim 4, characterized in that, The programmable gain circuit module includes a digital-to-analog converter and a voltage-controlled gain amplifier, wherein the digital-to-analog converter is model AD5686R and the voltage-controlled gain amplifier is model AD8337.

6. The hardware circuit system of the digital coincidence measurement spectrometer according to claim 5, characterized in that, The DC offset circuit module includes a digital-to-analog converter and an operational amplifier. The digital-to-analog converter is model AD5686R and is used to generate a DC bias voltage. The operational amplifier is used to superimpose the DC bias voltage onto the original signal.

7. The hardware circuit system of the digital coincidence measurement spectrometer according to claim 6, characterized in that, The single-ended to differential circuit module uses an ADA4932-2 single-ended to differential chip, which is used to convert analog single-ended signals into differential signals and input them to the differential input pins of the analog-to-digital converter.

8. The hardware circuit system of the digital coincidence measurement spectrometer according to claim 6, characterized in that, The dual-channel ADC module uses an AD9269-80 analog-to-digital converter, which is used to convert differential signals into digital signals and send them to the digital signal processing module.

9. The hardware circuit system of the digital coincidence measurement spectrometer according to claim 1, characterized in that, The FPGA chip is model EP4CE115.

10. The hardware circuit system of the digital coincidence measurement spectrometer according to claim 6, characterized in that, The communication module is an Ethernet communication expansion board, which uses a YT8531C functional chip.

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